JP2689536B2 - Method for manufacturing semiconductor wafer - Google Patents
Method for manufacturing semiconductor waferInfo
- Publication number
- JP2689536B2 JP2689536B2 JP28459088A JP28459088A JP2689536B2 JP 2689536 B2 JP2689536 B2 JP 2689536B2 JP 28459088 A JP28459088 A JP 28459088A JP 28459088 A JP28459088 A JP 28459088A JP 2689536 B2 JP2689536 B2 JP 2689536B2
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- JP
- Japan
- Prior art keywords
- stopper
- semiconductor
- polishing
- semiconductor wafer
- thickness
- Prior art date
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Description
【発明の詳細な説明】 以下の順序に従って本発明を説明する。DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.
A.産業上の利用分野 B.発明の概要 C.背景技術［第３図］ D.発明が解決しようとする問題点［第４図］ E.問題点を解決するための手段 F.作用 G.実施例［第１図、第２図］ H.発明の効果 （A.産業上の利用分野） 本発明は半導体ウエハの製造方法、特に厚さが均一で
平坦度の高い半導体ウエハを得ることができる新規な半
導体ウエハの製造方法に関する。A. Industrial field of use B. Outline of invention C. Background art [Fig. 3] D. Problems to be solved by the invention [Fig. 4] E. Means for solving problems F. Action G Example [FIGS. 1 and 2] H. Effects of the Invention (A. Field of Industrial Application) The present invention is a method for manufacturing a semiconductor wafer, and in particular, obtains a semiconductor wafer having a uniform thickness and high flatness. The present invention relates to a novel method for manufacturing a semiconductor wafer.
（B.発明の概要） 本発明は、半導体ウエハの製造方法において、 半導体層の厚さが均一になるようにするため、 半導体中に厚さの異なる対研摩用のストッパーを形成
し、半導体を一方の主面から厚い方のストッパーが露出
するまで研摩し、次に該ストッパーを薄い方のストッパ
ー以下の厚さになるように除去し、その後半導体の上記
一方の主面を薄い方のストッパーが露出するまで研摩す
るものである。(B. Outline of the Invention) In the present invention, in the method for manufacturing a semiconductor wafer, in order to make the thickness of the semiconductor layer uniform, stoppers for polishing having different thicknesses are formed in the semiconductor to form the semiconductor. Polish until the thicker stopper is exposed from one main surface, then remove the stopper so that the thickness is less than or equal to the thinner stopper, and then remove the one main surface of the semiconductor by the thinner stopper. It is to polish until it is exposed.
（C.背景技術）［第３図］ SOI型半導体基板の製造方法として貼り合せを利用し
た技術が本願出願人会社によって開発されている。第３
図（Ａ）乃至（Ｄ）はその開発された製造方法を工程順
に示す断面図である。(C. Background Art) [FIG. 3] A technology utilizing bonding as a method for manufacturing an SOI type semiconductor substrate has been developed by the applicant company. Third
6A to 6D are cross-sectional views showing the developed manufacturing method in the order of steps.
（Ａ）シリコン半導体基板ａの一方の表面を選択的に
エッチングすることにより第３図（Ａ）に示すように深
さ約1000Åの凹部ｂ、ｂ、……を形成する。該凹部ｂ、
ｂ、……によって囲繞された領域ｃ、ｃ、……が後で素
子形成用半導体層となる。(A) One surface of the silicon semiconductor substrate a is selectively etched to form recesses b, b, ... With a depth of about 1000Å as shown in FIG. 3 (A). The recess b,
Regions c, c, ... Surrounded by b, ... Will later become semiconductor layers for element formation.
（Ｂ）次に、同図（Ｂ）に示すように半導体基板ａの
上記表面上にシリコン酸化層SiO2（厚さ例えば１μｍ）
ｄを形成する。(B) Next, as shown in FIG. 7B, a silicon oxide layer SiO 2 (thickness of 1 μm, for example) is formed on the surface of the semiconductor substrate a.
forming d.
（Ｃ）次に、同図（Ｃ）に示すように上記シリコン酸
化層ｄの表面にシリコン半導体基板ｅを貼り合せる。該
半導体基板ｅが最終的にSOI型半導体基板の基板とな
る。(C) Next, as shown in FIG. 7C, a silicon semiconductor substrate e is attached to the surface of the silicon oxide layer d. The semiconductor substrate e finally becomes the substrate of the SOI type semiconductor substrate.
（Ｄ）次に、半導体基板ａを裏面［第３図（Ｄ）にお
ける下側の面］から研摩して同図（Ｄ）に示すようにシ
リコン酸化層ｄの表面を露出させる。シリコン酸化層
（SiO2）ｄは硬度が高いので研摩に対してのストッパー
となる。(D) Next, the semiconductor substrate a is polished from the back surface [the lower surface in FIG. 3 (D)] to expose the surface of the silicon oxide layer d as shown in FIG. 3 (D). Since the silicon oxide layer (SiO 2 ) d has a high hardness, it serves as a stopper for polishing.
すると、シリコン酸化層ｄによって半導体層ｃ、ｃ、
……が散在する半導体ウエハが出来上ることになる。勿
論、半導体ウエハの第３図（Ｄ）における下側の面が半
導体ウエハ表面になる。Then, the silicon oxide layer d causes the semiconductor layers c, c,
A semiconductor wafer with scattered dots will be completed. Of course, the lower surface of the semiconductor wafer in FIG. 3D is the semiconductor wafer surface.
（D.発明が解決しようとする問題点）［第４図］ ところで、第３図に示す半導体ウエハの製造方法によ
れば、第４図に示すように半導体層ｃ、ｃ、……の厚さ
が不均一になるという問題があった。というのは、シリ
コン半導体ウエハは４乃至８インチ程度の大きさを有
し、そのような大きさを有するシリコン半導体ウエハを
600μｍ程度も研摩すると、１〜２μｍ程度の厚さのバ
ラツキが生じてしまうからであり、その結果、ある部分
では第４図の左側の部分のように半導体層ｃ、ｃ、……
が厚くなり過ぎて半導体層ｃ、ｃ、……間がシリコンを
通じて繋ってしまい、ある部分では第４図の右側の部分
のように半導体層ｃ、ｃ、……が薄くなったりする。
尚、この部分ではストッパーであるシリコン酸化層ｄが
多少は削られて薄くなってしまうことになる。従って、
極端な場合半導体層ｃ、ｃ、……が研摩により完全にな
くなってしまうところも生じてしまう。これでは歩留り
が悪くなり、IC、LSI、VLSIの低価格化が阻まれてしま
うことになるので看過できない問題であった。(D. Problems to be Solved by the Invention) [FIG. 4] By the way, according to the method for manufacturing a semiconductor wafer shown in FIG. 3, the thickness of the semiconductor layers c, c ,. There was a problem that the thickness was non-uniform. This is because a silicon semiconductor wafer has a size of about 4 to 8 inches, and a silicon semiconductor wafer having such a size is used.
This is because when polishing is performed for about 600 μm, variations in thickness of about 1 to 2 μm occur, and as a result, at some portions, the semiconductor layers c, c, ...
Become too thick and the semiconductor layers c, c, ... Are connected through silicon, and the semiconductor layers c, c ,.
In this portion, the silicon oxide layer d, which is the stopper, is slightly shaved and thinned. Therefore,
In an extreme case, the semiconductor layers c, c, ... May be completely removed by polishing. This is a problem that cannot be overlooked because the yield becomes poor and the price reduction of ICs, LSIs, and VLSIs is hindered.
本発明はこのような問題点を解決すべく為されたもの
であり、均一な厚さの半導体層が形成されるようにする
ことを目的とする。The present invention has been made to solve such problems, and an object thereof is to form a semiconductor layer having a uniform thickness.
（E.問題点を解決するための手段） 本発明半導体ウエハの製造方法は上記問題点を解決す
るため、半導体中に厚さの異なる対研摩用のストッパー
を形成し、半導体を一方の主面から厚い方のストッパー
が露出するまで研摩し、次に該ストッパーを薄い方のス
トッパー以下の厚さになるように除去し、その後半導体
の上記一方の主面を薄い方のストッパーが露出するまで
研摩をすることを特徴とする。(E. Means for Solving Problems) In order to solve the above problems, the method for manufacturing a semiconductor wafer according to the present invention forms stoppers for polishing having different thicknesses in a semiconductor to form the semiconductor on one main surface. To a thick stopper exposed, then remove the stopper to a thickness less than or equal to the thin stopper, and then polish one of the main surfaces of the semiconductor until the thin stopper is exposed. It is characterized by doing.
（F.作用） 本発明半導体ウエハの製造方法によれば、第１の研磨
によって半導体ウエハ全体で１〜２μｍ程度の厚さムラ
が生じてもその研摩の終了後第１のストッパーを除去し
てしまうので、その段階で厚さムラがほとんどなくな
る。そして、厚さムラがなくなった表面に対して仕上げ
にあたる第２の研摩を行うので、最終的に生じる厚さム
ラはこの研摩において生じた僅かな厚さムラ程度の小さ
さになる。従って、従来のように研摩を一度で済ます方
法の場合に比較して厚さムラを非常に小さくすることが
できる。(F. Action) According to the method for manufacturing a semiconductor wafer of the present invention, even if a thickness unevenness of about 1 to 2 μm occurs in the entire semiconductor wafer due to the first polishing, the first stopper is removed after the polishing is completed. Since it will end up, there will be almost no thickness unevenness at that stage. Then, since the second polishing, which is the finishing, is performed on the surface where the thickness unevenness has disappeared, the finally produced thickness unevenness is as small as the slight thickness unevenness caused by this polishing. Therefore, the thickness unevenness can be made extremely small as compared with the conventional method in which polishing is performed only once.
（G.実施例）［第１図、第２図］ 以下、本発明半導体ウエハの製造方法を図示実施例に
従って詳細に説明する。(G. Embodiment) [FIGS. 1 and 2] Hereinafter, a method for manufacturing a semiconductor wafer of the present invention will be described in detail with reference to illustrated embodiments.
第１図及び第２図は本発明半導体ウエハの製造方法の
一つの実施例を説明するためのものであり、第１図
（Ａ）乃至（Ｆ）は製造方法を工程順に示す断面図であ
る。1 and 2 are for explaining one embodiment of the method for manufacturing a semiconductor wafer according to the present invention, and FIGS. 1A to 1F are sectional views showing the manufacturing method in the order of steps. .
（Ａ）先ず、同図（Ａ）に示すように、半導体基板１
の表面部に数千Å程度の深さの凹部２と、1000Å程度か
あるいはそれ以下の浅い凹部３を形成する。深い凹部２
はスクライブ領域となる部分に形成し、浅い凹部３はス
クライブ領域に囲繞された各半導体チップとなるべき部
分内における各フィールド絶縁膜を形成すべき部分に形
成する。尚、深い凹部２と浅い凹部３とはどちらを先に
形成するようにしても良い。(A) First, as shown in FIG.
A concave portion 2 having a depth of about several thousand Å and a shallow concave portion 3 having a depth of about 1000 Å or less are formed on the surface of the. Deep recess 2
Is formed in a portion to be a scribe region, and the shallow recess 3 is formed in a portion to be each semiconductor chip surrounded by the scribe region in which each field insulating film is to be formed. Either the deep recess 2 or the shallow recess 3 may be formed first.
（Ｂ）次に、半導体基板１の表面部にシリコン酸化層
（SiO2）４を例えばCVDにより形成し、しかる後該シリ
コン酸化層４の表面を平坦化する。同図（Ｂ）は平坦化
処理後の状態を示す。尚、５はシリコン酸化層４の深い
凹部２を埋める部分で、第１のストッパーを成す。６は
同じく浅い凹部３を埋める部分で第２のストッパーを成
す。(B) Next, a silicon oxide layer (SiO 2 ) 4 is formed on the surface of the semiconductor substrate 1 by, for example, CVD, and then the surface of the silicon oxide layer 4 is flattened. FIG. 3B shows the state after the flattening process. Reference numeral 5 is a portion that fills the deep recess 2 of the silicon oxide layer 4 and serves as a first stopper. Reference numeral 6 is a portion that also fills the shallow recessed portion 3 and forms a second stopper.
（Ｃ）次に、同図（Ｃ）に示すようにシリコン酸化層
４の表面に半導体基板７を貼り合せる。この半導体基板
７が最終的に半導体ウエハの基板になる。(C) Next, the semiconductor substrate 7 is bonded to the surface of the silicon oxide layer 4 as shown in FIG. This semiconductor substrate 7 finally becomes the substrate of the semiconductor wafer.
（Ｄ）次に、同図（Ｄ）に示すように半導体基板の底
面をシリコン酸化層４の第１ののストッパー５が露出す
るまで研摩する。(D) Next, as shown in FIG. 3D, the bottom surface of the semiconductor substrate is polished until the first stopper 5 of the silicon oxide layer 4 is exposed.
第２図は研摩に用いるポリッシング装置の一例を示す
横式的断面図であり、８は定盤、９、９はヘッド、10、
10は該ヘッド９、９に取り付けられたマウントプレート
で、該マウントプレート10、10にワックス11を介して被
研摩半導体ウエハＷが固着されている。そして、研摩
は、研摩剤12を半導体ウエハＷの被研摩面と定盤８との
間に介在させてヘッド９、９ンにより半導体ウエハＷを
定盤８に対して相対的に移動させることにより行う。研
摩剤としては高純度石英の微粒子（粒度例えば0.02μｍ
程度）をpH10〜11のアルカリ溶液内に分散させたものが
好適であり、半導体ウエハＷを定盤８に対して僅かに間
隔をおいた状態で回転させ、定盤８上に研磨剤12を滴下
することにより行う。無論、研摩布を半導体ウエハＷの
表面に接触させながら研摩するという従来の研摩方法を
採用しても良いが、この研摩方法によれば、研摩布が半
導体ウエハＷの面に沿って圧縮変形する余地があるの
で、研摩剤による研摩の方がより好ましいといえる。FIG. 2 is a horizontal sectional view showing an example of a polishing device used for polishing. 8 is a surface plate, 9 and 9 are heads, 10 and
Reference numeral 10 denotes a mount plate attached to the heads 9 and 9, and the semiconductor wafer W to be polished is fixed to the mount plates 10 and 10 via a wax 11. The polishing is performed by interposing an abrasive 12 between the surface to be polished of the semiconductor wafer W and the surface plate 8 and moving the semiconductor wafer W relative to the surface plate 8 by the heads 9 and 9. To do. Fine particles of high-purity quartz (particle size, for example, 0.02 μm)
Is dispersed in an alkaline solution having a pH of 10 to 11, and the semiconductor wafer W is rotated at a slight distance from the surface plate 8 to form the polishing agent 12 on the surface plate 8. This is done by dropping. Needless to say, a conventional polishing method in which the polishing cloth is brought into contact with the surface of the semiconductor wafer W to perform polishing may be adopted, but according to this polishing method, the polishing cloth is compressed and deformed along the surface of the semiconductor wafer W. Since there is room, it can be said that polishing with an abrasive is more preferable.
（Ｅ）次に半導体ウエハ１の表面側に露出したシリコ
ン酸化層４の第１のストッパー５をRIE又はウエットエ
ッチングにより除去する。第１図（Ｅ）は第１のストッ
パー５除去後の状態を示す。本実施例においては第１の
ストッパー５をその厚さ分完全に除去しているが必ずし
もそのようにすることは必要ではないが、しかし少なく
とも第１のストッパー５の厚さが第２のストッパー６の
厚さ以下になるように研摩することが必要である。(E) Next, the first stopper 5 of the silicon oxide layer 4 exposed on the front surface side of the semiconductor wafer 1 is removed by RIE or wet etching. FIG. 1 (E) shows a state after the first stopper 5 is removed. In this embodiment, the first stopper 5 is completely removed by the thickness thereof, but it is not always necessary to do so, but at least the thickness of the first stopper 5 is the second stopper 6. It is necessary to grind so that the thickness is less than or equal to.
（Ｆ）その後、２回目の研摩を同図（Ｆ）に示すよう
にシリコン酸化層４の第２のストッパー６、６、……表
面が露出するまで行う。1a、1a、……は、トランジスタ
等の素子が形成されるところのシリコン酸化層からなる
第２のストッパー６、６……により分離された半導体層
である。この第２のストッパー６、６、……はそのまま
フィールド絶縁膜となる。この研摩も上述した第１回目
の研摩と同じ方法で行うと良い。勿論、研摩布を用いた
従来の研摩方法で研摩するようにしても良い。(F) After that, the second polishing is performed until the surfaces of the second stoppers 6, 6, ... Of the silicon oxide layer 4 are exposed as shown in FIG. The semiconductor layers 1a, 1a, ... Are separated by the second stoppers 6, 6 ... Which are made of a silicon oxide layer where elements such as transistors are formed. The second stoppers 6, 6, ... Become the field insulating film as they are. This polishing may be performed in the same manner as the above-mentioned first polishing. Of course, the polishing may be performed by a conventional polishing method using a polishing cloth.
この半導体ウエハの製造方法は半導体ウエハの貼り合
せ後の研摩を２段階で行うもので、最初の研摩において
はスクライブ領域に位置された第１のストッパー５をス
トッパーとしており、マクロ的な平坦化が為される。こ
の段階では研摩によって生じた第１のストッパー５の厚
さのバラツキが大体そのまま半導体ウエハの厚さのバラ
ツキとなっており、ウエハ全体でバラツキが１〜２μｍ
程度にもなる。しかし、最初の研摩の終了後において第
１のストッパー５を少なくとも第２のストッパー６と同
じかそれよりも薄くなるように除去した後第２のストッ
パー６をストッパーとする研摩を行うので第１のストッ
パー５が有していた厚さのバラツキは消滅する。謂わば
御破算になる。そして、第２のストッパー６をストッパ
ーとする研摩によって各半導体チップというミクロな領
域内における平坦化を実現することができる。即ち、半
導体基板１の裏面は第１回目の研摩が終了した段階では
厚さにバラツキが生じているが、厚さのバラツキの生じ
ている耐研摩物であるシリコン酸化物からなる第１のス
トッパー５はその後直ちに除去され、その後表面に残っ
ているのは半導体だけとなる。そして、その半導体は被
研摩物であり、その厚さのバラツキは第２回目の研摩の
過程ではほとんど解消される。そして、第２のストッパ
ー６、６、……の厚さのバラツキが半導体ウエハの厚さ
のバラツキとなるが基本的に第２のストッパー６、６、
……は膜厚が略均一であり、僅かな厚さの半導体を研磨
する第２回目の研摩工程では第１回目の研摩工程の場合
と異なりストッパー６、６、……はほとんど削られな
い。従って、各半導体層を非常に均一な膜厚にすること
ができる。In this method for manufacturing a semiconductor wafer, polishing after bonding the semiconductor wafers is performed in two steps. In the first polishing, the first stopper 5 located in the scribe region is used as a stopper, and macro planarization is performed. Done At this stage, the variation in the thickness of the first stopper 5 caused by polishing becomes the variation in the thickness of the semiconductor wafer as it is, and the variation in the entire wafer is 1 to 2 μm.
It also becomes a degree. However, after the first polishing, the first stopper 5 is removed so as to be at least as thin as or thinner than the second stopper 6, and then the second stopper 6 is used as a stopper for polishing. The variation in the thickness of the stopper 5 disappears. So to speak Then, by the polishing using the second stopper 6 as a stopper, it is possible to realize the flattening in the micro area of each semiconductor chip. That is, the back surface of the semiconductor substrate 1 has a variation in thickness at the stage when the first polishing is completed, but the first stopper made of silicon oxide, which is an abrasion resistant material with variation in thickness, is formed. 5 is removed immediately thereafter, and only the semiconductor remains on the surface thereafter. The semiconductor is an object to be polished, and variations in its thickness are almost eliminated in the process of the second polishing. Then, the variation in the thickness of the second stoppers 6, 6, ... Becomes the variation in the thickness of the semiconductor wafer, but basically the second stoppers 6, 6,
... has a substantially uniform film thickness, and the stoppers 6, 6, ... are hardly removed in the second polishing step for polishing a semiconductor having a small thickness, unlike the first polishing step. Therefore, each semiconductor layer can have a very uniform film thickness.
（H.発明の効果） 以上に述べたように、本発明半導体ウエハの製造方法
は、半導体中に研摩されにくい材料からなる第１のスト
ッパーと該第１のストッパーよりも薄い第２のストッパ
ーを少なくとも形成する工程と、上記半導体を第１のス
トッパーが露出するまで研摩する工程と、上記第１のス
トッパーを少なくとも第２のストッパーの厚さと等しく
なるまで除去する工程と、上記半導体を第２のストッパ
ーが露出するまで研摩する工程と、を有することを特徴
とする半導体ウエハの製造方法 従って、本発明半導体ウエハの製造方法によれば、第
１回目の研摩によって半導体ウエハ全体で例えば１〜２
μｍ程度の比較的大きな厚さムラが生じてもその研摩の
終了後第１のストッパーを除去してしまうので、その段
階で厚さムラがほとんどなくなる。そして、厚さムラが
なくなった表面に対して仕上げにあたる第２回目の研摩
を行うので、最終的に生じる厚さムラはこの研摩におい
て生じた僅かな厚さムラ程度の小ささになる。従って、
従来のように研磨を一度で済ます方法の場合に比較して
厚さムラを非常に小さくすることができる。(H. Effect of the Invention) As described above, in the method for manufacturing a semiconductor wafer of the present invention, the first stopper made of a material that is hard to be abraded in the semiconductor and the second stopper thinner than the first stopper are used. At least forming, polishing the semiconductor until the first stopper is exposed, removing the first stopper to a thickness at least equal to the second stopper, and removing the semiconductor from the second stopper. And a step of polishing until the stopper is exposed. Therefore, according to the method of manufacturing a semiconductor wafer of the present invention, for example, 1 to 2 is applied to the entire semiconductor wafer by the first polishing.
Even if a relatively large thickness unevenness of about .mu.m occurs, the first stopper is removed after the polishing, so that there is almost no thickness unevenness at that stage. Then, since the second polishing, which is finishing, is performed on the surface from which the thickness unevenness has disappeared, the thickness unevenness finally produced is as small as the slight thickness unevenness generated in this polishing. Therefore,
The thickness unevenness can be made extremely small as compared with the conventional method in which polishing is performed only once.
第１図及び第２図は本発明半導体ウエハの製造方法の一
つの実施例を説明するためのもので、第１図（Ａ）乃至
（Ｆ）は製造方法を工程順に示す断面図、第２図は研摩
に用いるポリッシング装置を示す模式断面図、第３図
（Ａ）乃至（Ｄ）は背景技術を工程順に示す断面図、第
４図は発明が解決しようとする問題点を示す断面図であ
る。 符号の説明 １、７……半導体、 ５……第１のストッパー、 ６……第２のストッパー、 ８……定盤、12……研摩剤、 Ｗ……被研摩半導体ウエハ。FIGS. 1 and 2 are for explaining one embodiment of a method for manufacturing a semiconductor wafer according to the present invention, and FIGS. 1A to 1F are sectional views showing the manufacturing method in the order of steps, FIG. FIG. 3 is a schematic cross-sectional view showing a polishing device used for polishing, FIGS. 3A to 3D are cross-sectional views showing the background art in the order of steps, and FIG. 4 is a cross-sectional view showing problems to be solved by the invention. is there. DESCRIPTION OF SYMBOLS 1, 7 ... Semiconductor, 5 ... First stopper, 6 ... Second stopper, 8 ... Surface plate, 12 ... Abrasive, W ... Polished semiconductor wafer.
Claims (5)
１のストッパーと該第１のストッパーよりも薄い第２の
ストッパーを少なくとも形成する工程と、 上記半導体を第１のストッパーが露出するまで研磨する
工程と、 上記第１のストッパーを少なくとも第２のストッパーの
厚さと等しくなるまで除去する工程と、 上記半導体を第２のストッパーが露出するまで研摩する
工程と、 を有することを特徴とする半導体ウエハの製造方法1. A step of forming at least a first stopper made of a material which is hard to be abraded in a semiconductor and a second stopper thinner than the first stopper, and polishing the semiconductor until the first stopper is exposed. And a step of removing the first stopper until the thickness of the second stopper is equal to at least the thickness of the second stopper, and a step of polishing the semiconductor until the second stopper is exposed. Wafer manufacturing method
造方法2. The method of manufacturing a semiconductor wafer according to claim 1, wherein the semiconductor is made of silicon.
クライブ領域に形成する ことを特徴とする請求項（１）又は（２）記載の半導体
ウエハの製造方法3. The method of manufacturing a semiconductor wafer according to claim 1, wherein the first stopper is formed in a scribe region that separates the chips.
と半導体の相対的移動により研摩する ことを特徴とする請求項（１）、（２）又は（３）記載
の半導体ウエハの製造方法4. The semiconductor according to claim 1, wherein an abrasive is supplied between the semiconductor and the surface plate, and polishing is performed by relative movement of the surface plate and the semiconductor. Wafer manufacturing method
らなる ことを特徴とする請求項（４）記載の半導体ウエハの製
造方法。5. The method of manufacturing a semiconductor wafer according to claim 4, wherein the polishing agent is an alkaline solution containing high-purity quartz.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28459088A JP2689536B2 (en) | 1988-11-09 | 1988-11-09 | Method for manufacturing semiconductor wafer |
| DE68927871T DE68927871T2 (en) | 1988-11-09 | 1989-11-06 | Manufacturing process of a semiconductor wafer |
| US07/432,123 US5051378A (en) | 1988-11-09 | 1989-11-06 | Method of thinning a semiconductor wafer |
| EP89311454A EP0368584B1 (en) | 1988-11-09 | 1989-11-06 | Method of manufacturing a semiconductor wafer |
| KR1019890016068A KR0144461B1 (en) | 1988-11-09 | 1989-11-07 | Method for making a semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28459088A JP2689536B2 (en) | 1988-11-09 | 1988-11-09 | Method for manufacturing semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02129918A JPH02129918A (en) | 1990-05-18 |
| JP2689536B2 true JP2689536B2 (en) | 1997-12-10 |
Family
ID=17680425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28459088A Expired - Fee Related JP2689536B2 (en) | 1988-11-09 | 1988-11-09 | Method for manufacturing semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2689536B2 (en) |
-
1988
- 1988-11-09 JP JP28459088A patent/JP2689536B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02129918A (en) | 1990-05-18 |
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