JP2687342B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2687342B2
JP2687342B2 JP62073162A JP7316287A JP2687342B2 JP 2687342 B2 JP2687342 B2 JP 2687342B2 JP 62073162 A JP62073162 A JP 62073162A JP 7316287 A JP7316287 A JP 7316287A JP 2687342 B2 JP2687342 B2 JP 2687342B2
Authority
JP
Japan
Prior art keywords
protective film
surface protective
forming
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62073162A
Other languages
Japanese (ja)
Other versions
JPS63239955A (en
Inventor
久良 矢元
稔郎 木▲崎▼原
純三 大久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62073162A priority Critical patent/JP2687342B2/en
Publication of JPS63239955A publication Critical patent/JPS63239955A/en
Application granted granted Critical
Publication of JP2687342B2 publication Critical patent/JP2687342B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は配線層上に第１の表面保護膜と第２の表面保
護膜とを順次形成してなる半導体装置、例えば配線層上
に、SiN層とポリイミド層とを順次形成してなる半導体
集積回路装置の製造方法に関する。 〔発明の概要〕 本発明は例えば配線層上にSiN層とポリイミド層とを
順次形成してなる半導体集積回路装置を製造するに際
し、配線層上にSiN層を形成した後、配線層のボンディ
ングパッドの上方部分を除くSiN層上にポリイミド層を
凹版印刷用の原版であって凹部の深さを変えたものを用
いる印刷法により形成し、その後、このポリイミド層を
マスクにしてSiN層をエッチングしてボンディングパッ
ドの上方部分のSiN層にコンタクト窓を形成する様にし
たことにより、斯る半導体集積回路装置を少ない工程で
効率良く製造することができる様にしたものである。 〔従来の技術〕 一般に半導体集積回路装置は、第２図Ｆに示す様に構
成される。即ち半導体集積回路素子（１）を接着剤
（２）を用いてリードフレーム（３）に固定し、半導体
集積回路素子（１）に設けられたボンディングパッド
（４）とリードフレーム（３）のリード（５）とを金線
（６）によって接続（ボンディング）すると共に、リー
ド（５）の先端部分を除いて全体をエポキシ樹脂（７）
によってモールドすることによって構成される。この場
合、半導体集積回路素子（１）は半導体基板（８）の表
面側にMOS FET等必要な回路素子を集積化し、この上方
に絶縁層をなすSiO2層（９）を介してアルミニウムによ
る配線層（10）を設けると共に、この配線層（10）上に
第１の表面保護膜をなすSiN層（11）と第２の表面保護
膜をなすポリイミド層（12）とを重畳して設けることに
よって構成される。 ここに第１の表面保護膜をなすSiN層（11）は水分を
遮断し、配線層（10）が腐蝕，断線しない様にすると共
にNaイオンを遮断し、特性に劣化が生じない様にするた
めに設けられるものであり、また第２の表面保護膜をな
すポリイミド層（12）は、SiN層（11）におけるクラッ
クの発生やα線によるソフトエラーの発生を防止するた
めに設けられたものである。即ち、表面保護膜をSiN層
（11）のみとするときは、半導体ウエーハの裏面研削，
分割（ダイシング，ブレーキング），ワイヤボンディン
グ，モールドの各工程でSiN層（11）が外部と接触した
り、或いはエポキシ樹脂（７）との熱膨張率の差に起因
してSiN層（11）にクラックが生ずることがあり、これ
を放置するときは、このクラックから水分が入り込み配
線層（10）を腐蝕，断線させてしまうという不都合があ
った。特に第２図Ｆ例の様に軟かいアルミニウムによる
配線層（10）上に硬いSiN層（11）が設けられる場合に
あっては、このSiN層（11）は外部との接触により割れ
易いものとなってしまう。 そこで、近年製造される半導体集積回路装置において
は、第２図Ｆに示す様にSiN層（11）上に比較的軟い材
料であるポリイミド樹脂からなる表面保護膜（12）を設
け、SiN層（11）が外部と接触したり、或いはエポキシ
樹脂（７）との熱膨張率の差に起因して生ずるクラック
を防止し、配線層（10）に腐蝕，断線が生じない様にし
ている。またポリイミド樹脂は低α線有機材料であるた
め、斯るポリイミド層（12）を設けることはエポキシ樹
脂（７）のフィラに含有されているウラン，トリウム等
から発生するα線を減衰させることが可能となり、これ
は特にDRAM等メモリ装置を製造する場合に重要となる。 ところで従来、斯る半導体集積回路装置は、第２図Ａ
〜第２図Ｆに示す工程を経て製造されていた。 即ち、先ず第２図Ａに示す様に、半導体ウエーハ（1
3）を用意し、この半導体ウエーハ（13）のチップとし
て分割する部分（14）‥‥（14）の夫々にMOS FET等必
要な素子を集積化した後、この半導体エーハ（13）上に
絶縁層をなすSiO2層（９），アルミニウムによる配線層
（10）及びSiN層（11）を順次形成する。 次に第２図Ｂに示す様に、SiN層（11）上にレジスト
（15）を形成した後、ボンディングパッド（４）に対向
する部分のレジストを除去し、このレジスト（15）に窓
（15A）を形成し、続いて、第２図Ｃに示す様に、この
レジスト（15）をマスクとしてSiN層（11）にプラズマ
エッチングを施し、このSiN層（11）にボンディングパ
ッド（４）とコンタクトをとるための窓（11A）を形成
する。 次に第２図Ｄに示す様に、レジスト（15）を除去した
後、SiN層（11）上全面に表面保護膜をなすポリイミド
層（12）及びSiN層（11）の窓（11A）に対向する位置に
窓（16A）を有するレジスト（16）を順次形成する。こ
の場合、ポリイミド層（12）は、スピンコート法により
形成される。 次に第２図Ｅに示す様に、レジスト（16）をマスクと
してポリイミド層（12）をエッチングしてこのポリイミ
ド層（12）にSiN層（11）の窓（11A）と連なる窓（12
A）を形成する。 次に第２図Ｆに示す様にレジスト（16）を除去した
後、半導体ウエーハ（13）を各チップ（14）‥‥（14）
に分割し、続いてチップ（14）によって形成された半導
体集積回路素子（１）を接着剤（２）を用いてリードフ
レーム（３）に固定し、ボンディングパッド（４）とリ
ード（５）とを金線（６）で接続し、その後、エポキシ
樹脂（７）によってモールドする。 従来はこの様にして斯る半導体集積回路装置を製造し
ていた。 〔発明が解決しようとする問題点〕 しかしながら、斯る従来の半導体装置の製造方法にお
いては、ポリイミド層（12）を所定の位置、即ち、ボン
ディングパッド（４）上の窓（12A）となる部分以外の
部分に形成する場合、スピンコート法によってポリイミ
ド層（12）を全面に形成した後、このポリイミド層（1
2）上にレジスト（16）を被着形成し、続いてこのレジ
スト（16）に窓（16A）を形成し、その後、このレジス
ト（16）をマスクとしてポリイミド層（12）をエッチン
グしてボンディングパッド（４）上のポリイミド層を除
去するという複雑な工程を必要とし、ポリイミド層（1
2）を所望の位置に簡単に形成することができないとい
う不都合があった。 また例えば半導体集積回路装置であるダイナミック・
ランダム・アクセス・メモリ（以下、DRAMという）にお
いては、α線対策からメモリセル部上方のポリイミド層
についてはこれを比較的厚く、例えば35μｍ〜50μｍに
形成する必要がある一方、周辺部については、α線対策
はさほど必要がなく、SiN層（11）におけるクラックの
発生防止のみが必要とされるので、この部分のポリイミ
ド層の厚さは比較的薄く、例えば３μｍ〜５μｍの厚さ
に形成することで足りるとされている。ところが、斯る
従来の半導体装置の製造方法においては、ポリイミド層
（12）をスピンコート法によって形成しているため、全
面に一様な厚さのポリイミド層（12）しか形成できず、
このため、斯るDRAMの様に場所によって異なる厚さのポ
リイミド層を必要とする半導体装置については、これを
製造することができないという不都合があった。 本発明は、斯る点に鑑み、配線層上に第１の表面保護
膜と第２の表面保護膜とを順次形成してなる半導体装置
を少ない工程で、効率良く製造できる様にすることを目
的とする。 〔問題点を解決するための手段〕 本発明による半導体装置の製造方法は、例えば第１図
に示す様に、配線層（10）上に第１の表面保護膜（11）
と第２の表面保護膜（12）とを形成してなる半導体装置
の製造方法において、 配線層（10）上に第１の表面保護膜（11）を形成した
後、配線層（10）のボンディングパッド（４）の上方部
分を除く第１の表面保護膜（11）上に第２の表面保護膜
（12）を凹版印刷用の原版であって凹部の深さを変えた
ものを用いる印刷法により形成し、その後、第２の表面
保護膜（12）をマスクにして第１の表面保護膜（11）を
エッチングしてボンディングパッド（４）の上方部分の
第１の表面保護膜（11）にコンタクト窓（11A）を形成
する様にしたものである。 〔作用〕 斯る本発明においては、配線層（10）のボンディング
パッド（４）の上方部分を除く第１の表面保護膜（11）
上に第２の表面保護膜（12）を凹版印刷用の原版であっ
て凹部の深さを変えたものを用いる印刷法により形成す
る様にしているので、この第２の表面保護膜（12）のコ
ンタクト窓（12A）はこの第２の表面保護膜（12）を形
成すると同時に形成できる。 また本発明においては、この第２の表面保護膜（12）
をマスクとして第１の表面保護膜（11）をエッチングし
てこの第１の表面保護膜（11）にコンタクト窓（11A）
を形成する様にしているので、第１の表面保護膜（11）
をエッチングしてコンタクト窓（11A）を形成するに際
し、別にレジストを設ける必要はない。 また本発明においては、第２の表面保護膜（12）を印
刷法により形成する様にしているので、１回の印刷工程
で所望の厚さの第２の表面保護膜（12）を形成できる。 〔実施例〕 以下、第１図を参照して本発明による半導体装置の製
造方法の一実施例につき、DRAMを製造する場合を例にし
て説明しよう。尚、この第１図において第２図に対応す
る部分には同一符号を付す。 先ず第１図Ａに示す様に、半導体ウエーハ（13）を用
意し、この半導体ウエーハ（13）のチップとして分割す
る部分（14）‥‥（14）の夫々にDRAMを構成するに必要
な素子を形成した後、この半導体ウエーハ（13）上に絶
縁層をなすSiO2層（９），アルミニウムによる配線層
（10）及び第１の表面保護膜をなすSiN層（11）を順次
形成する。 第１図Ｂに示す様に、凹版印刷用の原版（17）を用意
する。この原版（17）は各チップ（14）‥‥（14）ごと
にボンディングパッド（４）に対向する部分を除き、そ
の他の部分にポリイミド樹脂（18）を充填する凹部（1
9）を形成したものであり、本例においてはメモリセル
アレイ部に対向する部分の凹部（19B）を比較的深く、
例えば35μｍ〜50μｍに形成し、周辺部に対抗する凹部
（19C）については比較的浅く、例えば３μｍ〜５μｍ
の深さに形成する。そこで本例においては、この原版
（17）の凹部（19）にポリイミド樹脂（18）を充填し
て、これを第１図Ｃに示す様にSiN層（11）に押し当て
た後、第１図Ｄに示す様にこの原版（17）をSiN層（1
1）から離脱させる。この様にすると、ボンディングパ
ッド（４）に対向する部分を除き、即ち、ボンディング
パッド（４）に対向する部分にコンタクト窓（12A）を
有するポリイミド層（12）が印刷形成される。そこで、
この後、加熱処理してこのポリイミド層（12）を硬化さ
せる。この場合、メモリセルアレイ部上方のポリイミド
層（12B）は比較的厚く、例えば35μｍ〜50μｍに形成
されるのでα線対策が充分になされ、メモリセルにおい
てソフトエラーの発生が防止される。また周辺部に対向
する部分のポリイミド層（12C）は比較的薄く、例えば
３μｍ〜５μｍの厚さに形成されるので、窓（12A）の
部分を精度良く形成することができる。 次に第１図Ｅに示す様にポリイミド層（12）をマスク
としてSiN層（11）をエッチングしてボンディングパッ
ド（４）上にコンタクト窓（11A）を形成する。 次に第１図Ｆに示す様に半導体ウエーハ（13）を各チ
ップ（14）‥‥（14）に分割し、その後、このチップ
（14）によって形成された半導体集積回路素子（１）を
接着剤（２）を用いてリードフレーム（３）に固定した
後、ボンディングパッド（４）とリード（５）とを金線
（６）で接続し、続いてエポキシ樹脂（７）によって樹
脂封止を行い、本例のDRAMを得る様にする。 斯る本実施例においては、凹版印刷用の原版（17）を
用意し、配線層（10）のボンディングパッド（４）の上
方部分を除くSiN層（11）上にポリイミド層（12）を印
刷法により形成する様にしているので、このポリイミド
層（12）のコンタクト窓（12A）はこのポリイミド層（1
2）を形成すると同時に形成できる。また、このポリイ
ミド層（12）をマスクとしてSiN層（11）をエッチング
してこのSiN層（11）にコンタクト窓（11A）を形成する
様にしているので、SiN層（11）をエッチィングしてコ
ンタクト窓（11A）を形成するに際し、別にレジストを
設ける必要がない。 また本実施例においては、凹版印刷用の原版（17）の
凹部（19）の深さを変えるだけで、ポリイミド層（12）
の厚さを所望の厚さに、例えばメモリセルアレイ部に対
向する部分のポリイミド層（12B）を比較的厚く、周辺
部分のポリイミド層（12C）を比較的薄くする様に形成
できる。 従って、本実施例に依れば、SiN層（11）と場所によ
って異なる厚さを有するポリイミド層（12）とを順次形
成してなる半導体装置を少ない工程で効率良く製造でき
るという利益がある。 また本実施例に依れば、半導体ウエーハ（13）を裏面
研削する前の工程でポリイミド層（12）を形成する様に
しているので、その後の工程例えば半導体ウエーハ（1
3）の裏面研摩，分割，ボンディング，モールド等の工
程でSiN層（11）にクラックが発生することを有効に防
止することができる。 尚、上述実施例においては、SiN層（11）上に設ける
表面保護膜をポリイミド層（12）によって形成する場合
につき述べたが、この代わりに、シリコン樹脂等種々の
樹脂を使用することもでき、この場合にも上述同様の作
用効果を得ることができる。 また上述実施例においては、DRAMを製造する場合につ
き述べたが、本発明は、この上述実施例に限らず、SRAM
等種々の半導体装置を製造する場合に適用でき、この場
合にも上述同様の作用効果を得ることができる。 また本発明は上述実施例に限らず、本発明の要旨を逸
脱することなく、その他種々の構成が取り得ることは勿
論である。 〔発明の効果〕 本発明に依れば、第２の表面保護膜（12）は１回の印
刷工程で所望の厚さに形成できると共にこの第２の表面
保護膜（12）のコンタクト窓（12A）はこの第２の表面
保護膜（12）を形成すると同時に形成でき、また第１の
表面保護膜（11）のコンタクト窓（11A）を形成するに
際し、別にレジストを設ける必要がない様にされている
ので、配線層上に第１の表面保護膜（11）と第２の表面
保護膜（12）とを順次形成してなる半導体装置を少ない
工程で効率良く製造することができるという利益があ
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a semiconductor device in which a first surface protective film and a second surface protective film are sequentially formed on a wiring layer, for example, on a wiring layer, The present invention relates to a method for manufacturing a semiconductor integrated circuit device in which a SiN layer and a polyimide layer are sequentially formed. SUMMARY OF THE INVENTION The present invention, for example, when manufacturing a semiconductor integrated circuit device formed by sequentially forming a SiN layer and a polyimide layer on the wiring layer, after forming the SiN layer on the wiring layer, the bonding pad of the wiring layer The polyimide layer is formed on the SiN layer except the upper part by a printing method using an original plate for intaglio printing in which the depth of the depression is changed, and then the SiN layer is etched using this polyimide layer as a mask. By forming a contact window in the SiN layer above the bonding pad, the semiconductor integrated circuit device can be efficiently manufactured in a small number of steps. [Prior Art] Generally, a semiconductor integrated circuit device is configured as shown in FIG. 2F. That is, the semiconductor integrated circuit element (1) is fixed to the lead frame (3) using an adhesive (2), and the bonding pad (4) provided on the semiconductor integrated circuit element (1) and the lead of the lead frame (3). The (5) and (5) are connected (bonded) by a gold wire (6), and the whole of the lead (5) except for the tip portion is made of an epoxy resin (7).
It is composed by molding. In this case, the semiconductor integrated circuit element (1) has necessary circuit elements such as MOS FETs integrated on the front surface side of the semiconductor substrate (8), and wiring made of aluminum through the SiO 2 layer (9) forming an insulating layer thereabove. The layer (10) is provided, and the SiN layer (11) forming the first surface protection film and the polyimide layer (12) forming the second surface protection film are provided on the wiring layer (10) in an overlapping manner. Composed by. Here, the SiN layer (11) forming the first surface protection film blocks moisture, prevents the wiring layer (10) from being corroded and disconnected, and blocks Na ions so that the characteristics are not deteriorated. The polyimide layer (12) forming the second surface protective film is provided to prevent the occurrence of cracks in the SiN layer (11) and soft errors due to α rays. Is. That is, when only the SiN layer (11) is used as the surface protective film, the back surface of the semiconductor wafer is ground,
The SiN layer (11) comes into contact with the outside in each process of division (dicing, breaking), wire bonding, and molding, or the SiN layer (11) is caused by the difference in the coefficient of thermal expansion with the epoxy resin (7). There is a problem in that cracks may occur in the wire, and when this is left as it is, water enters from the cracks and corrodes and disconnects the wiring layer (10). Particularly when the hard SiN layer (11) is provided on the wiring layer (10) made of soft aluminum as in the example of FIG. 2F, the SiN layer (11) is easily cracked by contact with the outside. Will be. Therefore, in a semiconductor integrated circuit device manufactured in recent years, a surface protective film (12) made of a polyimide resin, which is a relatively soft material, is provided on the SiN layer (11) as shown in FIG. The cracks caused by the contact of (11) with the outside or the difference in the coefficient of thermal expansion with the epoxy resin (7) are prevented so that the wiring layer (10) is not corroded or broken. Since polyimide resin is a low α-ray organic material, provision of such a polyimide layer (12) can attenuate α-rays generated from uranium, thorium, etc. contained in the filler of the epoxy resin (7). This becomes possible, which is particularly important when manufacturing a memory device such as DRAM. By the way, conventionally, such a semiconductor integrated circuit device is shown in FIG.
-It was manufactured through the process shown in FIG. 2F. That is, first, as shown in FIG. 2A, a semiconductor wafer (1
3) is prepared and the necessary elements such as MOS FETs are integrated in each of the parts (14) ... (14) to be divided as chips of this semiconductor wafer (13), and then the semiconductor wafer (13) is insulated. A layered SiO 2 layer (9), a wiring layer (10) made of aluminum, and a SiN layer (11) are sequentially formed. Next, as shown in FIG. 2B, after forming a resist (15) on the SiN layer (11), the resist in the portion facing the bonding pad (4) is removed, and a window ( 15A), and subsequently, as shown in FIG. 2C, the SiN layer (11) is subjected to plasma etching using the resist (15) as a mask, and the SiN layer (11) is bonded to the bonding pad (4). Form a window (11A) for making a contact. Next, as shown in FIG. 2D, after removing the resist (15), a polyimide layer (12) and a window (11A) of the SiN layer (11) forming a surface protective film on the entire surface of the SiN layer (11) are formed. A resist (16) having a window (16A) at a position facing each other is sequentially formed. In this case, the polyimide layer (12) is formed by spin coating. Next, as shown in FIG. 2E, the polyimide layer (12) is etched using the resist (16) as a mask, and the polyimide layer (12) has a window (12) continuous with the window (11A) of the SiN layer (11).
Form A). Next, after removing the resist (16) as shown in FIG. 2F, the semiconductor wafer (13) is attached to each chip (14) (14).
Then, the semiconductor integrated circuit element (1) formed by the chip (14) is fixed to the lead frame (3) with the adhesive (2), and the bonding pad (4) and the lead (5) are formed. Are connected with a gold wire (6), and then molded with an epoxy resin (7). Conventionally, such a semiconductor integrated circuit device is manufactured in this manner. [Problems to be Solved by the Invention] However, in such a conventional method for manufacturing a semiconductor device, the polyimide layer (12) is provided at a predetermined position, that is, a portion to be the window (12A) on the bonding pad (4). In the case of forming on a portion other than the above, after the polyimide layer (12) is formed on the entire surface by spin coating, the polyimide layer (1
2) A resist (16) is deposited on the resist (16), a window (16A) is subsequently formed in the resist (16), and then the polyimide layer (12) is etched by using the resist (16) as a mask to bond. The complicated process of removing the polyimide layer on the pad (4) is required, and the polyimide layer (1
There is an inconvenience that 2) cannot be easily formed at a desired position. In addition, for example, a dynamic
In a random access memory (hereinafter referred to as DRAM), it is necessary to form the polyimide layer above the memory cell portion to be relatively thick, for example, 35 μm to 50 μm, while the peripheral portion is Since there is no need to take measures against α-rays and only the occurrence of cracks in the SiN layer (11) needs to be prevented, the thickness of the polyimide layer at this portion is relatively thin, for example, 3 μm to 5 μm. It is said that this is enough. However, in such a conventional semiconductor device manufacturing method, since the polyimide layer (12) is formed by the spin coating method, only the polyimide layer (12) having a uniform thickness can be formed on the entire surface,
Therefore, a semiconductor device such as the DRAM that requires a polyimide layer having a different thickness depending on location cannot be manufactured. In view of this point, the present invention aims to enable a semiconductor device having a first surface protective film and a second surface protective film sequentially formed on a wiring layer to be efficiently manufactured with a small number of steps. To aim. [Means for Solving Problems] In the method for manufacturing a semiconductor device according to the present invention, for example, as shown in FIG. 1, a first surface protective film (11) is formed on a wiring layer (10).
A method of manufacturing a semiconductor device, comprising: forming a first surface protection film (11) on a wiring layer (10), and then forming a second surface protection film (12) on the wiring layer (10). Printing using a second surface protection film (12) on the first surface protection film (11) excluding the upper portion of the bonding pad (4) as an original plate for intaglio printing, in which the depth of the recesses is changed. And then the first surface protection film (11) is etched by using the second surface protection film (12) as a mask to etch the first surface protection film (11) above the bonding pad (4). ), A contact window (11A) is formed. [Operation] In the present invention, the first surface protective film (11) excluding the upper portion of the bonding pad (4) of the wiring layer (10)
Since the second surface protective film (12) is formed on the upper side by a printing method using an original plate for intaglio printing, in which the depth of the recesses is changed, the second surface protective film (12) is formed. The contact window (12A) can be formed simultaneously with the formation of the second surface protective film (12). In the present invention, the second surface protective film (12)
The first surface protection film (11) is etched by using the mask as a mask, and a contact window (11A) is formed in the first surface protection film (11).
The first surface protection film (11)
It is not necessary to separately provide a resist when the contact window (11A) is formed by etching. Further, in the present invention, since the second surface protective film (12) is formed by the printing method, the second surface protective film (12) having a desired thickness can be formed in one printing step. . [Embodiment] An embodiment of the method of manufacturing a semiconductor device according to the present invention will be described below with reference to FIG. Incidentally, in FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals. First, as shown in FIG. 1A, a semiconductor wafer (13) is prepared, and elements necessary for constructing a DRAM in each of the portions (14) ... (14) to be divided into chips of this semiconductor wafer (13). After this, the SiO 2 layer (9) forming an insulating layer, the wiring layer (10) made of aluminum, and the SiN layer (11) forming a first surface protective film are sequentially formed on the semiconductor wafer (13). As shown in FIG. 1B, an original plate (17) for intaglio printing is prepared. This original plate (17) has a recess (1) for filling the polyimide resin (18) in the other parts except the part facing the bonding pad (4) for each chip (14).
9) is formed, and in this example, the concave portion (19B) in the portion facing the memory cell array portion is relatively deep,
For example, it is formed with a thickness of 35 μm to 50 μm, and the recess (19C) facing the peripheral portion is relatively shallow, for example, 3 μm to 5 μm.
To a depth of. Therefore, in this example, the concave portion (19) of the original plate (17) is filled with a polyimide resin (18) and pressed against the SiN layer (11) as shown in FIG. As shown in Fig. D, this original plate (17) was replaced with a SiN layer (1
Remove from 1). By doing so, the polyimide layer (12) having the contact window (12A) is printed and formed except the portion facing the bonding pad (4), that is, the portion facing the bonding pad (4). Therefore,
Then, heat treatment is performed to cure the polyimide layer (12). In this case, the polyimide layer (12B) above the memory cell array portion is relatively thick, for example, formed to have a thickness of 35 μm to 50 μm, so that the α ray countermeasure is sufficiently taken and the soft error is prevented from occurring in the memory cell. Further, since the polyimide layer (12C) in the portion facing the peripheral portion is relatively thin, for example, formed to have a thickness of 3 μm to 5 μm, the portion of the window (12A) can be accurately formed. Next, as shown in FIG. 1E, the SiN layer (11) is etched using the polyimide layer (12) as a mask to form a contact window (11A) on the bonding pad (4). Next, as shown in FIG. 1F, the semiconductor wafer (13) is divided into chips (14) ... (14), and then the semiconductor integrated circuit element (1) formed by the chips (14) is bonded. After fixing to the lead frame (3) using the agent (2), the bonding pad (4) and the lead (5) are connected with a gold wire (6), and subsequently, resin sealing is performed with an epoxy resin (7). Then, the DRAM of this example is obtained. In this embodiment, an original plate (17) for intaglio printing is prepared, and a polyimide layer (12) is printed on the SiN layer (11) of the wiring layer (10) excluding the upper portion of the bonding pad (4). Since it is formed by the method, the contact window (12A) of this polyimide layer (12) is
2) can be formed at the same time as forming. Further, since the SiN layer (11) is etched by using the polyimide layer (12) as a mask to form the contact window (11A) in the SiN layer (11), the SiN layer (11) is etched. There is no need to separately provide a resist when forming the contact window (11A). Further, in the present embodiment, the polyimide layer (12) is simply changed by changing the depth of the recess (19) of the original plate (17) for intaglio printing.
Can be formed to have a desired thickness, for example, the polyimide layer (12B) in the portion facing the memory cell array portion can be made relatively thick and the polyimide layer (12C) in the peripheral portion can be made relatively thin. Therefore, according to this embodiment, there is an advantage that a semiconductor device in which the SiN layer (11) and the polyimide layer (12) having different thicknesses are sequentially formed can be efficiently manufactured in a small number of steps. Further, according to this embodiment, since the polyimide layer (12) is formed in the step before the back surface grinding of the semiconductor wafer (13), the subsequent steps such as the semiconductor wafer (1
It is possible to effectively prevent the occurrence of cracks in the SiN layer (11) during the processes such as 3) back surface polishing, division, bonding, and molding. In the above-mentioned embodiment, the case where the surface protective film provided on the SiN layer (11) is formed by the polyimide layer (12) has been described, but various resins such as silicone resin may be used instead. Also in this case, the same effect as the above can be obtained. Further, in the above-mentioned embodiment, the case of manufacturing the DRAM is described, but the present invention is not limited to the above-mentioned embodiment, and SRAM
For example, the present invention can be applied to the case of manufacturing various semiconductor devices. In this case, the same operation and effect as described above can be obtained. In addition, the present invention is not limited to the above-described embodiment, and it goes without saying that various other configurations can be adopted without departing from the spirit of the present invention. EFFECT OF THE INVENTION According to the present invention, the second surface protective film (12) can be formed to have a desired thickness in one printing step, and the contact window of the second surface protective film (12) ( 12A) can be formed at the same time when this second surface protection film (12) is formed, and it is not necessary to separately provide a resist when forming the contact window (11A) of the first surface protection film (11). Therefore, it is possible to efficiently manufacture a semiconductor device in which the first surface protection film (11) and the second surface protection film (12) are sequentially formed on the wiring layer with a small number of steps. There is.

【図面の簡単な説明】 第１図は本発明半導体装置の製造方法の一実施例を示す
工程図、第２図は従来の半導体装置の製造方法を示す工
程図である。 （１）は半導体集積回路素子、（４）はボンディングパ
ッド、（９）はSiO2層、（10）は配線層、（11）はSiN
層、（11A）はSiN層の窓、（12）はポリイミド層、（12
A）はポリイミド層の窓、（15）及び（16）は夫々レジ
スト、（17）は凹版印刷用原版、（18）はポリイミド樹
脂である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process drawing showing an embodiment of a semiconductor device manufacturing method according to the present invention, and FIG. 2 is a process drawing showing a conventional semiconductor device manufacturing method. (1) is a semiconductor integrated circuit device, (4) is a bonding pad, (9) is a SiO 2 layer, (10) is a wiring layer, and (11) is SiN.
Layer, (11A) window of SiN layer, (12) polyimide layer, (12
A) is a window of a polyimide layer, (15) and (16) are resists, (17) is an intaglio printing original plate, and (18) is a polyimide resin.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭59−232424（ＪＰ，Ａ) 特開 昭62−52936（ＪＰ，Ａ) 特開 昭58−53479（ＪＰ，Ａ)   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References Japanese Patent Laid-Open No. 232424/1984 (JP, A)                 JP 62-52936 (JP, A)                 JP 58-53479 (JP, A)

Claims (1)

(57)【特許請求の範囲】 １．配線層上に第１の表面保護膜と第２の表面保護膜と
を形成してなる半導体装置の製造方法において、 上記配線層上に第１の表面保護膜を形成する工程と、 上記配線層のボンディングパッドの上方部分を除く上記
第１の表面保護膜上に、凹版印刷用の原版であって凹部
の深さを変えたものを用いる印刷法により、第２の表面
保護膜を形成する工程と、 上記第２の表面保護膜をマスクにして上記第１の表面保
護膜をエッチングして上記ボンディングパッドの上方部
分の上記第１の表面保護膜にコンタクト窓を形成する工
程とを有する ことを特徴とする半導体装置の製造方法。 ２．配線層上に第１の表面保護膜と第２の表面保護膜と
を形成してなる半導体装置の製造方法において、 上記配線層上に第１の表面保護膜を形成する工程と、 上記配線層のボンディングパッドの上方部分を除く上記
第１の表面保護膜上に、凹版印刷用の原版であって凹部
の深さを変えたものを用いる印刷法により、部分的に厚
さの異なる第２の表面保護膜を形成する工程と、 上記第２の表面保護膜をマスクにして上記第１の表面保
護膜をエッチングして上記ボンディングパッドの上方部
分の上記第１の表面保護膜にコンタクト窓を形成する工
程とを有する ことを特徴とする半導体装置の製造方法。 ３．配線層上に第１の表面保護膜と第２の表面保護膜と
を形成してなる半導体装置の製造方法において、 上記配線層上に第１の表面保護膜を形成する工程と、 上記配線層のボンディングパッドの上方部分を除く上記
第１の表面保護膜上に、凹版印刷用の原版であって凹部
の深さを変えたものを用いる印刷法により、メモリセル
アレイ部に対向する部分の厚さが他の部分の厚さよりも
厚い第２の表面保護膜を形成する工程と、 上記第２の表面保護膜をマスクにして上記第１の表面保
護膜をエッチングして上記ボンディングパッドの上方部
分の上記第１の表面保護膜にコンタクト窓を形成する工
程とを有する ことを特徴とする半導体装置の製造方法。(57) [Claims] A method of manufacturing a semiconductor device, comprising: forming a first surface protective film and a second surface protective film on a wiring layer; a step of forming the first surface protective film on the wiring layer; Forming a second surface protection film on the first surface protection film excluding the upper part of the bonding pad by a printing method using an original plate for intaglio printing with different recess depths. And a step of etching the first surface protection film using the second surface protection film as a mask to form a contact window in the first surface protection film above the bonding pad. A method for manufacturing a characteristic semiconductor device. 2. A method of manufacturing a semiconductor device, comprising: forming a first surface protective film and a second surface protective film on a wiring layer; a step of forming the first surface protective film on the wiring layer; On the first surface protective film excluding the upper portion of the bonding pad, the second ingot having a partially different thickness by a printing method using an original plate for intaglio printing in which the depth of the recess is changed. Forming a surface protective film, and etching the first surface protective film using the second surface protective film as a mask to form a contact window in the first surface protective film above the bonding pad. A method of manufacturing a semiconductor device, comprising: 3. A method of manufacturing a semiconductor device, comprising: forming a first surface protective film and a second surface protective film on a wiring layer; a step of forming the first surface protective film on the wiring layer; The thickness of the portion facing the memory cell array portion by a printing method using an original plate for intaglio printing, in which the depth of the recess is changed, on the first surface protective film except for the upper part of the bonding pad. Forming a second surface protective film that is thicker than the thickness of other portions, and etching the first surface protective film using the second surface protective film as a mask to remove a portion above the bonding pad. A step of forming a contact window in the first surface protection film, the method of manufacturing a semiconductor device.
JP62073162A 1987-03-27 1987-03-27 Method for manufacturing semiconductor device Expired - Fee Related JP2687342B2 (en)

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JP62073162A JP2687342B2 (en) 1987-03-27 1987-03-27 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62073162A JP2687342B2 (en) 1987-03-27 1987-03-27 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63239955A JPS63239955A (en) 1988-10-05
JP2687342B2 true JP2687342B2 (en) 1997-12-08

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JP62073162A Expired - Fee Related JP2687342B2 (en) 1987-03-27 1987-03-27 Method for manufacturing semiconductor device

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Country Link
JP (1) JP2687342B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5779933B2 (en) * 2011-03-25 2015-09-16 凸版印刷株式会社 Thin film transistor device and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853479A (en) * 1981-09-24 1983-03-30 Seiko Epson Corp Manufacture of thin film
JPS59232424A (en) * 1983-06-15 1984-12-27 Hitachi Ltd Semiconductor device and manufacture of the same
JPS6252936A (en) * 1985-08-31 1987-03-07 Nitto Electric Ind Co Ltd Paste composition for covering semiconductor element

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