JP2670408B2 - 樹脂封止型半導体装置及びその製造方法 - Google Patents

樹脂封止型半導体装置及びその製造方法

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Publication number
JP2670408B2
JP2670408B2 JP4288561A JP28856192A JP2670408B2 JP 2670408 B2 JP2670408 B2 JP 2670408B2 JP 4288561 A JP4288561 A JP 4288561A JP 28856192 A JP28856192 A JP 28856192A JP 2670408 B2 JP2670408 B2 JP 2670408B2
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Japan
Prior art keywords
resin
lead frame
resin body
island
semiconductor device
Prior art date
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Expired - Fee Related
Application number
JP4288561A
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JPH06140548A (ja
Inventor
俊哉 渡辺
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Toshiba Corp
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Toshiba Corp
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Priority to JP4288561A priority Critical patent/JP2670408B2/ja
Priority to US08/127,060 priority patent/US5365106A/en
Publication of JPH06140548A publication Critical patent/JPH06140548A/ja
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Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、低熱抵抗値を実現する
ために、リ−ドフレ−ムのアイランド（ダイパッド）の
一主面を樹脂体の表面に露出させる樹脂封止型半導体装
置の改良に関する。
【０００２】
【従来の技術】従来、樹脂封止型半導体装置では、低熱
抵抗値を実現するため、例えば図５に示すように、リ−
ドフレ−ム１１のアイランド（ダイパッド）１１ａの一
主面を樹脂体１２の表面に露出させる構造が採用されて
いる。
【０００３】しかし、上記構成の樹脂封止型半導体装置
には、例えば図６に示すように、樹脂体１２を成形する
際の加熱によって、その最終形状に歪み（そり）を生じ
ることが知られている。これは、バイメタルのように、
膨脹係数の異なる材料が互いに張り合わされているた
め、即ちリ−ドフレ−ム（金属）と樹脂の膨脹係数が異
なることにより生じるものである。そして、このような
最終形状の歪みは、樹脂体１２の内部に搭載されている
半導体チップ１３を割るなどの実害を与える欠点があ
る。
【０００４】
【発明が解決しようとする課題】このように、従来の樹
脂封止型半導体装置は、低熱抵抗値を実現するため、リ
−ドフレ−ムのアイランドの一主面を樹脂体の表面に露
出させているが、樹脂体成形時の加熱によりその最終形
状に歪みを生じる欠点がある。
【０００５】本発明は、上記欠点を解決すべくなされた
もので、その目的は、低熱抵抗値を実現し得ると共に、
その最終形状における歪み（そり）を生じることがない
樹脂封止型半導体装置及びその製造方法を提供すること
である。
【０００６】
【課題を解決するための手段】上記目的を達成するた
め、本発明の樹脂封止型半導体装置は、半導体チップを
搭載するためのアイランドを有し、当該半導体チップが
搭載される側と反対側の当該アイランドの一主面が樹脂
体から露出するように構成されている第１のリ−ドフレ
−ムと、上記第１のリ−ドフレ−ムのアイランドとほぼ
同じ形状の歪み防止部材を有し、当該アイランドに対向
する側と反対側の当該歪み防止部材の一主面が樹脂体か
ら露出するように構成されている第２のリ−ドフレ−ム
と備えている。
【０００７】また、上記第１のリ−ドフレ−ムには、イ
ンナ−リ−ド及びアウタ−リ−ドが形成されている。さ
らに、上記第１及び第２のリ−ドフレ−ムには、これら
を重ね合せる際の位置合せ用の穴がそれぞれ形成されて
いる。
【０００８】
【作用】上記構成によれば、第２のリ−ドフレ−ムは、
アイランドとほぼ同じ形状の歪み防止部材を有し、か
つ、当該アイランドに対向する側と反対側の当該歪み防
止部材の一主面が樹脂体から露出するように構成されて
いる。これにより、樹脂封止時において、樹脂体の両側
の面では、熱膨脹による応力のバランスがとれるため
に、最終形状の樹脂封止半導体装置には歪み（そり）が
生じることがない。
【０００９】
【実施例】以下、図面を参照しながら、本発明の一実施
例について詳細に説明する。図１は、本発明の一実施例
に係わる樹脂封止型半導体装置を示している。図１にお
いて、Ａは、第１のリ−ドフレ−ムであり、Ｂは、第２
のリ−ドフレ−ムである。また、第１のリ−ドフレ−ム
Ａにおいて、２１は、アイランド（ダイパッド）、２
２は、インナ−リ−ド、２３は、アウタ−リ−ド、２４
は、半導体チップ、２５は、位置合せ用の穴である。第
２のリ−ドフレ−ム Ｂにおいて、２６は、歪み（そ
り）防止部材、２７は、位置合せ用の穴である。
【００１０】この樹脂封止型半導体装置は、従来とほぼ
同様の構成を有する第１のリ−ドフレ−ム Ａに、本発
明の特徴である第２のリ−ドフレ−ム Ｂをさらに具備
するものである。そして、第２のリ−ドフレ−ム Ｂ
は、第１のリ−ドフレ−ム Ａのアイランド２１とほぼ
同様の形状を有する歪み（そり）防止部材２６を備えて
いる。この歪み（そり）防止部材２６は、アイランド２
１と同様に、その一主面が樹脂体の表面に露出される。
【００１１】つまり、本発明は、樹脂体の両側の面に金
属、即ち第１のリ−ドフレ−ム Ａのアイランド２１の
一主面、及び、第２のリ−ドフレ−ム Ｂの歪み（そ
り）防止部材２６の一主面を露出させることで、樹脂体
の両面に発生する応力のバランスをとり、最終形状にお
ける歪み（そり）をなくすものである。
【００１２】なお、第１のリ−ドフレ−ム Ａのアイラ
ンド２１と第２のリ−ドフレ−ムＢの歪み（そり）防止
部材２６は、対称的に配置される必要があるが、これ
は、第１のリ−ドフレ−ム Ａ及び第２のリ−ドフレ−
ム Ｂの所定の場所に位置合せ用の穴２５，２７を設
け、例えば樹脂体の成形時に金型のピンに嵌め込むこと
により、容易に達成できる。
【００１３】次に、図２〜図４を参照しながら、図１の
樹脂封止型半導体装置の製造方法について説明する。ま
ず、図２に示すように、第１のリ−ドフレ−ム Ａのア
イランド２１上に半導体チップ２４を搭載する。また、
ボンディングワイヤ２８により、インナ−リ−ド２２と
半導体チップ２４との接続を行う。
【００１４】次に、図３に示すように、第１のリ−ドフ
レ−ム Ａに第２のリ−ドフレ−ムＢを重ね合せる。こ
れは、例えば、樹脂成形用の金型に第１のリ−ドフレ−
ムＡを搭載した後、第２のリ−ドフレ−ム Ｂを搭載す
ることにより、容易に行うことができる。
【００１５】次に、図４に示すように、樹脂封止（成
形）を行う。なお、この時、第１のリ−ドフレ−ム Ａ
と第２のリ−ドフレ−ム Ｂは、同一の素材を有してい
るために、当該成形時の加熱によって樹脂体２９の両側
において同様な熱膨脹が起こる。従って、樹脂体２９の
両側の面では、熱膨脹による応力のバランスがとれ、歪
み（そり）が発生することがない。この後、通常の方法
によって、最終形状の樹脂封止型半導体装置を第１及び
第２のリ−ドフレ−ム Ａ，Ｂからそれぞれ切り離す。
【００１６】
【発明の効果】以上、説明したように、本発明の樹脂封
止型半導体装置及びその製造方法によれば、次のような
効果を奏する。従来は、樹脂体の片側のみにリ−ドフレ
−ムのアイランドの一主面が露出していたため、金属と
樹脂体のバイメタル構造の原理により、パッケ−ジに歪
み（そり）を生じていた。これに対し、本発明によれ
ば、二種類のリ−ドフレ−ムを用い、新たに採用したリ
−ドフレ−ムには、アイランドとほぼ同様の形状を有す
る歪み（そり）防止部材を設けている。即ち、最終形状
の樹脂封止型半導体装置は、金属板（アイランド、歪み
防止部材）により樹脂体が挟まれた構造を有することに
なる。このため、樹脂体の両面に発生する応力のバラン
スがとれ、低熱抵抗値を実現し得ると共に、歪み（そ
り）を生じさせることもない。
【図面の簡単な説明】
【図１】本発明の一実施例に係わる樹脂封止型半導体装
置を示す斜視図。
【図２】図１の樹脂封止型半導体装置の製造方法を示す
断面図。
【図３】図１の樹脂封止型半導体装置の製造方法を示す
断面図。
【図４】図１の樹脂封止型半導体装置の製造方法を示す
断面図。
【図５】従来の樹脂封止型半導体装置を示す断面図。
【図６】従来の樹脂封止型半導体装置を示す断面図。
【符号の説明】
Ａ …第１のリ−ドフレ−ム、 Ｂ …第２のリ−ドフレ−ム、 ２１ …アイランド（ダイパッド）、 ２２ …インナ−リ−ド、 ２３ …アウタ−リ−ド、 ２４ …半導体チップ、 ２５，２７…位置合せ用の穴 ２６ …歪み（そり）防止部材、 ２８ …ボンディングワイヤ、 ２９ …樹脂体。

Claims (3)

    (57)【特許請求の範囲】
  1. 【請求項１】 第１面に半導体チップが搭載されるアイ
    ランドを有し、前記アイランドの第１面の全体が樹脂体
    により覆われ、前記アイランドの第１面の反対側の第２
    面が前記樹脂体から露出する第１のリ−ドフレ−ムと、前記 第１のリ−ドフレ−ムのアイランドとほぼ同じ形状
    の歪み防止部材を有し、前記アイランドの第１面に対向
    する前記歪み防止部材の第１面の全体が前記樹脂体によ
    り覆われ、前記歪み防止部材の第１面の反対側の第２面
    が前記樹脂体から露出する第２のリ−ドフレ−ムとを具
    備する樹脂封止型半導体装置。
  2. 【請求項２】 前記第１及び第２のリ−ドフレ−ムに
    は、これらを重ね合せる際の位置合せ用の穴がそれぞれ
    形成されていることを特徴とする請求項１に記載の樹脂
    封止型半導体装置。
  3. 【請求項３】 第１のリ−ドフレ−ムのアイランド上に
    半導体チップを搭載する工程と、前記第１のリ−ドフレ
    −ムのアイランドとほぼ同じ形状の歪み防止部材を有す
    る第２のリ−ドフレ−ムを、前記半導体チップが前記ア
    イランドと前記歪み防止部材の間に挟み込まれるように
    前記第１のリ−ドフレ−ムに重ね合せる工程と、前記ア
    イランドと前記歪み防止部材の互いに対向する面がそれ
    ぞれ樹脂体に覆われ、前記互いに対向する面以外の面が
    それぞれ前記樹脂体から露出するように、前記アイラン
    ドと前記歪み防止部材の間に前記樹脂体を満たす工程と
    を具備する樹脂封止型半導体装置の製造方法。
JP4288561A 1992-10-27 1992-10-27 樹脂封止型半導体装置及びその製造方法 Expired - Fee Related JP2670408B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP4288561A JP2670408B2 (ja) 1992-10-27 1992-10-27 樹脂封止型半導体装置及びその製造方法
US08/127,060 US5365106A (en) 1992-10-27 1993-09-27 Resin mold semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4288561A JP2670408B2 (ja) 1992-10-27 1992-10-27 樹脂封止型半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JPH06140548A JPH06140548A (ja) 1994-05-20
JP2670408B2 true JP2670408B2 (ja) 1997-10-29

Family

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Family Applications (1)

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JP4288561A Expired - Fee Related JP2670408B2 (ja) 1992-10-27 1992-10-27 樹脂封止型半導体装置及びその製造方法

Country Status (2)

Country Link
US (1) US5365106A (ja)
JP (1) JP2670408B2 (ja)

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