JP2644079B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2644079B2 JP2644079B2 JP29940790A JP29940790A JP2644079B2 JP 2644079 B2 JP2644079 B2 JP 2644079B2 JP 29940790 A JP29940790 A JP 29940790A JP 29940790 A JP29940790 A JP 29940790A JP 2644079 B2 JP2644079 B2 JP 2644079B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- pad
- opening
- psg
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に関し、特にバンプの周囲の
絶縁膜の構造に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a structure of an insulating film around a bump.
従来のバンプを有する半導体集積回路の製造方法を第
２図を用いて説明する。A conventional method for manufacturing a semiconductor integrated circuit having bumps will be described with reference to FIG.
まず第２図（ａ）のように、半導体基板１上に、例え
ばAl層からなるバンプ形成用のパッド２を形成したの
ち、その上に全面にわたって、チップの耐湿性を向上さ
せるためのPSG膜３を形成する。さらに、このPSG膜３上
に耐湿性を向上させるためのシリコン窒化膜４を形成す
る。First, as shown in FIG. 2 (a), a bump forming pad 2 made of, for example, an Al layer is formed on a semiconductor substrate 1, and a PSG film for improving the moisture resistance of the chip is formed over the entire surface. Form 3 Further, a silicon nitride film 4 for improving moisture resistance is formed on the PSG film 3.
次に第２図（ｂ）のように、フォトレジスト膜15をマ
スクとしてシリコン窒化膜４をCF4等のガスを用いるド
ライエッチング法でエッチングする。さらに第２図
（ｃ）のように、上述のフォトレジスト膜15をマスクと
してPSG膜３をフッ酸等の溶液でPSG膜３を等方的にウェ
ットエッチングする。Next, as shown in FIG. 2B, the silicon nitride film 4 is etched by a dry etching method using a gas such as CF 4 using the photoresist film 15 as a mask. Further, as shown in FIG. 2C, the PSG film 3 is isotropically wet-etched with a solution such as hydrofluoric acid using the above-mentioned photoresist film 15 as a mask.
次に第２図（ｄ）のように、フォトレジスト膜15を除
去する。次に第２図（ｅ）のように、全面にバンプ用の
銅をメッキするための電極として、例えば薄いTi−Cu膜
6Aをスパッタ法により形成するが、シリコン窒化膜４が
PSG膜３よりもパッドの内側にあるため段差が厳しく、
スパッタした場合、Ti−Cu膜6Aに段切れが発生しやす
い。次に第２図（ｆ）に示す様に、フォトレジスト膜15
Aをマスクとして電極となるTi−Cu膜6A上に銅をメッキ
してバンプ７を形成する。Next, as shown in FIG. 2D, the photoresist film 15 is removed. Next, as shown in FIG. 2E, for example, a thin Ti-Cu film is used as an electrode for plating copper for bumps on the entire surface.
6A is formed by a sputtering method.
The step is more severe because it is on the inside of the pad than the PSG film 3,
When sputtered, the Ti—Cu film 6A is apt to break. Next, as shown in FIG.
Using A as a mask, copper is plated on Ti-Cu film 6A serving as an electrode to form bump 7.
上述した従来のバンプの形成方法では、パシベーショ
ン膜としてのシリコン窒化膜が、PSG膜により内側に形
成されるため、メッキの下地となるTi−Cu膜に段切れが
発生する。このため銅メッキによりバンプを形成した場
合ウェーハ面内で均一にメッキされないため、バンプの
高さがばらつくという不具合が発生する。In the above-described conventional bump forming method, since the silicon nitride film as the passivation film is formed on the inner side by the PSG film, the Ti-Cu film serving as the base for plating is disconnected. For this reason, when bumps are formed by copper plating, the bumps are not uniformly plated in the wafer surface, and the height of the bumps varies.
本発明の半導体集積回路は、半導体基板上に形成され
た金属膜よりなるバンプ形成用のパッドと、前記パッド
を含む全面に形成されかつパッド上にパッドより小さい
面積の開口部を有するPSG膜と、前記PSG膜上に形成され
かつ前記パッドの上部にパッドより大きい面積の開口部
を有するシリコン窒化膜とを含むものである。A semiconductor integrated circuit according to the present invention includes a pad for forming a bump made of a metal film formed on a semiconductor substrate, a PSG film formed on the entire surface including the pad and having an opening on the pad with an area smaller than the pad. A silicon nitride film formed on the PSG film and having an opening having an area larger than the pad above the pad.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｈ）は本発明の一実施例を説明する
ための半導体チップの断面図である。以下製造工程順に
説明する。1 (a) to 1 (h) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention. Hereinafter, description will be made in the order of the manufacturing process.
まず第１図（ａ）のように、半導体基板１上に、例え
ばAl膜からなるバンプ形成用のパッド２を形成し、その
上にPSG膜３とシリコン窒化膜４を順次形成する。次で
パット２上にパッド２より面積の大きい第１の開口10A
を有するフォトレジスト膜５を形成する。First, as shown in FIG. 1A, a pad 2 for forming a bump made of, for example, an Al film is formed on a semiconductor substrate 1, and a PSG film 3 and a silicon nitride film 4 are sequentially formed thereon. Next, a first opening 10A having a larger area than the pad 2 on the pad 2
Is formed.
次に第１図（ｂ）のようにフォトレジスト膜５をマス
クに、例えばCF4等のガスを用いるドライエッチング法
でシリコン窒化膜４をエッチングする。次に第１図
（ｃ）のように、フォトレジスト膜５を除去したのち第
１図（ｄ）のように、第２のホトリソグラフィ工程を行
うため、全面にフォトレジスト膜5Aを塗布する。Then a mask with the photoresist film 5 as Fig. 1 (b), etching the silicon nitride film 4 by dry etching using, for example, CF 4 or the like gas. Next, as shown in FIG. 1 (c), after removing the photoresist film 5, a photoresist film 5A is applied to the entire surface to perform a second photolithography step as shown in FIG. 1 (d).
次に第１図（ｅ）のように、PSG膜３に開口部を設け
るため、ホトリソグラフィにより、フォトレジスト膜5A
をパターニングし、パッド２より小さな面積の第２の開
口部10Bを形成する。次に第１図（ｆ）のように、第２
の開口部10Bを有するフォトレジスト膜5Aをマスクに、
フッ酸溶液でPSG膜３を等方的にエッチングする。Next, as shown in FIG. 1E, in order to provide an opening in the PSG film 3, a photoresist film 5A is formed by photolithography.
Is patterned to form a second opening 10B having an area smaller than the pad 2. Next, as shown in FIG.
Using the photoresist film 5A having the opening 10B as a mask,
The PSG film 3 is isotropically etched with a hydrofluoric acid solution.
次に第１図（ｇ）のように、フォトレジスト膜5Aを除
去する。次に第１図（ｈ）のように、全面にメッキ用の
電極としてTi−Cu膜６を形成し、次でパッド２上に開口
部を有するフォトレジスト膜5Bをマスクとして銅メッキ
を行ないバンプ７を形成する。Next, as shown in FIG. 1 (g), the photoresist film 5A is removed. Next, as shown in FIG. 1 (h), a Ti-Cu film 6 is formed as an electrode for plating over the entire surface, and then copper plating is performed using a photoresist film 5B having an opening on the pad 2 as a mask. 7 is formed.
このようにして構成された本実施例によれば、PSG膜
３に形成される開口部に比べてシリコン窒化膜４に形成
される開口部の方が大きいため、シリコン窒化膜４上に
形成されるTi−Cu膜６に段切れが発生することはなくな
る。従って半導体基板上に形成されるバンプ７の高さ
は、従来20μｍ程度のばらつきが認められたが、本実施
例によれば５μｍ以下にすることができた。According to the present embodiment thus configured, since the opening formed in the silicon nitride film 4 is larger than the opening formed in the PSG film 3, the opening formed on the silicon nitride film 4 is formed. No break in the Ti-Cu film 6 occurs. Therefore, the height of the bumps 7 formed on the semiconductor substrate has conventionally been varied by about 20 μm, but according to the present embodiment, it could be reduced to 5 μm or less.
以上説明したように本発明は、バンプ形成用のパッド
上に、パッドより小さい面積の開口部を有するPSG膜
と、パッドより大きい面積の開口部を有するシリコン窒
化膜とを形成することにより、バンプ用の金属をメッキ
するための電極である、薄いTi−Cu膜を段切れなしに形
成できるため、バンプの高さのばらつきを小さくできる
という効果がある。As described above, the present invention forms a bump on a pad for bump formation by forming a PSG film having an opening with an area smaller than the pad and a silicon nitride film having an opening with an area larger than the pad. Since a thin Ti—Cu film, which is an electrode for plating a metal for use, can be formed without any stepping, there is an effect that variations in bump height can be reduced.
第１図は本発明の一実施例を説明するための半導体チッ
プの断面図、第２図は従来技術による製造方法を説明す
るための半導体チップの断面図である。 １……半導体基板、２……パッド、３……PSG膜、４…
…シリコン窒化膜、5,5A……フォトレジスト膜、6,6A…
…Ti−Cu膜、７……バンプ、10A……第１の開口部、10B
……第２の開口部、15,15A……フォトレジスト膜。FIG. 1 is a sectional view of a semiconductor chip for explaining one embodiment of the present invention, and FIG. 2 is a sectional view of the semiconductor chip for explaining a manufacturing method according to the prior art. 1 ... Semiconductor substrate, 2 ... Pad, 3 ... PSG film, 4 ...
… Silicon nitride film, 5,5A …… Photoresist film, 6,6A…
... Ti-Cu film, 7 ... Bump, 10A ... First opening, 10B
... second opening, 15, 15A ... photoresist film.
Claims (1)
バンプ形成用のパッドと、前記パッドを含む全面に形成
されかつパッド上にパッドより小さい面積の開口部を有
するPSG膜と、前記PSG膜上に形成されかつ前記パッドの
上部にパッドより大きい面積の開口部を有するシリコン
窒化膜とを含むことを特徴とする半導体集積回路。1. A pad for forming a bump made of a metal film formed on a semiconductor substrate, a PSG film formed on the entire surface including the pad and having an opening on the pad with an area smaller than the pad, and the PSG A silicon nitride film formed on the film and having an opening having an area larger than the pad above the pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29940790A JP2644079B2 (en) | 1990-11-05 | 1990-11-05 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29940790A JP2644079B2 (en) | 1990-11-05 | 1990-11-05 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04171821A JPH04171821A (en) | 1992-06-19 |
| JP2644079B2 true JP2644079B2 (en) | 1997-08-25 |
Family
ID=17872165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29940790A Expired - Lifetime JP2644079B2 (en) | 1990-11-05 | 1990-11-05 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2644079B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19907168C1 (en) * | 1999-02-19 | 2000-08-10 | Micronas Intermetall Gmbh | Layer arrangement and method for its production |
| JP5867467B2 (en) * | 2013-09-03 | 2016-02-24 | トヨタ自動車株式会社 | Manufacturing method of semiconductor device |
-
1990
- 1990-11-05 JP JP29940790A patent/JP2644079B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04171821A (en) | 1992-06-19 |
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