JP2639959B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2639959B2
JP2639959B2 JP7198788A JP7198788A JP2639959B2 JP 2639959 B2 JP2639959 B2 JP 2639959B2 JP 7198788 A JP7198788 A JP 7198788A JP 7198788 A JP7198788 A JP 7198788A JP 2639959 B2 JP2639959 B2 JP 2639959B2
Authority
JP
Japan
Prior art keywords
main surface
semiconductor substrate
semiconductor device
main
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7198788A
Other languages
Japanese (ja)
Other versions
JPH01245556A (en
Inventor
洋明 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON INTAA KK
Original Assignee
NIPPON INTAA KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON INTAA KK filed Critical NIPPON INTAA KK
Priority to JP7198788A priority Critical patent/JP2639959B2/en
Publication of JPH01245556A publication Critical patent/JPH01245556A/en
Application granted granted Critical
Publication of JP2639959B2 publication Critical patent/JP2639959B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To increase a controllable current withstand voltage by a method wherein the whole surface on the side of one main surface of a semiconductor substrate is kept covering without performing window openings on an insulating protective film until a process for fixing with an alloy a temperature compensating plate on the semiconductor substrate and a heavy metal diffusion process for controlling the lifetime of minority carriers end. CONSTITUTION:A temperature compensating plate 9 consisting of such a metal as molybdenum is fixed with an alloy on the side of the main surface on the other side of a semiconductor substrate 1 through an Al foil 10 or the like in a state that one main surface of the substrate 1 is completely covered without performing window openings on an insulating protective film 7 consisting of an Si dioxide film or the like. After then, the window openings 8 are performed and thereafter, cathode electrodes 11 and gate electrodes 12 are formed on the surfaces of cathode segments 5 on the side of the main surface on one side of the substrate 1 and the surfaces of parts, which are used as gate parts, of a P-type layer 6 in the same way as the existing way. Thereby, the contamination of an Si surface and a boundary surface, which are exposed by metallic vapor to generate at the time of fixing with an alloy or by a heavy metal diffusion, is prevented. As a result, a controllable current withstand voltage can be increased.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、ゲート電流（Igt）及び順方向電圧降下
（VTM）値等の電気的特性が安定し、可制御電流耐量の
大きい半導体装置が得られる半導体装置の製造方法に関
する。The present invention relates to a semiconductor device having stable electric characteristics such as a gate current (Igt) and a forward voltage drop (V TM ) value and a large controllable current withstand capability. The present invention relates to a method for manufacturing a semiconductor device capable of obtaining the above.

［従来の技術］ 第２図に従来の半導体装置の製造法方を示す。[Prior Art] FIG. 2 shows a method of manufacturing a conventional semiconductor device.

まず、同図（ａ）に示すようにＮ型半導体基板１の両
主面にガリウム（Ga）を拡散し、Ｐ層2,3を形成する。
次に同図（ｂ）に示すように、上面のＰ層２にリン
（Ｐ）を拡散し、N+層４を形成する。First, as shown in FIG. 1A, gallium (G a ) is diffused on both main surfaces of the N-type semiconductor substrate 1 to form P layers 2 and 3.
Next, as shown in FIG. 3B, phosphorus (P) is diffused into the P layer 2 on the upper surface to form an N + layer 4.

次に、同時（ｃ）に示すように、フォトリソ技術によ
りN+層４を選択的にエッチング除去し、複数の島状のカ
ソードセグメント５及び複数のゲート領域となるＰ層６
を露出させる。次いで、同図（ｄ）に示すように上側の
Ｐ層２及びカソードセグメント５として形成したN+層４
の全面に二酸化シリコン膜等の絶縁保護膜７を形成す
る。Next, as shown simultaneously (c), the N + layer 4 is selectively etched away by the photolithography technique to form a plurality of island-shaped cathode segments 5 and a plurality of P layers 6 serving as gate regions.
To expose. Next, as shown in FIG. 4D, the upper P layer 2 and the N + layer 4 formed as the cathode segment 5 are formed.
An insulating protective film 7 such as a silicon dioxide film is formed on the entire surface of the substrate.

次に、同図（ｅ）に示すように上記のカソードセグメ
ント５及びゲート部となるＰ層６に電極金属を形成する
ための窓明け８を行なう。Next, as shown in FIG. 3E, a window 8 for forming an electrode metal is formed on the cathode segment 5 and the P layer 6 serving as a gate.

次に、同図（ｆ）に示すように半導体基板１の下面側
のＰ層３の表面、すなわち、この例では半導体基板１の
アノード側にモリブデン（Mo）等の金属からなる温度補
償板９がアルミニウム（Al）箔10等を介して合金・固着
される。Then, the lower surface of the P layer 3 on the surface of the semiconductor substrate 1 as shown in FIG. (F), i.e., the temperature compensation plate made of metal such as molybdenum (M o) to the anode side of the semiconductor substrate 1 in this example 9 is alloyed and fixed via an aluminum (Al) foil 10 or the like.

最後に、同図（ｇ）に示すように半導体基板１の一方
の主面側のカソードセグメント５の表面及びゲート部と
なるＰ層の表面６にカソード電極11及びゲート電極12を
形成する。Finally, as shown in FIG. 1G, a cathode electrode 11 and a gate electrode 12 are formed on the surface of the cathode segment 5 on one main surface side of the semiconductor substrate 1 and the surface 6 of the P layer serving as a gate.

［発明が解決しようとする課題］ 従来の半導体装置は上記のような工程を経て製作され
るので、次のような解決すべき課題がある。[Problem to be Solved by the Invention] Since a conventional semiconductor device is manufactured through the above-described steps, there are the following problems to be solved.

すなわち、下側のＰ層３の表面に温度補償板９を合金
・固着する以前の工程で半導体基板１上絶縁保護膜７
に、カソード電極11及びゲート電極12を形成すべく電極
金属を付着させるための窓明け８を行うため、その後の
温度補償板９の合金・固着工程でアルミニウム（Al）箔
10等の金属が溶融した際に、その金属の蒸気により絶縁
保護膜７の窓明け８の切り口の部分や露出シリコン面を
汚染し、そのため、局部的なカソードセグメントに対し
ゲート電流（Igt）及び順方向電圧降下（VTM）を増大さ
せる。また、少数キャリアのライフタイムを制御するた
めに金（Au）等の重金属をアノード側から拡散するよう
な半導体装置では、Alのみならず、Au等の重金属による
汚染も考えられ、上記Igt及びVTMの増大を助長すること
になる。In other words, in the step before the temperature compensating plate 9 is alloyed and fixed on the surface of the lower P layer 3, the insulating protective film 7 on the semiconductor substrate 1 is formed.
Next, in order to perform a window 8 for depositing an electrode metal to form a cathode electrode 11 and a gate electrode 12, an aluminum (Al) foil
When a metal such as 10 is melted, the vapor of the metal contaminates the cut portion of the window 8 of the insulating protective film 7 and the exposed silicon surface, so that the gate current (Igt) and the local Increase the forward voltage drop ( VTM ). In a semiconductor device in which a heavy metal such as gold (Au) diffuses from the anode side to control the lifetime of minority carriers, contamination by heavy metals such as Au as well as Al can be considered. This will help increase TM .

特に、ゲート・ターン・オフ・サイリスタ（GTO）の
場合、その可制御電流耐量は、各カソードセグメントの
Igt及びVTM値が均一になるほど向上するが、上記のよう
に局部的に不均一な部分が存在すると可制御電流耐量が
著しく低下してしまう。In particular, in the case of a gate turn-off thyristor (GTO), the controllable current withstand capability of each cathode segment
The more the Igt and VTM values become uniform, the better, but if there is a locally non-uniform portion as described above, the controllable current withstand capability is significantly reduced.

［発明の目的］ この発明は、上記のような問題点を解消するためには
されたもので、この種の半導体装置の高温放置試験等を
行なってもIgt及びVTMの値が変化せず、また、一方の主
面の多数のカソードセグメント間のIgt及びVTMの値を均
一にすることができ、可制御電流耐量の大きい半導体装
置の製造方法を提供することを目的とする。[Object of the Invention] The present invention has been made in order to solve the above problems, and the values of Igt and VTM do not change even when a high-temperature storage test or the like of this type of semiconductor device is performed. It is another object of the present invention to provide a method of manufacturing a semiconductor device having a large controllable current withstand value, wherein the values of Igt and VTM can be made uniform among a large number of cathode segments on one main surface.

［課題を解決するための手段］ この発明に係る半導体装置の製造方法は、半導体基板
へ温度補償板を合金付けする工程及び少数キャリアのラ
イフタイムを制御するための重金属拡散工程が終了する
までは、絶縁保護被膜に窓明けを施すことなく、半導体
基板の一主面側の全面を被覆しておくようにしたもので
ある。[Means for Solving the Problems] In the method of manufacturing a semiconductor device according to the present invention, a method of alloying a temperature compensating plate to a semiconductor substrate and a heavy metal diffusion step for controlling a minority carrier lifetime are completed. The entire surface of the semiconductor substrate on one main surface side is covered without opening the insulating protective film.

［作用］ この発明の半導体装置の製造方法においては、温度補
償板の合金・固着工程及び重金属拡散工程のように半導
体基板を高温下におく工程が終了するまで、半導体基板
の一主面側の全面を絶縁保護膜で覆っているため、合金
・固着時の金属蒸気及びライフタイム制御のための重金
属によるシリコン露出面の汚染等が回避でき、Igt及びV
TM値の局部的なばらつきを抑制し、その結果、可制御電
流耐量を大きくすることができる。[Operation] In the method for manufacturing a semiconductor device according to the present invention, until the step of keeping the semiconductor substrate at a high temperature, such as the alloy / fixing step of the temperature compensating plate and the heavy metal diffusion step, is completed, Since the entire surface is covered with an insulating protective film, contamination of the exposed silicon surface by metal vapor at the time of alloying and fixing and heavy metal for lifetime control can be avoided.
Local variation of the TM value is suppressed, and as a result, the controllable current withstand capability can be increased.

［実施例］ 以下に、この発明の実施例を説明する。Example An example of the present invention will be described below.

第１図に示した工程において、同図（ａ）ないし
（ｄ）の工程は従来と同様に実施される。In the steps shown in FIG. 1, the steps shown in FIGS. 1A to 1D are carried out in the same manner as in the prior art.

しかしながら、同図（ｃ）の工程では、二酸化シリコ
ン膜等からなる絶縁保護膜７に窓明けを施すことなく、
半導体基板１の一主面を完全に被覆した状態で、他方の
主面側にアルミニウム箔10等を介してモリブデン等の金
属からなる温度補償板９を合金・固着させる。しかる後
に、同図（ｆ）に示すように公知の方法で窓明け８を行
ない、その後は従来と同様に半導体基板１の一方の主面
側のカソードセグメント５の表面及びゲート部となるＰ
層６の表面にカソード電極11及びゲート電極12を形成す
る。However, in the process shown in FIG. 3C, the insulating protective film 7 made of a silicon dioxide film or the like is not opened without opening a window.
In a state where one main surface of the semiconductor substrate 1 is completely covered, a temperature compensating plate 9 made of metal such as molybdenum is alloyed and fixed to the other main surface via an aluminum foil 10 or the like. Thereafter, as shown in FIG. 3 (f), a window 8 is formed by a known method, and thereafter, the surface of the cathode segment 5 on one main surface side of the semiconductor substrate 1 and the P serving as a gate portion are formed in a conventional manner.
A cathode electrode 11 and a gate electrode 12 are formed on the surface of the layer 6.

次に、第３図に従来製法と本願発明の製法によって製
作されたGTOの高温放置試験によるVTMの変化を示す。同
図（ａ）は従来製法によるもので、VTMの初期値を1.0と
した時の変化は300時間経過後で約1.16倍増加してしま
うのに対し、本願発明の製法では、同図（ｂ）に示すよ
うに、同じくVTMの初期値を1.0とした時の変化は300時
間経過後で約1.03倍であり、格段の効果がある。Next, FIG. 3 shows a change in VTM of the GTO manufactured by the conventional manufacturing method and the manufacturing method of the present invention in a high-temperature storage test. FIG. 7A shows the result of the conventional manufacturing method, and the change when the initial value of VTM is set to 1.0 increases by about 1.16 times after 300 hours, whereas in the manufacturing method of the present invention, FIG. As shown in b), when the initial value of VTM is set to 1.0, the change is about 1.03 times after 300 hours, which is a remarkable effect.

［発明の効果］ この発明な上記のようにカソード領域及びゲート領域
等となる半導体基板の一方の主面側を二酸化シリコン膜
等の絶縁保護膜で完全に被覆した状態で、アノード側等
となる半導体基板の他方の主面側に温度補償板を合金・
固着又は重金属の拡散工程を実施するようにしたので、
合金・固着時に発生する金属蒸気により、あるいは重金
属の拡散により露出シリコン面や境界面の汚染が防止さ
れる。その結果、高温放置試験等を行なってもVTMの値
が長時間に亘ってほとんど変化しない。さらに、一方の
主面の多数のカソードセグメント間のIgt及びVTMの値を
均一にすることができ、例えばGTOでは可制御電流耐量
を大きくすることができる等の優れた効果がある。[Effects of the Invention] As described above, the semiconductor substrate serving as the cathode region and the gate region becomes the anode side in a state where one main surface side is completely covered with an insulating protective film such as a silicon dioxide film. A temperature compensation plate is alloyed on the other main surface side of the semiconductor substrate.
Since the fixation or heavy metal diffusion process was performed,
The contamination of the exposed silicon surface and the boundary surface is prevented by the metal vapor generated at the time of alloying / fixing or by the diffusion of heavy metal. As a result, the value of VTM hardly changes over a long period of time even when a high-temperature storage test or the like is performed. Further, it is possible to make the values of Igt and VTM uniform among a large number of cathode segments on one main surface. For example, in the case of GTO, there is an excellent effect that the controllable current resistance can be increased.

【図面の簡単な説明】 第１図（ａ）ないし（ｇ）は、この発明の半導体装置の
製造方法を示す工程図、第２図（ａ）ないし（ｇ）は、
従来の半導体装置の製造方法を示す工程図、第３図
（ａ），（ｂ）は従来製法と本願発明の製法とによって
製作されたGTOの高温放置試験におけるVTMの経時変化の
状態を比較したグラフである。 １……半導体基板 2,3……Ｐ層 ４……N+層 ５……カソードセグメント ７……絶縁保護被膜 ８……窓明け ９……温度補償板 10……アルミニウム箔BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to (g) are process diagrams showing a method for manufacturing a semiconductor device according to the present invention, and FIGS. 2 (a) to (g) are
FIGS. 3 (a) and 3 (b) are process diagrams showing a conventional method of manufacturing a semiconductor device, and FIG. 3 (a) and FIG. 3 (b) show a comparison of the state of VTM with time in a high-temperature storage test of a GTO manufactured by the conventional method and the method of the present invention It is the graph which did. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2,3 ... P layer 4 ... N + layer 5 ... Cathode segment 7 ... Insulating protective film 8 ... Opening 9 ... Temperature compensating plate 10 ... Aluminum foil

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】半導体基板の一方の主面に、複数の第１の
主電極及び複数の制御電極とが段差を有して設けられ、
他方の主面には第２の主電極が配置され、この主電極に
温度補償板が合金・固着される半導体装置の製造方法に
おいて、前記半導体基板の一方の主面に段差が設けられ
た後に、他方の主面と温度補償板とを合金・固着する工
程の実施に当り、前記合金・固着する工程が終了するま
で一方の主面の全面を絶縁保護膜で被覆しておくことを
特徴とする半導体装置の製造方法。1. A plurality of first main electrodes and a plurality of control electrodes are provided on one main surface of a semiconductor substrate with steps.
In a method for manufacturing a semiconductor device in which a second main electrode is disposed on the other main surface and a temperature compensation plate is alloyed and fixed to the main electrode, after a step is provided on one main surface of the semiconductor substrate, In performing the step of alloying and fixing the other main surface and the temperature compensating plate, the entire surface of one main surface is covered with an insulating protective film until the step of alloying and fixing is completed. Semiconductor device manufacturing method. 【請求項２】複数の第１の主電極及び複数の制御電極と
が段差を有して設けられ、他方の主面には第２の主電極
が配置され、この第２の主電極側から少数キャリアのラ
イフタイムを制御させるために重金属拡散がなされる半
導体装置の製造方法において、前記半導体基板の一方の
主面に段差が設けられた後に、他方の主面側から重金属
拡散をする工程の実施に当り、前記重金属拡散をする工
程が終了するまで一方の主面の全面を絶縁保護膜で被覆
しておくことを特徴とする半導体装置の製造方法。2. A plurality of first main electrodes and a plurality of control electrodes are provided with a step, and a second main electrode is arranged on the other main surface, and from the second main electrode side. In the method of manufacturing a semiconductor device in which heavy metal diffusion is performed to control the life time of minority carriers, after a step is provided on one main surface of the semiconductor substrate, the step of performing heavy metal diffusion from the other main surface side In carrying out the method, a method of manufacturing a semiconductor device, wherein the entire surface of one main surface is covered with an insulating protective film until the step of diffusing heavy metals is completed.
JP7198788A 1988-03-28 1988-03-28 Method for manufacturing semiconductor device Expired - Lifetime JP2639959B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7198788A JP2639959B2 (en) 1988-03-28 1988-03-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7198788A JP2639959B2 (en) 1988-03-28 1988-03-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01245556A JPH01245556A (en) 1989-09-29
JP2639959B2 true JP2639959B2 (en) 1997-08-13

Family

ID=13476323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7198788A Expired - Lifetime JP2639959B2 (en) 1988-03-28 1988-03-28 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2639959B2 (en)

Also Published As

Publication number Publication date
JPH01245556A (en) 1989-09-29

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