JP2625675B2 - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JP2625675B2 JP2625675B2 JP61049701A JP4970186A JP2625675B2 JP 2625675 B2 JP2625675 B2 JP 2625675B2 JP 61049701 A JP61049701 A JP 61049701A JP 4970186 A JP4970186 A JP 4970186A JP 2625675 B2 JP2625675 B2 JP 2625675B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal processing
- recording
- bias
- processing circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Semiconductor Integrated Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路に関し、特に映像及び音声の信号処
理をする記録・再生用集積回路を含む集積回路に関す
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit, and more particularly to an integrated circuit including a recording / reproducing integrated circuit for performing video and audio signal processing.
家庭用ビディオテープレコーダ（以降家庭用VTRと称
す）の映像及び音声の信号処理の集積化は、最近、特に
進んでおり、例えば、映像の信号処理に必要な機能の大
部分が同一の集積回路チップ内に収められたものも見う
けられる。このような映像及び音声の信号処理を含む記
録・再生用集積回路は、記録時に必要な信号処理機能
と、再生時に必要な信号処理機能の両方の一部分あるい
は全部を有すると共に、記録と再生とを切換えるための
バイアス切換信号用端子及びバイアス切換回路を、通
常、具備している。The integration of video and audio signal processing for home video tape recorders (hereinafter referred to as home VTRs) has been particularly advanced recently. For example, an integrated circuit in which most of the functions required for video signal processing are the same You can also see what is in the chip. A recording / reproducing integrated circuit including such video and audio signal processing has both a part or all of a signal processing function required at the time of recording and a signal processing function required at the time of reproduction, and performs recording and reproduction. A bias switching signal terminal and a bias switching circuit for switching are usually provided.
第２図は従来の記録・再生用集積回路の一例のブロッ
ク図、第３図（ａ）は記録系信号処理回路の一例のブロ
ック図、第３図（ｂ）は再生系信号処理回路の一例のブ
ロック図である。FIG. 2 is a block diagram of an example of a conventional recording / reproducing integrated circuit, FIG. 3 (a) is a block diagram of an example of a recording signal processing circuit, and FIG. 3 (b) is an example of a reproduction signal processing circuit. It is a block diagram of.
この従来例は、第２図に示すように、記録・再生用集
積回路21に記録系信号処理回路３と再生系信号処理回路
４とバイアス切換回路22とを含み、バイアス切換回路22
が、バイアス切換信号用端子14を介して、スイッチ回路
25からバイアス切換信号26を受け、これが第１の信号
（例えばバイアス電源電圧VB）のとき記録系信号処理回
路３のみに記録系バイアス27を供給し、バイアス切換信
号26が第２の信号（例えば接地電位0V）のとき再生系信
号処理回路４のみに再生系バイアス28を供給する。従っ
て、バイアス切換信号26が、第１の信号（例えばバイア
ス電源電圧VB）のとき記録系信号処理回路３が動作状
態、再生系信号処理回路４が休止状態となり、第２の信
号（例えば接地電圧0V）のとき記録系信号処理回路３が
休止状態、再生系信号処理回路４が動作状態となる。In this conventional example, as shown in FIG. 2, a recording / reproducing integrated circuit 21 includes a recording signal processing circuit 3, a reproducing signal processing circuit 4, and a bias switching circuit 22, and a bias switching circuit 22.
Is connected to the switch circuit via the bias switching signal terminal 14.
25, a bias switching signal 26 is received, and when this is a first signal (for example, a bias power supply voltage V B ), a recording system bias 27 is supplied only to the recording system signal processing circuit 3, and the bias switching signal 26 becomes the second signal ( For example, when the ground potential is 0 V), the reproduction system bias 28 is supplied only to the reproduction system signal processing circuit 4. Therefore, when the bias switching signal 26 is the first signal (for example, the bias power supply voltage V B ), the recording signal processing circuit 3 is in the operation state, the reproduction signal processing circuit 4 is in the stop state, and the second signal (for example, ground) When the voltage is 0 V), the recording-system signal processing circuit 3 is in a pause state, and the reproduction-system signal processing circuit 4 is in an operating state.
記録系信号処理回路３は、第３図（ａ）に示すよう
に、入力端子９と出力端子10との間をAGC回路31,低域フ
ィルタ（LPF）33,非線形エンファシス回路34,クランプ
回路35,メインエンファシス回路36,ホワイト・ダークク
リップ回路37,周波数変調器38及び記録増幅器39の順に
それらを接続すると共にAGC回路31の出力をAGC検出回路
32を介してAGC回路31にフィードバックするという構成
をしている。As shown in FIG. 3A, the recording signal processing circuit 3 includes an AGC circuit 31, a low-pass filter (LPF) 33, a non-linear emphasis circuit 34, and a clamp circuit 35 between the input terminal 9 and the output terminal 10. , A main emphasis circuit 36, a white / dark clip circuit 37, a frequency modulator 38, and a recording amplifier 39, which are connected in this order, and the output of the AGC circuit 31 is detected by an AGC detection circuit.
The configuration is such that feedback is provided to the AGC circuit 31 via the AGC circuit 32.
従って、記録系信号処理回路３の入力端子９に映像信
号を入力すれば、内部回路によって所定のFM信号に変換
し出力端子10に出力し、更にこの信号をビディオヘッド
を通じて磁気テープに記録することができる。Therefore, when a video signal is input to the input terminal 9 of the recording system signal processing circuit 3, it is converted into a predetermined FM signal by an internal circuit and output to the output terminal 10, and this signal is further recorded on a magnetic tape through a video head. Can be.
又、再生系信号処理回路４は、第３図（ｂ）に示すよ
うに、入力端子12と出力端子13との間を再生増幅器41,
リミッタ回路42,FM復調器43,低域フィルタ（LPF）44,メ
インデエンファシス回路45,非線形デエンファシス回路4
6,ノイズキャンセラー回路47,輝度，色信号ミックス回
路（Y/Cミックス回路）48及び出力増幅器49の順にこれ
らを接続した構成をしている。Also, as shown in FIG. 3 (b), the reproduction system signal processing circuit 4 connects a reproduction amplifier 41 between the input terminal 12 and the output terminal 13,
Limiter circuit 42, FM demodulator 43, low-pass filter (LPF) 44, main de-emphasis circuit 45, nonlinear de-emphasis circuit 4
6, a noise canceller circuit 47, a luminance / color signal mix circuit (Y / C mix circuit) 48, and an output amplifier 49 are connected in this order.
この再生系信号処理回路４は、記録系信号処理回路３
とは反対に、ビディオヘッドから読取った磁気テープの
記録内容すなわちFM信号を入力端子11を介して入力すれ
ば、これを映像信号に変換し出力端子12に出力すること
ができる。The reproduction-system signal processing circuit 4 includes the recording-system signal processing circuit 3.
Conversely, if the recorded content of the magnetic tape read from the video head, that is, the FM signal is input through the input terminal 11, it can be converted into a video signal and output to the output terminal 12.
上述した従来の記録・再生用集積回路は、外部のバイ
アス切換信号に基づいて記録系信号処理回路又は再生系
信号処理回路のいずれか一方のみ選択してバイアスを供
給するようになっているので、各々の回路機能を別々に
選別や検査をしなければならずこの従来例のように多く
の機能を内蔵している場合には選別や検査の工数が非常
にかかるという欠点がある。特に、記録・再生用集積回
路にとって非常に重要な、記録と再生との相反関係（例
えば周波数変調器とFM復調器，エンファシス回路とデエ
ンファシス回路などの相反関係）の選別や検査を一時に
できないので手間がかかった。Since the conventional recording / reproducing integrated circuit described above is configured to select and supply only one of the recording-system signal processing circuit and the reproduction-system signal processing circuit based on an external bias switching signal, Each circuit function must be separately selected and inspected, and when many functions are built in as in this conventional example, there is a disadvantage that the number of steps of the selection and inspection is extremely long. In particular, it is not possible to select or inspect the reciprocal relationship between recording and reproduction (for example, the reciprocal relationship between a frequency modulator and an FM demodulator, an emphasis circuit and a de-emphasis circuit), which is very important for a recording / reproducing integrated circuit. It took time.
本発明の目的は、記録系信号処理回路及び再生系信号
処理回路の選別や検査の工数を低減し、しかも記録と再
生との相反関係の選別や検査を一時にできる集積回路を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit capable of reducing the number of steps of selecting and inspecting a recording signal processing circuit and a reproducing signal processing circuit and inspecting the reciprocal relationship between recording and reproduction at the same time. is there.
本発明の集積回路は、ビデオテープレコーダの映像お
よび音声信号の記録系信号処理回路と、前記映像および
音声信号の再生系信号処理回路とを備える集積回路にお
いて、 それぞれ選択的に供給される第１および第２のバイア
ス制御信号にそれぞれ応答して前記記録系信号処理回路
および再生系信号処理回路の各々の動作用にそれぞれ供
給する第１および第２のバイアス信号を単独に発生し第
３のバイアス制御信号に応答して前記第１および第２の
バイアス信号を同時に発生するバイアス制御回路を備え
て構成される。An integrated circuit according to the present invention is an integrated circuit including a video signal and audio signal recording system signal processing circuit of a video tape recorder, and a video and audio signal reproduction system signal processing circuit. A first bias signal and a second bias signal which are respectively supplied for operation of each of the recording system signal processing circuit and the reproduction system signal processing circuit in response to the third bias control signal and the third bias control signal, respectively. A bias control circuit for simultaneously generating the first and second bias signals in response to the control signal;
次に、本発明の一実施例について図面を参照して説明
する。Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のブロック図である。 FIG. 1 is a block diagram of one embodiment of the present invention.
第１図に示すように、この実施例は、記録・再生用集
積回路１に記録系信号処理回路３と再生系信号処理回路
４とバイアス制御回路２とを含み、バイアス制御回路２
がバイアス制御信号用端子13を介してスイッチ回路５の
バイアス制御信号６を入力し、これが第１の信号（例え
ばバイアス電源電圧VB）のとき記録系信号処理回路３の
みに記録系バイアス７を供給し、バイアス制御信号６が
第２の信号（例えば接地電位0V）のとき再生系信号処理
回路４のみに再生系バイアス８を供給し、バイアス制御
信号６が第３の信号（例えばバイアス制御用電圧VX）の
とき記録系信号処理回路３及び再生系信号処理回路４に
それぞれ記録系バイアス７及び再生系バイアス８を同時
に供給する。ここで、バイアス制御用電圧VXは ０＜VX＜VB とする。As shown in FIG. 1, in this embodiment, a recording / reproducing integrated circuit 1 includes a recording system signal processing circuit 3, a reproducing system signal processing circuit 4, and a bias control circuit 2, and a bias control circuit 2
Receives the bias control signal 6 of the switch circuit 5 via the bias control signal terminal 13, and when this is the first signal (for example, the bias power supply voltage V B ), the recording system bias 7 is applied only to the recording system signal processing circuit 3. When the bias control signal 6 is the second signal (for example, ground potential 0 V), the reproduction system bias 8 is supplied only to the reproduction system signal processing circuit 4 and the bias control signal 6 is supplied to the third signal (for example, bias control signal). At the same time supplies the recording signal processor 3 and the reproducing system signal processing circuit, respectively recording system bias 7 and the reproducing system bias 8 to 4 when the voltage V X). The bias control voltage V X is the 0 <V X <V B.
第１表にバイアス制御信号６と記録系信号処理回路３
の記録系バイアス７及び再生系信号処理回路４の再生系
バイアス８の供給・遮断状態との関係を示した。Table 1 shows the bias control signal 6 and the recording signal processing circuit 3
The relationship between the recording system bias 7 and the supply / cutoff state of the reproduction system bias 8 of the reproduction system signal processing circuit 4 is shown.
従って、この実施例では、第３の信号のときに記録系
バイアス７と再生系バイアス８とを同時に供給し、記録
系信号処理回路３と再生系信号処理回路４とが共に動作
状態となる。Therefore, in this embodiment, the recording system bias 7 and the reproduction system bias 8 are simultaneously supplied at the time of the third signal, and both the recording system signal processing circuit 3 and the reproduction system signal processing circuit 4 are in operation.
その結果、記録系信号処理回路３と再生系信号処理回
路４との特性測定を同時にすることによって、バイアス
切換の手間と測定時間を減らすことは勿論、記録と再生
の両方の特性に拘わる相反関係（例えば、周波数変調器
とFM復調器、エンファシス回路とデエンファシス回路な
どの相反関係）についての測定も一時にできる。例え
ば、第３図（ａ）に示した周波数変調器38の入力に映像
信号を入れ、その出力であるFM信号を第３図（ｂ）に示
したリミッタ回路42に直接入力し、これをFM復調器43を
介して出力すれば、再び映像信号が得られるので、この
ような方法を使えば、周波数の変調と復調との相反関係
についての測定が一時にできる。 As a result, by simultaneously measuring the characteristics of the recording-system signal processing circuit 3 and the reproduction-system signal processing circuit 4, it is possible to reduce the labor and the measurement time of the bias switching, and of course, the reciprocal relation relating to both the recording and reproduction characteristics. (For example, the reciprocal relationship between a frequency modulator and an FM demodulator, and an emphasis circuit and a de-emphasis circuit) can be measured at one time. For example, a video signal is input to the input of the frequency modulator 38 shown in FIG. 3A, and the FM signal as the output is directly input to the limiter circuit 42 shown in FIG. If the signal is output via the demodulator 43, a video signal can be obtained again. Therefore, by using such a method, measurement of the reciprocal relationship between frequency modulation and demodulation can be performed at once.
なお、この実施例では、バイアス制御信号として三種
の電圧を使っているがこれに限るものではなく電流値や
パルス信号を用いても良いことは自明である。In this embodiment, three kinds of voltages are used as the bias control signal. However, the present invention is not limited to this, and it is obvious that a current value or a pulse signal may be used.
又、記録系信号処理回路及び再生系信号処理回路が、
第３図（ａ）及び（ｂ）に示した回路の全てを含んでい
なくとも良い。Also, the recording system signal processing circuit and the reproduction system signal processing circuit
It is not necessary to include all of the circuits shown in FIGS. 3 (a) and 3 (b).
以上説明したように本発明は、バイアス制御信号が第
３の信号のときに、記録系信号処理回路及び再生系信号
処理回路のそれぞれに記録系バイアス及び再生系バイア
スを同時に供給できるので、記録系信号処理回路と再生
系信号処理回路との特性を同時に測定でき従来例に比べ
て選別及び検査の工数の低減が図れるという効果があ
る。特に、記録・再生用集積回路にとって非常に重要な
ファクターである記録と再生との相反関係（例えば周波
数変調器とFM復調器、エンファシス回路とデエンファシ
ス回路などの相反関係）の測定を一時にできるので、手
間がかからずしかも誤差の少ない選別や検査が可能にな
るという効果がある。As described above, according to the present invention, when the bias control signal is the third signal, the recording system bias and the reproduction system bias can be simultaneously supplied to the recording system signal processing circuit and the reproduction system signal processing circuit, respectively. The characteristics of the signal processing circuit and the reproduction system signal processing circuit can be measured simultaneously, which has the effect of reducing the number of steps of selection and inspection as compared with the conventional example. In particular, the reciprocal relation between recording and reproduction (for example, the reciprocal relation between a frequency modulator and an FM demodulator, an emphasis circuit and a de-emphasis circuit, etc.), which is a very important factor for a recording / reproduction integrated circuit, can be measured at one time. Therefore, there is an effect that sorting and inspection can be performed without any trouble and with little error.
第１図は本発明の一実施例のブロック図、第２図は従来
の記録・再生用集積回路の一例のブロック図、第３図
（ａ）は記録系信号処理回路の一例のブロック図、第３
図（ｂ）は再生系信号処理回路の一例のブロック図であ
る。 １……記録・再生用集積回路、２……バイアス制御回
路、３……記録系信号処理回路、４……再生系信号処理
回路、５……スイッチ回路、６……バイアス制御信号、
７……記録系バイアス、８……再生系バイアス、９……
入力端子、10……出力端子、11……入力端子、12……出
力端子、13……バイアス制御信号用端子、14……バイア
ス切換信号用端子、21……記録・再生用集積回路、22…
…バイアス切換回路、25……スイッチ回路、26……バイ
アス切換信号、27……記録系バイアス、28……再生系バ
イアス、31……AGC回路、32……AGC検出回路、33……低
域フィルタ（LPF）、34……非線形エンファシス回路、3
5……クランプ回路、36……メインエンファシス回路、3
7……ホワイト・ダーククリップ回路、38……周波数変
調器、39……記録増幅器、41……再生増幅器、42……リ
ミッタ回路、43……FM復調器、44……低域フィルタ（LP
F）、45……メインデエンファシス回路、46……非線形
デエンファシス回路、47……ノイズキャンセラー回路、
48……輝度，色信号ミックス回路（Y/Cミックス回
路）、49……出力増幅器、VB……バイアス電源電圧、VX
……バイアス制御用電圧。1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of an example of a conventional integrated circuit for recording / reproduction, FIG. 3 (a) is a block diagram of an example of a recording-system signal processing circuit, Third
FIG. 1B is a block diagram of an example of a reproduction system signal processing circuit. DESCRIPTION OF SYMBOLS 1 ... Integrated circuit for recording / reproduction, 2 ... Bias control circuit, 3 ... Signal processing circuit for recording, 4 ... Signal processing circuit for reproduction, 5 ... Switch circuit, 6 ... Bias control signal,
7: Recording system bias, 8: Reproduction system bias, 9:
Input terminal 10, output terminal 11, input terminal 12, output terminal 13, bias control signal terminal 14, bias switching signal terminal 21, recording / reproducing integrated circuit 22, …
... Bias switching circuit, 25 ... Switch circuit, 26 ... Bias switching signal, 27 ... Recording system bias, 28 ... Reproduction system bias, 31 ... AGC circuit, 32 ... AGC detection circuit, 33 ... Low frequency Filter (LPF), 34 ... Non-linear emphasis circuit, 3
5 ... clamp circuit, 36 ... main emphasis circuit, 3
7: White / dark clip circuit, 38: Frequency modulator, 39: Recording amplifier, 41: Reproduction amplifier, 42: Limiter circuit, 43: FM demodulator, 44: Low-pass filter (LP
F), 45: Main de-emphasis circuit, 46: Non-linear de-emphasis circuit, 47: Noise canceller circuit,
48 ...... luminance, color signal mixing circuit (Y / C mixing circuit), 49 ...... output amplifier, V B ...... bias supply voltage, V X
…… Bias control voltage.
Claims (1)
号の記録系信号処理回路と、前記映像および音声信号の
再生系信号処理回路とを備える集積回路において、 それぞれ選択的に供給される第１および第２のバイアス
制御信号にそれぞれ応答して前記記録系信号処理回路お
よび再生系信号処理回路の各々の動作用にそれぞれ供給
する第１および第２のバイアス信号を単独に発生し第３
のバイアス制御信号に応答して前記第１および第２のバ
イアス信号を同時に発生するバイアス制御回路を備える
ことを特徴とする集積回路。1. An integrated circuit comprising a video signal and audio signal recording system signal processing circuit of a video tape recorder and a video and audio signal reproduction system signal processing circuit, wherein first and second signals selectively supplied are respectively provided. The first and second bias signals respectively supplied for the respective operations of the recording-system signal processing circuit and the reproduction-system signal processing circuit are individually generated in response to
And a bias control circuit for simultaneously generating the first and second bias signals in response to the bias control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61049701A JP2625675B2 (en) | 1986-03-06 | 1986-03-06 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61049701A JP2625675B2 (en) | 1986-03-06 | 1986-03-06 | Integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62206869A JPS62206869A (en) | 1987-09-11 |
| JP2625675B2 true JP2625675B2 (en) | 1997-07-02 |
Family
ID=12838487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61049701A Expired - Lifetime JP2625675B2 (en) | 1986-03-06 | 1986-03-06 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2625675B2 (en) |
-
1986
- 1986-03-06 JP JP61049701A patent/JP2625675B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62206869A (en) | 1987-09-11 |
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