JP2610866B2 - Semiconductor resistance element - Google Patents
Semiconductor resistance elementInfo
- Publication number
- JP2610866B2 JP2610866B2 JP62072004A JP7200487A JP2610866B2 JP 2610866 B2 JP2610866 B2 JP 2610866B2 JP 62072004 A JP62072004 A JP 62072004A JP 7200487 A JP7200487 A JP 7200487A JP 2610866 B2 JP2610866 B2 JP 2610866B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- metal silicide
- polycrystalline silicon
- silicon resistor
- covering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体抵抗素子に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor resistor.
従来より、集積回路の抵抗素子として多結晶シリコン
抵抗体が寄生容量の少ないために多く使用されている。2. Description of the Related Art Conventionally, a polycrystalline silicon resistor has been widely used as a resistance element of an integrated circuit because of its low parasitic capacitance.
第２図は従来の半導体抵抗素子の一例の半導体チップ
の断面図である。FIG. 2 is a sectional view of a semiconductor chip as an example of a conventional semiconductor resistance element.
半導体ウェーハ１の上にフィールド絶縁膜２が形成さ
れ、この上に不純物が導入され所定の面積抵抗率を持ち
所定の形状にした多結晶シリコン抵抗体３が形成され
る。A field insulating film 2 is formed on a semiconductor wafer 1, on which impurities are introduced to form a polycrystalline silicon resistor 3 having a predetermined area resistivity and a predetermined shape.
気相成長法などで形成させた絶縁膜４に対して所定の
間隔Ｌを置いた二つのコンタクト孔７が形成され、コン
トタクト孔５の底面に多結晶シリコン抵抗体３のオーミ
ックコンタクトを得るためPt,Pd,W,Ti及Moとシリコンと
の金属珪化物層６を形成する。Two contact holes 7 are formed at predetermined intervals L with respect to the insulating film 4 formed by a vapor phase growth method or the like, and an ohmic contact of the polycrystalline silicon resistor 3 is obtained at the bottom of the contact hole 5. A metal silicide layer 6 of Pt, Pd, W, Ti, Mo and silicon is formed.
この時使用時の温度における配線層のAlとの反応を防
ぐためにTi等バリアメタル層７を形成し、その上にAlの
配線層８を形成し、半導体シリコン抵抗素子が完成す
る。At this time, a barrier metal layer 7 such as Ti is formed in order to prevent a reaction with Al of the wiring layer at the temperature at the time of use, and an Al wiring layer 8 is formed thereon, thereby completing the semiconductor silicon resistance element.
上述の半導体抵抗素子の抵抗値Ｒは、一般に第（１）
式で決定される。Generally, the resistance value R of the above-described semiconductor resistance element is (1)
Determined by the formula.
ρs:多結晶シリコン抵抗体の面積抵抗率、 L:抵抗長、Ｗ＝抵抗幅、Rc:コンタクト抵抗、 で与えられる。 ρs: area resistivity of the polycrystalline silicon resistor, L: resistance length, W = resistance width, Rc: contact resistance.
ここで、抵抗層Ｌは二つの金属珪化物層の間隔Ｌ、す
なわち二つのコンタクト孔５の間隔Ｌが実効的な値とな
る。Here, the effective value of the resistance layer L is the distance L between the two metal silicide layers, that is, the distance L between the two contact holes 5.
一般に、絶縁膜４がシリコン酸化膜である場合に、コ
ンタクト孔５の開孔には弗化水素系による等方性のウェ
ットエッチングや、CF4ガスによる異方性の反応性イオ
ンエッチング（以下RIEという）を適用している。Generally, when the insulating film 4 is a silicon oxide film, the opening of the contact hole 5 is formed by isotropic wet etching using hydrogen fluoride or anisotropic reactive ion etching (hereinafter, RIE) using CF 4 gas. Has been applied.
上述した従来の半導体抵抗素子は、コンタクト孔の開
孔加工寸法精度が実効的な抵抗長に大きく影響するの
で、抵抗の精度改善のために抵抗長を大きくとると、高
集積化と高速化をさまたげるという問題があった。In the conventional semiconductor resistor described above, the dimensional accuracy of the contact hole opening greatly affects the effective resistance length. Therefore, if the resistance length is increased to improve the resistance accuracy, high integration and high speed operation will be achieved. There was a problem of shutting down.
第３図は第２図の配線層及びバリヤメタル層を除いた
半導体チップの平面図である。FIG. 3 is a plan view of the semiconductor chip excluding the wiring layer and the barrier metal layer of FIG.
前述の等方性エッチングでは、二つのコントクト孔5a
間を間隔Laにとっても、横方向のエッチングが行われる
ために、実効的なコンタクト孔5bは誤差△Ｌだけ広が
り、開孔後の間隔LbはLa−２△Ｌとなる。In the aforementioned isotropic etching, two contact holes 5a are formed.
Even when the interval is La, the effective contact hole 5b is widened by an error ΔL because the lateral etching is performed, and the interval Lb after the opening is La−2LaL.
ここで、コンタクト抵抗Rcを無視すると、（１）式に
よる抵抗値Ｒの誤差は２△L/Lとなる。Here, ignoring the contact resistance Rc, the error of the resistance value R according to the equation (1) is 2 △ L / L.
従って、La＝６μm,△Ｌ＝0,3μｍとすると10％の寸
法誤差を生じるので、この寸法誤差は３％以下にするに
はＬが20μｍ必要となり、抵抗素子の高集積化や高速特
性の障害となる。Therefore, if La = 6 μm and ΔL = 0,3 μm, a dimensional error of 10% occurs. To reduce the dimensional error to 3% or less, L is required to be 20 μm. It is an obstacle.
一方、RIEによる異方性エッチングも、ホトレジスト
膜圧を厚く設定する必要があるために、マスクパターン
転写時の転写精度は悪く、同様に△Ｌの誤差を生じる。On the other hand, in the anisotropic etching by RIE, since the photoresist film pressure needs to be set to be large, the transfer accuracy at the time of transferring the mask pattern is poor, and similarly, an error of ΔL occurs.
本発明の目的は、抵抗値の精度が良い高集積度で高速
度の半導体抵抗素子を抵抗することにある。SUMMARY OF THE INVENTION An object of the present invention is to resist a high-density, high-speed semiconductor resistance element having a high resistance value accuracy.
本発明の半導体抵抗素子は、 （Ａ） 半導体ウェーハの一主面を覆うフィールド絶縁
膜の上に選択的に形成された所定の抵抗率を有する多結
晶シリコン抵抗体、 （Ｂ） 前記多結晶シリコン抵抗体の表面に形成された
所定の部分を覆う少なくとも一つの絶縁膜マスク、 （Ｃ） 前記多結晶シリコン抵抗体の前記絶縁膜マスク
に覆われていない露出面を覆う金属珪化物層 （Ｄ） 前記フィールド絶縁膜、前記絶縁膜マスク及び
前記金属珪化物層の全表面を覆う絶縁膜、 （Ｅ） 前記絶縁膜に選択的に形成されて前記金属珪化
物層を露出する少なくとも一つのコンタクト孔、 （Ｆ） 前記金属珪化物層の露出部と接続する配線層、 を含んで構成されている。(A) a polycrystalline silicon resistor having a predetermined resistivity selectively formed on a field insulating film covering one main surface of a semiconductor wafer; (B) the polycrystalline silicon At least one insulating film mask covering a predetermined portion formed on the surface of the resistor; (C) a metal silicide layer covering an exposed surface of the polycrystalline silicon resistor that is not covered with the insulating film mask; An insulating film covering the entire surface of the field insulating film, the insulating film mask and the metal silicide layer; (E) at least one contact hole selectively formed in the insulating film to expose the metal silicide layer; (F) a wiring layer connected to the exposed portion of the metal silicide layer.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の半導体チップの断面図で
ある。FIG. 1 is a sectional view of a semiconductor chip according to one embodiment of the present invention.
半導体ウェーハ１上に形成されたフィールド絶縁膜２
の上に、一導電形の不純物を導入し、面積抵抗率が２〜
５Ω／□の多結晶シリコン抵抗体３を形成する。Field insulating film 2 formed on semiconductor wafer 1
On top of this, an impurity of one conductivity type is introduced, and the area resistivity is 2 to 2.
A 5Ω / □ polycrystalline silicon resistor 3 is formed.
実効的な抵抗長Lcとなる領域に、絶縁膜4aとして50〜
100nm程度の厚さにシリコン酸化膜を形成し多結晶シリ
コン抵抗体３の表面の一部を覆う。In the region where the effective resistance length Lc is, 50-
A silicon oxide film is formed to a thickness of about 100 nm to cover a part of the surface of the polycrystalline silicon resistor 3.
この時絶縁膜4aのパターン形状の形成方法としては、
RIE等の異方性エッチングを適用することによりパター
ン寸法の精度を上げることができる。At this time, as a method of forming the pattern shape of the insulating film 4a,
By applying anisotropic etching such as RIE, the accuracy of the pattern dimension can be improved.
また絶縁膜4aでは、ピンホールが生じない程度に膜厚
を薄く設定することにより、エッチング精度も良好とな
る。In addition, by setting the thickness of the insulating film 4a to be small enough to prevent pinholes, the etching accuracy is improved.
一方、絶縁膜4aに覆われない二つの領域は従来と同じ
金属珪化物層６を絶縁膜4aをマスクとして選択的に形成
され、それらの間隔Lcは自己整合されて等しい。珪化物
の熱処理としては例えば白金珪化物形成の場合はPt層の
厚さ20〜40nmに対して窒素雰囲気で500〜550℃の加熱を
10〜20分程度行なう。On the other hand, two regions which are not covered with the insulating film 4a are selectively formed using the same metal silicide layer 6 as in the prior art using the insulating film 4a as a mask, and their intervals Lc are self-aligned and equal. As the heat treatment of the silicide, for example, in the case of forming platinum silicide, the Pt layer is heated at 500 to 550 ° C. in a nitrogen atmosphere to a thickness of 20 to 40 nm.
Perform for about 10 to 20 minutes.
この多結晶シリコン抵抗体３は、従来の多結晶シリコ
ン抵抗体と同様にして、シリコン酸化膜あるいはPSG膜
などの絶縁膜４で覆われ、二つのコンタクト孔５が金属
珪化物層６上に間隔Laを置いて開孔され、Ti等のバリヤ
メタル層７を介して配線層８と接続される。This polycrystalline silicon resistor 3 is covered with an insulating film 4 such as a silicon oxide film or a PSG film in the same manner as a conventional polycrystalline silicon resistor, and two contact holes 5 are formed on the metal silicide layer 6 with an interval. It is opened with La placed, and is connected to the wiring layer 8 via a barrier metal layer 7 such as Ti.
ここで（１）式の半導体抵抗素子の抵抗値Ｒを決定す
る実効的な抵抗長Ｌは、二つの金属珪化物６の間隔Lcで
あり、設計的に二つのコントクト孔５の間隔Laとは無関
係である。Here, the effective resistance length L that determines the resistance value R of the semiconductor resistance element of the equation (1) is the distance Lc between the two metal silicides 6, and the distance La between the two contact holes 5 is designed by design. Irrelevant.
従って、抵抗Ｒの誤差は間隔Lcの寸法誤差にのみ依存
する。Therefore, the error of the resistor R depends only on the dimensional error of the interval Lc.
金属珪化物層６の間隔Lcは、4aの長さの精度で決まる
が、一般にRIEを用いた薄い絶縁膜4aのエッチング精度
が極めて高く、間隔Lcが６μｍに対して△Lcを0.1μｍ
にする事は容易である。The interval Lc between the metal silicide layers 6 is determined by the accuracy of the length of 4a. In general, the etching accuracy of the thin insulating film 4a using RIE is extremely high.
It is easy to do.
〔発明の効果〕 以上説明したように本発明は、集積回路に使用される
多結晶シリコン抵抗体の実効的な抵抗長を薄い絶縁膜の
RIEエッチング精度で決定することにより、高集積度の
高速度の半導体抵抗素子が得られるという効果がある。[Effects of the Invention] As described above, the present invention reduces the effective resistance length of a polycrystalline silicon resistor used for an integrated circuit by a thin insulating film.
By determining the RIE etching accuracy, there is an effect that a highly integrated and high-speed semiconductor resistance element can be obtained.
第１図は本発明の一実施例の半導体チップの断面図、第
２図は従来の半導体抵抗素子の一例の半導体チップの断
面図、第３図は第２図の配線用及びバリヤメタル層を除
いた半導体チップの平面図である。 １……半導体ウェーハ、２……フィールド絶縁膜、３…
…多結晶シリコン抵抗体、4,4a……絶縁膜パターン、５
……コンタクト孔、９……コンタクトマスク孔、Ll……
抵抗長。1 is a cross-sectional view of a semiconductor chip according to one embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor chip as an example of a conventional semiconductor resistor, and FIG. 3 is a view of FIG. 2 excluding wiring and barrier metal layers. FIG. 3 is a plan view of a semiconductor chip that has been set. 1 ... semiconductor wafer, 2 ... field insulating film, 3 ...
… Polycrystalline silicon resistor, 4,4a …… Insulating film pattern, 5
... contact hole, 9 ... contact mask hole, Ll ...
Resistance length.
Claims (1)
絶縁膜の上に選択的に形成された所定の抵抗率を有する
多結晶シリコン抵抗体と、前記多結晶シリコン抵抗体の
両端部分を除く表面に形成された所定の膜厚を有する絶
縁膜マスクと、前記多結晶シリコン抵抗体の前記両端部
分上の前記絶縁膜マスクに覆われていない露出面を選択
的に覆いそれぞれ前記所定の膜厚よりも薄い膜厚を有す
る第１及び第２の金属硅化物層と、前記フィールド絶縁
膜、前記絶縁膜マスク並びに前記第１及び第２の金属硅
化物層の全表面を覆い前記所定の膜厚よりも厚い膜厚を
有する層間絶縁膜と、前記層間絶縁膜に選択的に形成さ
れて前記第１及び第２の金属硅化物層の各々の一部を露
出する第１及び第２のコンタクト孔と、前記第１及び第
２の金属硅化物層の露出部と接続する第１及び第２の配
線層とを有し、前記第１及び第２の金属硅化物層にはさ
まれた前記絶縁膜マスクの長さによって抵抗値が決定さ
れることを特徴とする半導体抵抗素子。1. A polycrystalline silicon resistor having a predetermined resistivity selectively formed on a field insulating film covering one main surface of a semiconductor wafer, and a surface excluding both end portions of the polycrystalline silicon resistor. An insulating film mask having a predetermined thickness formed on the substrate; and selectively covering exposed surfaces of the polycrystalline silicon resistor on the both end portions which are not covered with the insulating film mask. A first and a second metal silicide layer having a small thickness, and covering the entire surface of the field insulating film, the insulating film mask, and the first and the second metal silicide layers. An interlayer insulating film having a relatively large thickness, first and second contact holes selectively formed in the interlayer insulating film and exposing a part of each of the first and second metal silicide layers; , The first and second metal silicide layers It has first and second wiring layers connected to an exposed portion, and a resistance value is determined by a length of the insulating film mask sandwiched between the first and second metal silicide layers. Characteristic semiconductor resistance element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072004A JP2610866B2 (en) | 1987-03-25 | 1987-03-25 | Semiconductor resistance element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62072004A JP2610866B2 (en) | 1987-03-25 | 1987-03-25 | Semiconductor resistance element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63237458A JPS63237458A (en) | 1988-10-03 |
| JP2610866B2 true JP2610866B2 (en) | 1997-05-14 |
Family
ID=13476840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62072004A Expired - Fee Related JP2610866B2 (en) | 1987-03-25 | 1987-03-25 | Semiconductor resistance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2610866B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04313266A (en) * | 1991-04-10 | 1992-11-05 | Fuji Xerox Co Ltd | Thin-film semiconductor device |
| JP3935687B2 (en) * | 2001-06-20 | 2007-06-27 | アルプス電気株式会社 | Thin film resistance element and manufacturing method thereof |
| JP5138274B2 (en) | 2007-05-25 | 2013-02-06 | 三菱電機株式会社 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5854663A (en) * | 1981-09-28 | 1983-03-31 | Nec Corp | Manufacture of semiconductor device |
| JPS59207652A (en) * | 1983-05-11 | 1984-11-24 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
-
1987
- 1987-03-25 JP JP62072004A patent/JP2610866B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63237458A (en) | 1988-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2773729B2 (en) | Method for manufacturing semiconductor device | |
| JPH0424861B2 (en) | ||
| JP2008226963A (en) | Semiconductor device and manufacturing method therefor | |
| JP3175188B2 (en) | Method of forming alignment mark | |
| JPH04229616A (en) | Method for boring an opening on semicon- ductor layer structure | |
| JP2610866B2 (en) | Semiconductor resistance element | |
| JP3199847B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP2916306B2 (en) | Semiconductor device | |
| JP3180796B2 (en) | Method for manufacturing semiconductor device | |
| JPH05175428A (en) | Integrated circuit device | |
| JP3271090B2 (en) | Semiconductor device manufacturing method | |
| JP3164040B2 (en) | Manufacturing method of polysilicon resistance element | |
| JPS6013313B2 (en) | Manufacturing method of semiconductor device | |
| JPS639748B2 (en) | ||
| JPH0575026A (en) | Manufacture of resistor element | |
| JP3112036B2 (en) | Method for manufacturing semiconductor device | |
| JP2707538B2 (en) | Method for manufacturing semiconductor device | |
| JPS6038872B2 (en) | Manufacturing method of semiconductor device | |
| JPS6214953B2 (en) | ||
| JPS5912028B2 (en) | Manufacturing method for semiconductor devices | |
| JPS6079743A (en) | Semiconductor device | |
| JP2901262B2 (en) | Manufacturing method of polysilicon resistance element | |
| JP3038873B2 (en) | Method for manufacturing semiconductor device | |
| JP3099450B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2504239B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |