JP2609743B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2609743B2 JP2609743B2 JP2172407A JP17240790A JP2609743B2 JP 2609743 B2 JP2609743 B2 JP 2609743B2 JP 2172407 A JP2172407 A JP 2172407A JP 17240790 A JP17240790 A JP 17240790A JP 2609743 B2 JP2609743 B2 JP 2609743B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- semiconductor region
- power supply
- type semiconductor
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 209
- 239000000758 substrate Substances 0.000 claims description 69
- 238000009792 diffusion process Methods 0.000 claims description 54
- 239000012535 impurity Substances 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 238000009826 distribution Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置及びその製造方法に関し、特に
半導体基板の表面に設けられた複数種類の半導体領域の
製造及び該半導体領域を形成する方法に関するものであ
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for manufacturing a plurality of types of semiconductor regions provided on a surface of a semiconductor substrate and a method for forming the semiconductor regions. Things.
第２図は例えばアイ エス エス シー シー 89
ダイジェスト オブ テクニカル ペイパーズ（ISSCC
89 DIGEST OF TECHNICAL PAPERS）（P248,249）に示さ
れた半導体装置の断面構造を示す図であり、図におい
て、１はｎ型半導体基板で、その表面にはｐウェル15
と、これとは濃度が異なるｐウェル13とが隣接して形
成されており、さらに上記半導体基板１表面には、上記
ｐウェル13と隣接してｎウェル12が形成され、上記ｐ
ウェル15から若干離れて、上記ｐウェル13と同一濃
度のｐウェル14が形成されている。ここで、上記ｐウ
ェル15の表面には、ｎウェル16及びp+拡散領域15aが
形成されており、該p+拡散領域15aは電源電位ＶSSが供
給される電源ノード15bに接続されている。FIG. 2 shows, for example, ISSC 89
Digest of Technical Papers (ISSCC
89 is a diagram showing a cross-sectional structure of the semiconductor device shown in (DIGEST OF TECHNICAL PAPERS) (P248, 249), in which 1 is an n-type semiconductor substrate and the surface thereof is a p-well 15;
And a p-well 13 having a concentration different from that of the n-well 12 are formed adjacent to the p-well 13 on the surface of the semiconductor substrate 1.
A p-well 14 having the same concentration as the p-well 13 is formed slightly apart from the well 15. Here, an n-well 16 and ap + diffusion region 15a are formed on the surface of the p well 15, and the p + diffusion region 15a is connected to a power supply node 15b to which a power supply potential VSS is supplied.
また、上記ｎウェル12には、第１のｐ型MOSトランジ
スタ22のソース，ドレイン領域となる一対のp+拡散領域
12a、及び該ウェル12の電位を固定するためのn+拡散領
域12bが形成されており、上記p+拡散領域12aの一方及び
n+拡散領域12bは、電源電位Vextが供給される電源ノー
ド12cに接続されている。The n-well 12 has a pair of p + diffusion regions serving as source and drain regions of the first p-type MOS transistor 22.
12a, and an n + diffusion region 12b for fixing the potential of the well 12 is formed, and one of the p + diffusion regions 12a and
N + diffusion region 12b is connected to power supply node 12c to which power supply potential Vext is supplied.
上記ｐウェル13には、第１のｎ型MOSトランジスタ2
3のソース，ドレイン領域となる一対のn+拡散領域13a、
及び該ｐウェル13の電位を固定するためのp+拡散領域
13bが形成されており、n+拡散領域13aの一方及び該p+拡
散領域13bは、電源電位ＶSSが供給される電源ノード13c
に接続されている。The p well 13 has a first n-type MOS transistor 2
A pair of n + diffusion regions 13a serving as source / drain regions of 3;
And ap + diffusion region for fixing the potential of the p well 13
13b, one of the n + diffusion regions 13a and the p + diffusion region 13b are connected to a power supply node 13c to which the power supply potential VSS is supplied.
It is connected to the.
上記ｎウェル16には、第２のｐ型MOSトランジスタ26
のソース，ドレイン領域となる一対のp+拡散領域16a、
及び該ウェル16の電位を固定するためのn+拡散領域16b
が形成されており、上記p+拡散領域16aの一方及びn+拡
散領域16bは、電源電位Vintが供給される電源ノード16c
に接続され、上記p+拡散領域16aの他方は、上記ｐウェ
ル13の第１のｎ型MOSトランジスタ23のn+拡散領域13a
の他方に接続されている。A second p-type MOS transistor 26 is provided in the n-well 16.
A pair of p + diffusion regions 16a serving as source and drain regions of
And an n + diffusion region 16b for fixing the potential of the well 16
Are formed, and one of the p + diffusion regions 16a and the n + diffusion region 16b are connected to a power supply node 16c to which a power supply potential Vint is supplied.
The other of the p + diffusion region 16a is connected to the n + diffusion region 13a of the first n-type MOS transistor 23 in the p well 13.
Connected to the other.
上記ｐウェル14には、第２のｎ型MOSトランジスタ2
4のソース，ドレイン領域となる一対のn+拡散領域14a、
及び該ｐウェル14の電位を固定するためのp+拡散領域
14bが形成されており、該p+拡散領域14bは電源電位ＶBB
が供給される電源ノード14cに接続されている。The p well 14 has a second n-type MOS transistor 2
4, a pair of n + diffusion regions 14a serving as source and drain regions,
And ap + diffusion region for fixing the potential of the p well 14
14b are formed, and the p + diffusion region 14b is connected to the power supply potential VBB.
Is supplied to the power supply node 14c to which the power is supplied.
一般に、MOSFETが微細化されるにつれて、ウェルの不
純物濃度はますます上がる傾向にある。これは短チャン
ネル効果を抑えるためであり、その結果、スレッショル
ドVthのバックゲートバイアス依存性はますます強くな
っている。従ってトランジスタの高速化のためにはバッ
クゲートバイアスをかけない方が好ましい。Generally, as MOSFETs are miniaturized, the impurity concentration of wells tends to increase more and more. This is to suppress the short channel effect, and as a result, the dependence of the threshold Vth on the back gate bias is becoming stronger. Therefore, it is preferable not to apply a back gate bias in order to increase the speed of the transistor.
しかしながら例えばダイナミックRAMのメモリセル部
のようにソフトエラー対策や素子分離耐圧の向上のため
にバックゲートバイアスをかけた方がよい場合もある。
従って、各々のトランジスタに最適なバックゲートバイ
アスをかけられることが最も望ましい。However, there are cases where it is better to apply a back gate bias for measures against soft errors and improvement of element isolation withstand voltage, for example, as in a memory cell portion of a dynamic RAM.
Therefore, it is most desirable that an optimum back gate bias be applied to each transistor.
第２図に示す従来の半導体装置では、上述したように
ｎウェル12にはVext、ｎウェル16にはVint、ｐウェル
13にはＶSS、ｐウェル14にはＶBB、ｐウェル15には
ＶSSのバックゲートバイアスがかかっている。In the conventional semiconductor device shown in FIG. 2, Vext is applied to the n-well 12, Vint is applied to the n-well 16, and p-well is
A back gate bias of VSS is applied to 13, a p-well 14 is applied to VBB, and a p-well 15 is applied to VSS.
従来の半導体装置では、第２図に示されているよう
に、ｐウェル15内にｎウェル16を形成しているので、
ｎウェル16の領域においては、導電型としてはｎ型とな
っているものの、ｐウェル15の形成時に打ち込まれた
ｐ型不純物とｎウェル16の形成時に打ち込まれたｎ型不
純物が併存しており、このｎウェル16では不純物濃度が
高いためにキャリアのモビリティが低くなっている。In a conventional semiconductor device, an n-well 16 is formed in a p-well 15 as shown in FIG.
In the region of the n-well 16, although the conductivity type is n-type, the p-type impurity implanted when the p-well 15 is formed and the n-type impurity implanted when the n-well 16 is formed coexist. In the n-well 16, the carrier mobility is low due to the high impurity concentration.
また、ｎウェル16がｐウェル15を突き抜けて、ｎ型
半導体基板１と接触してしまわないようにｎウェル16を
形成する必要があるが、拡散層の深さを制御することは
簡単ではない。Further, it is necessary to form the n-well 16 so that the n-well 16 does not penetrate the p-well 15 and come into contact with the n-type semiconductor substrate 1, but it is not easy to control the depth of the diffusion layer. .
さらに、ｐウェル15とｐウェル13を同じ濃度にす
ると、ｎウェル16の形成時に打ち込む不純物の濃度が高
くなりすぎるので、ｐウェル15とｐウェル13の濃度
を異ならせてこれらのウェルを別々に形成しなければな
らず、またｎウェル12,16も上記ｐウェル15,13と同
様、濃度を変えて別々に形成する必要があり、マスク枚
数及び工程数が増えるという問題点があった。Further, if the p-well 15 and the p-well 13 are made to have the same concentration, the concentration of the impurity to be implanted at the time of forming the n-well 16 becomes too high. It is necessary to form the n-wells 12 and 16 similarly to the p-wells 15 and 13 with different densities, which increases the number of masks and the number of steps.
ところで、特開昭60−50953号公報，特開昭63−10237
1号公報，及び特開平２−105566号公報には、半導体装
置において、半導体基板上に形成した第１あるいは第２
導電型のエピタキシャル層の一部を、これが該エピタキ
シャル層の他の部分から電気的に絶縁されるよう、上記
エピタキシャル層底面部に形成した第２あるいは第１導
電型の埋込層及びエピタキシャル層中に形成した第２あ
るいは第１導電型領域により取り囲んだ構造が示されて
いる。Incidentally, JP-A-60-50953 and JP-A-63-10237
No. 1 and Japanese Unexamined Patent Publication No. 2-105566 disclose a first or second semiconductor device formed on a semiconductor substrate.
A portion of the second or first conductivity type buried layer and the epitaxial layer formed on the bottom surface of the epitaxial layer so that a part of the conductive type epitaxial layer is electrically insulated from other portions of the epitaxial layer. The structure surrounded by the second or first conductivity type region formed in FIG.
しかしながら、これらの公報記載の半導体装置の構造
では、第１あるいは第２導電型のエピタキシャル層中
に、第２あるいは第１導電型の領域を不純物の注入によ
り選択的に形成して、上記エピタキシャル層の一部を他
の領域から電気的に絶縁しているため、導電型がエピタ
キシャル層と逆の領域では、ｎ型不純物とｐ型不純物と
が併存し、不純物濃度が高いものとなっている。このた
めこれらの領域は素子領域として用いた場合には、キャ
リアのモビリティが低い素子領域となってしまう。However, in the structure of the semiconductor device described in these publications, the second or first conductivity type region is selectively formed in the first or second conductivity type epitaxial layer by implanting an impurity to form the epitaxial layer. Are electrically insulated from the other regions, and in the region where the conductivity type is opposite to that of the epitaxial layer, the n-type impurity and the p-type impurity coexist and the impurity concentration is high. Therefore, when these regions are used as element regions, they become element regions having low carrier mobility.
この発明は上記のような問題を解決するためになされ
たもので、半導体基板に、該基板や他の半導体領域（ウ
ェル）と電気的に絶縁されるべき、これらと同一導電型
の半導体領域（ウェル）を、その領域内でのキャリアの
モビリティの低下を抑えつつ形成することが可能である
とともに、上記半導体基板等と電気的に絶縁されるべき
半導体領域の基板への突き抜けを抑えることができ、し
かも半導体領域（ウェル）の作り分けの回数を少なくす
ることができる半導体装置を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a semiconductor substrate having the same conductivity type as a semiconductor substrate and another semiconductor region (well) to be electrically insulated from the substrate and other semiconductor regions (wells) is provided. Well) can be formed while suppressing a decrease in mobility of carriers in the region, and penetration of a semiconductor region to be electrically insulated from the semiconductor substrate or the like into the substrate can be suppressed. In addition, it is an object of the present invention to obtain a semiconductor device in which the number of semiconductor regions (wells) can be reduced.
また、この発明は、半導体基板に、該基板や他の半導
体領域（ウェル）と電気的に絶縁されるべき、これらと
同一導電型の半導体領域（ウェル）を、マスク枚数や工
程数の増大を抑えつつ簡単に形成することができ、しか
もこの際、上記基板等と電気的に絶縁された半導体領域
でのキャリアのモビリティの増大を小さく抑えることが
できる半導体装置の製造方法を得ることを目的とする。Further, the present invention provides a semiconductor substrate having a semiconductor region (well) of the same conductivity type to be electrically insulated from the substrate and other semiconductor regions (wells) by increasing the number of masks and the number of steps. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can be easily formed while suppressing the increase in mobility of carriers in a semiconductor region electrically insulated from the substrate or the like. I do.
この発明に係る半導体装置（請求項１）は、第１導電
型の半導体基板の一主面に形成され、第１の電源電位が
供給される第１の電源ノードに接続される第１の第１導
電型半導体領域と、上記半導体基板の中に形成される第
２導電型の高エネルギーイオン注入層と、上記半導体基
板の一主面に、底面が上記高エネルギーイオン注入層の
上面とPN接合をなして形成され、上記第１の電源電位と
は異なる第２の電源電位が供給される第２の電源ノード
に接続される第２の第１導電型半導体領域と、上記半導
体基板の一主面に、底面が上記高エネルギーイオン注入
層の上面と接するとともに側面が上記第２の第１導電型
半導体領域の側面とPN接合をなして形成され、上記高エ
ネルギーイオン注入層とで上記第２の第１導電型半導体
領域を上記半導体基板及び上記第１の第１導電型半導体
領域と電気的に絶縁するための第２導電型半導体領域
と、上記第１の第１導電型半導体領域の表面に形成さ
れ、第１の第２導電型MOSトランジスタのソース及びド
レイン領域となる一対の第２導電型の第１拡散領域と、
上記第２の第１導電型半導体領域の表面に形成され、第
２の第２導電型MOSトランジスタのソース及びドレイン
領域となる一対の第２導電型の第２拡散領域と、上記第
２導電型半導体領域の表面に形成され、第１導電型MOS
トランジスタのソース及びドレイン領域となる一対の第
１導電型の拡散領域とを備えたものである。A semiconductor device according to the present invention (claim 1) is formed on one main surface of a semiconductor substrate of a first conductivity type and connected to a first power supply node supplied with a first power supply potential. A first conductivity type semiconductor region, a second conductivity type high energy ion implantation layer formed in the semiconductor substrate, and a PN junction with one main surface of the semiconductor substrate, a bottom surface of which is a top surface of the high energy ion implantation layer; And a second first conductivity type semiconductor region connected to a second power supply node to which a second power supply potential different from the first power supply potential is supplied. A bottom surface in contact with the top surface of the high-energy ion-implanted layer, and a side surface formed with the side surface of the second first-conductivity-type semiconductor region in a PN junction; The first conductivity type semiconductor region of the semiconductor substrate And a second conductivity type semiconductor region for electrically insulating the first first conductivity type semiconductor region, and a first second conductivity type formed on the surface of the first first conductivity type semiconductor region. A pair of first diffusion regions of the second conductivity type serving as source and drain regions of the MOS transistor;
A pair of second diffusion regions of the second conductivity type formed on the surface of the second first conductivity type semiconductor region and serving as source and drain regions of the second second conductivity type MOS transistor; The first conductivity type MOS formed on the surface of the semiconductor region
And a pair of first conductivity type diffusion regions serving as source and drain regions of the transistor.
また、この発明に係る半導体装置（請求項２）は、上
記半導体装置（請求項１）において、上記第２導電型半
導体領域は、第１及び第２の電源電位とは異なる第３の
電源電位が供給される第３の電源ノードに接続されてい
るものである。Also, in the semiconductor device according to the present invention (claim 2), in the semiconductor device (claim 1), the second conductivity type semiconductor region is a third power supply potential different from the first and second power supply potentials. Are connected to a third power supply node to which the power is supplied.
また、この発明に係る半導体装置（請求項３）は、第
１及び第２の第１導電型半導体領域の濃度分布は同じで
あるものである。In the semiconductor device according to the present invention (claim 3), the first and second first conductivity type semiconductor regions have the same concentration distribution.
また、この発明に係る半導体装置の製造方法（請求項
４）は、半導体装置の製造方法において、第１導電型の
半導体基板の一主面に形成され、第１の電源電位が供給
される第１の電源ノードに接続される第１の第１導電型
半導体領域と、上記半導体基板の中に形成される第２導
電型の高エネルギーイオン注入層と、上記半導体基板の
一主面に、底面が上記高エネルギーイオン注入層の上面
とPN接合をなして形成され、上記第１の電源電位とは異
なる第２の電源電位が供給される第２の電源ノードに接
続される第２の第１導電型半導体領域と、上記半導体基
板の一主面に、底面が上記高エネルギーイオン注入層の
上面と接するとともに側面が上記第２の第１導電型半導
体領域の側面とPN接合をなして形成され、上記高エネル
ギーイオン注入層とで上記第２の第１導電型半導体領域
を上記半導体基板及び上記第１の第１導電型半導体領域
と電気的に絶縁するための第２導電型半導体領域と、上
記第１の第１導電型半導体領域の表面に形成され、第１
の第２導電型MOSトランジスタのソース及びドレイン領
域となる一対の第２導電型の第１拡散領域と、上記第２
の第１導電型半導体領域の表面に形成され、第２の第２
導電型MOSトランジスタのソース及びドレイン領域とな
る一対の第２導電型の第２拡散領域とを備えた半導体装
置を製造する方法において、上記第１及び第２の第１導
電型半導体領域を形成する半導体領域への第１導電型不
純物の拡散を同時に行うものである。Further, a method of manufacturing a semiconductor device according to the present invention (claim 4) is a method of manufacturing a semiconductor device, comprising: forming a semiconductor substrate of a first conductivity type on one main surface and supplying a first power supply potential. A first first conductivity type semiconductor region connected to the first power supply node, a second conductivity type high energy ion implantation layer formed in the semiconductor substrate, and a bottom surface on one main surface of the semiconductor substrate. Is formed so as to form a PN junction with the upper surface of the high-energy ion implantation layer, and is connected to a second power supply node supplied with a second power supply potential different from the first power supply potential. A conductive type semiconductor region, and a main surface formed on one main surface of the semiconductor substrate such that a bottom surface is in contact with an upper surface of the high energy ion implanted layer and a side surface forms a PN junction with a side surface of the second first conductive type semiconductor region. With the above high energy ion implanted layer A second conductivity type semiconductor region for electrically insulating the second first conductivity type semiconductor region from the semiconductor substrate and the first first conductivity type semiconductor region; and the first first conductivity type semiconductor. Formed on the surface of the region, the first
A pair of second diffusion type first diffusion regions serving as source and drain regions of the second conductivity type MOS transistor;
Formed on the surface of the first conductive type semiconductor region, and the second second conductive type semiconductor region.
In a method for manufacturing a semiconductor device having a pair of second conductive type second diffusion regions serving as source and drain regions of a conductive type MOS transistor, the first and second first conductive type semiconductor regions are formed. The first conductivity type impurity is simultaneously diffused into the semiconductor region.
また、この発明に係る半導体装置の製造方法（請求項
５）は、請求項４に記載の半導体装置の製造方法におい
て、上記半導体装置は、半導体基板の一主面に形成さ
れ、第１及び第２の電源電位とは異なる第３の電源電位
が供給される第３の電源ノードに接続される第２の第２
導電型半導体領域と、この第２の第２導電型半導体領域
の表面に形成され、第１導電型MOSトランジスタのソー
ス及びドレイン領域となる一対の第１導電型の拡散領域
とを有するものであり、上記第２導電型半導体領域及び
第２の第２導電型半導体領域を形成する半導体領域への
第２導電型不純物の拡散を同時に行うものである。According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the semiconductor device is formed on one main surface of a semiconductor substrate. 2nd second power supply potential connected to a third power supply node supplied with a third power supply potential different from the second power supply potential.
A conductive type semiconductor region; and a pair of first conductive type diffusion regions formed on the surface of the second second conductive type semiconductor region and serving as source and drain regions of the first conductive type MOS transistor. And simultaneously diffusing the second conductivity type impurity into the second conductivity type semiconductor region and the semiconductor region forming the second second conductivity type semiconductor region.
この発明に係る半導体装置においては、第１導電型半
導体基板の表面に位置する第１導電型半導体領域を、こ
れが上記半導体基板や他の第１導電型半導体領域から電
気的に絶縁されるよう、基板中に形成した高エネルギー
イオン注入層及び基板表面の第２導電型半導体領域によ
り囲んだから、上記基板等から電気的に絶縁されるべき
第１導電型半導体領域と他の第１導電型半導体領域に
は、電位が異なるバックゲートバイアスを独立して印加
することができる。また、上記電気的に絶縁されるべき
第１導電型半導体領域は、第２導電型の半導体領域中で
はなく、半導体基板の領域中に位置することとなるた
め、この第１導電型半導体領域中での不純物を第１導電
型のもののみにしてこの領域での不純物濃度を低減する
ことができ、該領域でのキャリアのモビリティの低下を
抑制することができる。In the semiconductor device according to the present invention, the first conductivity type semiconductor region located on the surface of the first conductivity type semiconductor substrate is electrically insulated from the semiconductor substrate and other first conductivity type semiconductor regions. The first conductive semiconductor region and the other first conductive semiconductor regions that are to be electrically insulated from the substrate and the like because they are surrounded by the high energy ion implanted layer formed in the substrate and the second conductive semiconductor region on the substrate surface. , A back gate bias having a different potential can be independently applied. Further, the first conductivity type semiconductor region to be electrically insulated is not located in the semiconductor region of the second conductivity type but in the region of the semiconductor substrate. By using only impurities of the first conductivity type, the impurity concentration in this region can be reduced, and a decrease in carrier mobility in this region can be suppressed.
また、上記第１導電型半導体領域と、これを周辺の第
１導電型領域から電気的に絶縁するための第２導電型半
導体領域とを平面的に重ねて形成する必要がなく、また
高エネルギーイオン注入層はその打ち込むエネルギーに
よって形成される深さが決まることから、製造時の制御
が容易になる。In addition, it is not necessary to form the first conductivity type semiconductor region and the second conductivity type semiconductor region for electrically insulating the first conductivity type semiconductor region from the surrounding first conductivity type region in a planar manner. The depth at which the ion implantation layer is formed is determined by the energy to be implanted, which facilitates control during manufacturing.
また、この発明においては、上記第１導電型半導体領
域を周辺の第１導電型領域から電気的に絶縁するための
第２導電型半導体領域の表面に、第１導電型MOSトラン
ジスタのソース及びドレイン領域となる一対の第１導電
型の拡散領域を形成したので、基板表面のトランジスタ
素子による利用効率を高めることができる。Further, according to the present invention, the source and drain of the first conductivity type MOS transistor are provided on the surface of the second conductivity type semiconductor region for electrically insulating the first conductivity type semiconductor region from the surrounding first conductivity type region. Since the pair of first conductivity type diffusion regions serving as regions are formed, the utilization efficiency of the transistor element on the substrate surface can be increased.
また、この発明においては、上記第２導電型半導体領
域には、第１及び第２の電源電位とは異なる第３の電源
電位を印加するようにしたので、該領域内に配置された
トランジスタのバックゲートバイアスを最適なものとで
きる。Also, in the present invention, the third power supply potential different from the first and second power supply potentials is applied to the second conductivity type semiconductor region. The back gate bias can be optimized.
さらに、この発明においては、上記第１及び第２の第
１導電型半導体領域の濃度分布を同一にしたので、上記
基板等から絶縁されるべき第１導電型半導体領域と、こ
れと同一導電型の他の半導体領域とを、濃度を変えて別
々の工程で形成する必要がなくなり、マスク数や工程数
の増加を抑えることが可能である。Furthermore, in the present invention, the first and second first conductivity type semiconductor regions have the same concentration distribution, so that the first conductivity type semiconductor region to be insulated from the substrate and the like, and the same conductivity type as the first conductivity type semiconductor region. It is not necessary to form the semiconductor region with another semiconductor region in different steps by changing the concentration, and it is possible to suppress an increase in the number of masks and steps.
この発明に係る半導体装置の製造方法においては、第
２導電型MOSトランジスタが配置される第１の第１導電
型半導体領域と、第２導電型MOSトランジスタが配置さ
れ、周辺の第１導電型領域から電気的に絶縁されるべき
第２の第１導電型半導体領域とを同じ工程で形成するの
で、電位が異なるバックゲートバイアスを独立して印加
可能な複数の半導体領域を、マスク数や工程数の増加を
招くことなく形成することができる。In the method of manufacturing a semiconductor device according to the present invention, a first first-conductivity-type semiconductor region in which a second-conductivity-type MOS transistor is disposed, and a first-conductivity-type region in which a second-conductivity-type MOS transistor is disposed. Are formed in the same process as the second first conductivity type semiconductor region which is to be electrically insulated from the semiconductor device. Can be formed without increasing the number of layers.
この発明においては、上記半導体装置の製造方法にお
いて、上記第２の第１導電型半導体領域を周辺の第１導
電型領域から電気的に分離するための第２導電型半導体
領域と、上記第1,第２の第１導電型半導体領域に印加さ
れる第1,第２の電源電位と異なる第３の電源電位が印加
される第２の第２導電型半導体領域とを同じ工程で形成
するので、電位が異なるバックゲートバイアスを独立し
て印加可能な半導体領域の数を、マスク数や工程数の増
加を抑えつつ増大させることができる。According to the present invention, in the method for manufacturing a semiconductor device, the second conductivity type semiconductor region for electrically separating the second first conductivity type semiconductor region from a peripheral first conductivity type region; And the second second conductivity type semiconductor region to which a third power supply potential different from the first and second power supply potentials applied to the second first conductivity type semiconductor region is formed in the same step. In addition, the number of semiconductor regions to which back gate biases having different potentials can be independently applied can be increased while suppressing an increase in the number of masks and the number of steps.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による半導体装置の断面構
造を示す図であり、図において、２はｎ型半導体基板
（第１導電型の半導体基板）１の表面に形成された第１
のｎウェル（第１の第１導電型半導体領域）、７は上記
半導体基板１の中に高エネルギーイオン注入により形成
されたp+型イオン注入層、６は上記ｎ型半導体基板１の
表面に、底面が上記高エネルギーイオン注入層７の上面
とPN接合をなして形成された第２のｎウェル（第２の第
１導電型半導体領域）で、上記第１のｎウェル２と同一
の濃度分布を持っている。FIG. 1 is a view showing a cross-sectional structure of a semiconductor device according to one embodiment of the present invention. In the drawing, reference numeral 2 denotes a first semiconductor substrate (first conductivity type semiconductor substrate) 1 formed on a surface
N-well (first first conductivity type semiconductor region), 7 is a p + -type ion implantation layer formed by high energy ion implantation in the semiconductor substrate 1, and 6 is a surface of the n-type semiconductor substrate 1. A second n-well (second first conductivity type semiconductor region) having a bottom surface formed as a PN junction with the upper surface of the high-energy ion implantation layer 7 and having the same concentration as that of the first n-well 2. Has a distribution.
また３及び５は、それぞれ上記半導体基板１の表面
に、その底面が上記イオン注入層７の上面と接するとと
もに側面が上記ｎウェル６の側面とPN接合をなして形成
されたｐウェル（第２導電型半導体領域）で、これらの
ｐウェル３及び５は、上記ｎウェル６がｎ型半導体基板
１及びｎウェル２から電気的に絶縁されるよう、上記イ
オン注入層７とともに上記ｎウェル６を囲んでいる。Reference numerals 3 and 5 denote p-wells (second wells) formed on the surface of the semiconductor substrate 1 with the bottom surface in contact with the upper surface of the ion-implanted layer 7 and the side surfaces formed with the side surfaces of the n-well 6 by PN junction. In the conductive type semiconductor region, the p wells 3 and 5 are connected to the n well 6 together with the ion implantation layer 7 so that the n well 6 is electrically insulated from the n type semiconductor substrate 1 and the n well 2. Surrounding.
さらに、４は上記半導体基板１の表面の、上記ｐウェ
ル５から所定距離離れた位置に形成された第２のｐウェ
ル（第２の第２導電型半導体領域）である。Reference numeral 4 denotes a second p-well (second second conductivity type semiconductor region) formed at a position on the surface of the semiconductor substrate 1 at a predetermined distance from the p-well 5.
ここで、上記ｐウェル５の表面にはp+拡散領域5aが形
成されており、該p+拡散領域5aは電源電位ＶSSが供給さ
れる電源ノード5cに接続されている。Here, a p + diffusion region 5a is formed on the surface of the p well 5, and the p + diffusion region 5a is connected to a power supply node 5c to which a power supply potential VSS is supplied.
また、上記ｎウェル２には、第１のｐ型MOSトランジ
スタ20のソース，ドレイン領域となる一対のp+拡散領域
2a、及び該ｎウェル２の電位を固定するためのn+拡散領
域2bが形成されており、上記p+拡散領域2aの一方及びn+
拡散領域2bは、電源電位Vextが供給される電源ノード2c
に接続されている。The n-well 2 has a pair of p + diffusion regions serving as source and drain regions of the first p-type MOS transistor 20.
2a and an n + diffusion region 2b for fixing the potential of the n well 2 are formed, and one of the p + diffusion regions 2a and n +
Diffusion region 2b is connected to power supply node 2c to which power supply potential Vext is supplied.
It is connected to the.
上記ｐウェル３には、第１のｎ型MOSトランジスタ30
のソース，ドレイン領域となる一対のn+拡散領域3a、及
び該ｐウェル３の電位を固定するためのp+拡散領域3bが
形成されており、n+拡散領域3aの一方及び該p+拡散領域
3bは、電源電位ＶSSが供給される電源ノード3cに接続さ
れている。In the p well 3, a first n-type MOS transistor 30 is provided.
A pair of n + diffusion regions 3a serving as source and drain regions and ap + diffusion region 3b for fixing the potential of the p well 3 are formed. One of the n + diffusion regions 3a and the p + region
3b is connected to a power supply node 3c to which the power supply potential VSS is supplied.
上記ｎウェル６には、第２のｐ型MOSトランジスタ60
のソース，ドレイン領域となる一対のp+拡散領域6a、及
び該ｎウェル６の電位を固定するためのn+拡散領域6bが
形成されており、上記p+拡散領域6aの一方及びn+拡散領
域6bは、電源電位Vintが供給される電源ノード6cに接続
され、上記p+拡散領域6aの他方は、上記ｐウェル３の第
１のｎ型MOSトランジスタ30のn+拡散領域3aの他方に接
続されている。In the n-well 6, a second p-type MOS transistor 60 is provided.
A pair of p + diffusion regions 6a to be the source and drain regions of the N + and an n + diffusion region 6b for fixing the potential of the n well 6 are formed. One of the p + diffusion regions 6a and the n + The region 6b is connected to the power supply node 6c to which the power supply potential Vint is supplied, and the other of the p + diffusion region 6a is connected to the other of the n + diffusion region 3a of the first n-type MOS transistor 30 in the p well 3. It is connected.
上記ｐウェル４には、第２のｎ型MOSトランジスタ40
のソース，ドレイン領域となる一対のn+拡散領域4a、及
び該ｐウェル４の電位を固定するためのn+拡散領域4bが
形成されており、該p+拡散領域4bは電源電位ＶBBが供給
される電源ノード4cに接続されている。In the p well 4, a second n-type MOS transistor 40 is provided.
A pair of n + diffusion regions 4a serving as source / drain regions and an n + diffusion region 4b for fixing the potential of the p well 4 are formed, and the p + diffusion region 4b is supplied with a power supply potential VBB. Connected to the power supply node 4c.
このような構造の半導体装置の製造方法では、上記ｎ
ウェル２とｎウェル６は同じ工程で形成し、上記ｐウェ
ル3,5とｐウェル４とは同一の工程で形成する。In the method of manufacturing a semiconductor device having such a structure, the above n
The well 2 and the n-well 6 are formed in the same step, and the p-wells 3, 5 and the p-well 4 are formed in the same step.
次に作用効果について説明する。 Next, the operation and effect will be described.
第１図に示すようにｐウェル中にｎウェルが作られる
ことがないので、ｐウェル3,4,5は特に濃度を変える必
要がなく、同じ工程で作ることができる。また高エネル
ギーイオン注入p+層７の形成においては、ｎ型半導体基
板１の該イオン注入層７部分以外には不純物は拡散され
ないので、ｎウェル６はｐ型不純物の存在しないｎ型半
導体基板部分に作るのとほぼ同じこととなる。従ってｎ
ウェル２とｎウェル６を形成するに際しても、不純物打
ち込み量を特にかえる必要もなく、該両ウェル2,6を同
じ工程で形成することができる。As shown in FIG. 1, since no n-well is formed in the p-well, the p-wells 3, 4, and 5 need not be particularly changed in concentration, and can be formed in the same process. In forming the high-energy ion-implanted p + layer 7, since no impurity is diffused except for the ion-implanted layer 7 of the n-type semiconductor substrate 1, the n-well 6 has no p-type impurity. It is almost the same as making it. Therefore n
When forming the well 2 and the n-well 6, it is not necessary to change the impurity implantation amount, and the wells 2 and 6 can be formed in the same step.
しかもｎウェル６はｐウェル3,5及び高エネルギー注
入p+層７で囲まれているので、電気的には該ｎウェル６
はｎウェル２やｎ型半導体基板１からは絶縁されること
となる。従って、ｎウェル２とｎウェル６には独立にバ
ックゲートバイアスを与えることができる。またｐウェ
ル４はｎ型半導体基板１の領域により他のｐウェル3,5
と分離されているので、ｐウェル3,5とｐウェル４にも
独立にバックゲートバイアスを与えることができる。ま
た、高エネルギー注入p+層７は、その打ち込むエネルギ
ーによって形成される深さが決まるので、深さの制御が
し易く、ｎウェル６がｎ型半導体基板１に突き抜けてし
まう可能性が低くなる。Moreover, since the n-well 6 is surrounded by the p-wells 3, 5 and the high energy implanted p + layer 7, the n-well 6 is electrically
Is insulated from the n-well 2 and the n-type semiconductor substrate 1. Therefore, a back gate bias can be independently applied to the n-well 2 and the n-well 6. Further, the p-well 4 has other p-wells 3 and 5 depending on the area of the n-type
Therefore, a back gate bias can be independently applied to the p wells 3 and 5 and the p well 4. Further, since the depth formed by the energy to be implanted in the high-energy implantation p + layer 7 is determined, the depth can be easily controlled, and the possibility that the n-well 6 penetrates into the n-type semiconductor substrate 1 is reduced. .
また、前述のようにｎウェル６はｐ型不純物の存在し
ない基板領域に形成されるので、その形成時にはｎウェ
ル形成に必要な量の不純物だけを打ち込めばよく、必要
以上に不純物の濃度を上げなくてもよいので、モビリテ
ィーの低下を抑えることができる。Further, as described above, since the n-well 6 is formed in the substrate region where no p-type impurity is present, only the amount of impurity necessary for forming the n-well needs to be implanted at the time of formation, and the impurity concentration is increased more than necessary. Since there is no need to do so, it is possible to suppress a decrease in mobility.
このように本実施例では、ｎ型半導体基板１と電気的
に絶縁する必要のあるｎウェル６を、高エネルギー注入
p+層７とｐウェル3,5で囲むようにしたので、上記ｎウ
ェル６と他のｎウェル２とに独立にバックゲートバイア
スを与えることができる。また、ｐウェル3,5とｐウェ
ル４とはｎ型半導体基板の領域により分離されているの
で、これらのｐウェル3,5とｐウェル４にも独立にバッ
クゲートバイアスを与えることができる。As described above, in the present embodiment, the n-well 6 which needs to be electrically insulated from the n-type semiconductor substrate 1 is implanted with high energy.
Since the p + layer 7 and the p wells 3 and 5 are surrounded, a back gate bias can be independently applied to the n well 6 and the other n wells 2. Since the p-wells 3, 5 and the p-well 4 are separated from each other by the region of the n-type semiconductor substrate, a back gate bias can be independently applied to the p-wells 3, 5 and the p-well 4.
また、上記複数のウェルは半導体基板の表面領域にオ
ーバーラップすることなく配置されているため、同一導
電型のウェルはすべて同一濃度にして１回の工程で作る
ことができる。さらにｎ型基板領域や他のｎウェルと絶
縁されるべきｎウェル部分の形成時には、ｎウェル形成
に必要な量の不純物を打ち込めばよく、必要以上に不純
物の濃度を上げなくてよいので上記ｎウェル部分でのモ
ビリティの低下を抑えることができる。Further, since the plurality of wells are arranged without overlapping the surface region of the semiconductor substrate, all wells of the same conductivity type can be formed in one process with the same concentration. Further, at the time of forming the n-type substrate region and the n-well portion to be insulated from other n-wells, an impurity necessary for forming the n-well may be implanted, and it is not necessary to increase the impurity concentration more than necessary. A decrease in mobility at the well portion can be suppressed.
なお、上記実施例では、半導体装置の構造として、ｎ
型半導体基板上にウェルを形成したものを例に挙げた
が、これはｐ型半導体基板上にウェルを形成したもので
もよい。In the above embodiment, the structure of the semiconductor device is n
Although an example in which a well is formed on a p-type semiconductor substrate has been described as an example, this may be one in which a well is formed on a p-type semiconductor substrate.
以上のようにこの発明に係る半導体装置によれば、第
１導電型半導体基板の表面に位置する第１導電型半導体
領域を、これが上記半導体基板や他の第１導電型半導体
領域から電気的に絶縁されるよう、基板中に形成した高
エネルギーイオン注入層及び基板表面の第２導電型半導
体領域により囲んだので、上記基板等から電気的に絶縁
されるべき第１導電型半導体領域と他の第１導電型半導
体領域には、電位が異なるバックゲートバイアスを独立
して印加することができ、さらに上記電気的に絶縁され
るべき第１導電型半導体領域は、第２導電型の半導体領
域中ではなく、半導体基板の領域中に位置することとな
るため、この第１導電型半導体領域中での不純物を第１
導電型のもののみにしてこの領域での不純物濃度を低減
することができ、該領域でのキャリアのモビリティの低
下を抑制することができるという効果がある。As described above, according to the semiconductor device of the present invention, the first conductivity type semiconductor region located on the surface of the first conductivity type semiconductor substrate is electrically disconnected from the semiconductor substrate and other first conductivity type semiconductor regions. Since it is surrounded by the high energy ion implanted layer formed in the substrate and the second conductivity type semiconductor region on the substrate surface so as to be insulated, the first conductivity type semiconductor region to be electrically insulated from the substrate and the like and other A back gate bias having a different potential can be independently applied to the first conductivity type semiconductor region, and the first conductivity type semiconductor region to be electrically insulated is a second conductivity type semiconductor region. Instead, the impurity is located in the region of the semiconductor substrate.
By using only the conductive type, the impurity concentration in this region can be reduced, and there is an effect that a decrease in carrier mobility in this region can be suppressed.
また、上記第１導電型半導体領域と、これを周辺の第
１導電型領域から電気的に絶縁するための第２導電型半
導体領域とを平面的に重ねて形成する必要がなく、また
高エネルギーイオン注入層はその打ち込むエネルギーに
よって形成される深さが決まることから、製造時の制御
が容易になるという効果もある。In addition, it is not necessary to form the first conductivity type semiconductor region and the second conductivity type semiconductor region for electrically insulating the first conductivity type semiconductor region from the surrounding first conductivity type region in a planar manner. Since the ion implantation layer determines the depth to be formed by the energy to be implanted, there is also an effect that control at the time of manufacturing becomes easy.
また、この発明によれば、上記第１導電型半導体領域
を周辺の第１導電型領域から電気的に絶縁するための第
２導電型半導体領域の表面に、第１導電型MOSトランジ
スタのソース及びドレイン領域となる一対の第１導電型
の拡散領域を形成したので、基板表面のトランジスタ素
子による利用効率を高めることができる効果がある。According to the invention, the source of the first conductivity type MOS transistor and the source of the first conductivity type MOS transistor are provided on the surface of the second conductivity type semiconductor region for electrically insulating the first conductivity type semiconductor region from the surrounding first conductivity type region. Since a pair of first conductivity type diffusion regions serving as drain regions are formed, there is an effect that utilization efficiency of the transistor element on the substrate surface can be improved.
また、この発明によれば、上記第２導電型半導体領域
には、第１及び第２の電源電位とは異なる第３の電源電
位を印加するようにしたので、該領域内に配置されたト
ランジスタのバックゲートバイアスを最適なものとでき
る効果がある。Further, according to the present invention, since the third power supply potential different from the first and second power supply potentials is applied to the second conductivity type semiconductor region, the transistor disposed in the region is provided. This has the effect of making the back gate bias optimal.
さらに、この発明によれば、上記第１及び第２の第１
導電型半導体領域の濃度分布を同一にしたので、上記基
板等から絶縁されるべき第１導電型半導体領域と、これ
と同一導電型の他の半導体領域とを、濃度を変えて別々
の工程で形成する必要がなくなり、マスク数や工程数の
増加を抑えることができる効果がある。Further, according to the present invention, the first and second first
Since the concentration distribution of the conductive type semiconductor region is made the same, the first conductive type semiconductor region to be insulated from the substrate or the like and another semiconductor region of the same conductive type as this are changed in different steps by changing the concentration. This eliminates the necessity of formation, and has the effect of suppressing an increase in the number of masks and steps.
この発明に係る半導体装置の製造方法によれば、第２
導電型MOSトランジスタが配置される第１の第１導電型
半導体領域と、第２導電型MOSトランジスタが配置さ
れ、周辺の第１導電型領域から電気的に絶縁されるべき
第２の第１導電型半導体領域とを同じ工程で形成するの
で、電位が異なるバックゲートバイアスを独立して印加
可能な複数の半導体領域を、マスク数や工程数の増加を
招くことなく形成することができる効果がある。According to the semiconductor device manufacturing method of the present invention, the second
A first first conductivity type semiconductor region in which a conductivity type MOS transistor is arranged, and a second first conductivity type in which a second conductivity type MOS transistor is arranged and which is to be electrically insulated from surrounding first conductivity type regions. Since the mold semiconductor region is formed in the same step, a plurality of semiconductor regions to which a back gate bias having a different potential can be independently applied can be formed without increasing the number of masks and steps. .
この発明によれば、上記第２の第１導電型半導体領域
を周辺の第１導電型領域から電気的に分離するための第
２導電型半導体領域と、上記第1,第２の第１導電型半導
体領域に印加される第1,第２の電源電位と異なる第３の
電源電位が印加される第２の第２導電型半導体領域とを
同じ工程で形成するので、電位が異なるバックゲートバ
イアスを独立して印加可能な半導体領域の数を、マスク
数や工程数の増加を抑えつつ増大させることができる効
果がある。According to this invention, the second conductivity type semiconductor region for electrically separating the second first conductivity type semiconductor region from the surrounding first conductivity type region, and the first and second first conductivity type semiconductor regions. Back-gate biases having different potentials since the second and second conductive type semiconductor regions to which a third power supply potential different from the first and second power supply potentials applied to the type semiconductor region are formed in the same step. Has the effect of increasing the number of semiconductor regions to which can be independently applied while suppressing an increase in the number of masks and the number of steps.
第１図はこの発明の一実施例による半導体装置の断面
図、第２図は従来の半導体装置の断面図である。 １……ｎ型半導体基板（第１導電型半導体基板）、２…
…第１のｎウェル（第１の第１導電型半導体領域）、3,
5……ｐウェル（第２導電型半導体領域）、４……ｐウ
ェル（第２の第２導電型半導体領域）、６……第２のｎ
ウェル（第２の第１導電型半導体領域）、７……高エネ
ルギーイオン注入p+層（第２導電型の高エネルギーイオ
ン注入層）。 なお、図中同一符号は同一または相当部分を示す。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 1 .... n-type semiconductor substrate (first conductivity type semiconductor substrate), 2 ....
... first n-well (first first conductivity type semiconductor region), 3,
5... P-well (second conductivity type semiconductor region), 4... P-well (second second conductivity type semiconductor region), 6.
Wells (second first conductivity type semiconductor region), 7... High energy ion implanted p + layer (second conductivity type high energy ion implanted layer). In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (5)
れ、第１の電源電位が供給される第１の電源ノードに接
続される第１の第１導電型半導体領域と、 上記半導体基板の中に形成される第２導電型の高エネル
ギーイオン注入層と、 上記半導体基板の一主面に、底面が上記高エネルギーイ
オン注入層の上面とPN接合をなして形成され、上記第１
の電源電位とは異なる第２の電源電位が供給される第２
の電源ノードに接続される第２の第１導電型半導体領域
と、 上記半導体基板の一主面に、底面が上記高エネルギーイ
オン注入層の上面と接するとともに側面が上記第２の第
１導電型半導体領域の側面とPN接合をなして形成され、
上記高エネルギーイオン注入層とで上記第２の第１導電
型半導体領域を上記半導体基板及び上記第１の第１導電
型半導体領域と電気的に絶縁するための第２導電型半導
体領域と、 上記第１の第１導電型半導体領域の表面に形成され、第
１の第２導電型MOSトランジスタのソース及びドレイン
領域となる一対の第２導電型の第１拡散領域と、 上記第２の第１導電型半導体領域の表面に形成され、第
２の第２導電型MOSトランジスタのソース及びドレイン
領域となる一対の第２導電型の第２拡散領域と、 上記第２導電型半導体領域の表面に形成され、第１導電
型MOSトランジスタのソース及びドレイン領域となる一
対の第１導電型の拡散領域とを備えたことを特徴とする
半導体装置。A first conductive type semiconductor region formed on one main surface of a first conductive type semiconductor substrate and connected to a first power supply node supplied with a first power supply potential; A second conductivity type high energy ion implantation layer formed in the semiconductor substrate; and a bottom surface formed on one principal surface of the semiconductor substrate so as to form a PN junction with an upper surface of the high energy ion implantation layer. 1
A second power supply potential different from the power supply potential of
A second first conductivity type semiconductor region connected to a power supply node of the first type; a first surface of the semiconductor substrate having a bottom surface in contact with an upper surface of the high energy ion implanted layer and a side surface having the second first conductivity type. Formed with a PN junction with the side surface of the semiconductor region,
A second conductivity type semiconductor region for electrically insulating the second first conductivity type semiconductor region from the semiconductor substrate and the first first conductivity type semiconductor region with the high energy ion implanted layer; A pair of second diffusion type first diffusion regions formed on the surface of the first first conductivity type semiconductor region and serving as source and drain regions of the first second conductivity type MOS transistor; A pair of second conductive type second diffusion regions formed on the surface of the conductive type semiconductor region and serving as source and drain regions of the second second conductive type MOS transistor; and formed on the surface of the second conductive type semiconductor region. And a pair of first conductivity type diffusion regions serving as source and drain regions of the first conductivity type MOS transistor.
とは異なる第３の電源電位が供給される第３の電源ノー
ドに接続されていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the second conductivity type semiconductor region is connected to a third power supply node to which a third power supply potential different from the first and second power supply potentials is supplied. A semiconductor device which is connected.
であることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the first and second first conductivity type semiconductor regions have the same concentration distribution.
れ、第１の電源電位が供給される第１の電源ノードに接
続される第１の第１導電型半導体領域と、 上記半導体基板の中に形成される第２導電型の高エネル
ギーイオン注入層と、 上記半導体基板の一主面に、底面が上記高エネルギーイ
オン注入層の上面とPN接合をなして形成され、上記第１
の電源電位とは異なる第２の電源電位が供給される第２
の電源ノードに接続される第２の第１導電型半導体領域
と、 上記半導体基板の一主面に、底面が上記高エネルギーイ
オン注入層の上面と接するとともに側面が上記第２の第
１導電型半導体領域の側面とPN接合をなして形成され、
上記高エネルギーイオン注入層とで上記第２の第１導電
型半導体領域を上記半導体基板及び上記第１の第１導電
型半導体領域と電気的に絶縁するための第２導電型半導
体領域と、 上記第１の第１導電型半導体領域の表面に形成され、第
１の第２導電型MOSトランジスタのソース及びドレイン
領域となる一対の第２導電型の第１拡散領域と、 上記第２の第１導電型半導体領域の表面に形成され、第
２の第２導電型MOSトランジスタのソース及びドレイン
領域となる一対の第２導電型の第２拡散領域とを備えた
半導体装置を製造する方法において、 上記第１及び第２の第１導電型半導体領域を形成する半
導体領域への第１導電型不純物の拡散を同時に行うこと
を特徴とする半導体装置の製造方法。A first conductive type semiconductor region formed on one main surface of the semiconductor substrate of the first conductive type and connected to a first power supply node supplied with a first power supply potential; A second conductivity type high energy ion implantation layer formed in the semiconductor substrate; and a bottom surface formed on one principal surface of the semiconductor substrate so as to form a PN junction with an upper surface of the high energy ion implantation layer. 1
A second power supply potential different from the power supply potential of
A second first conductivity type semiconductor region connected to a power supply node of the first type; a first surface of the semiconductor substrate having a bottom surface in contact with an upper surface of the high energy ion implanted layer and a side surface having the second first conductivity type. Formed with a PN junction with the side surface of the semiconductor region,
A second conductivity type semiconductor region for electrically insulating the second first conductivity type semiconductor region from the semiconductor substrate and the first first conductivity type semiconductor region with the high energy ion implanted layer; A pair of second diffusion type first diffusion regions formed on the surface of the first first conductivity type semiconductor region and serving as source and drain regions of the first second conductivity type MOS transistor; A method for manufacturing a semiconductor device comprising a pair of second diffusion regions of a second conductivity type formed on a surface of a conductivity type semiconductor region and serving as source and drain regions of a second second conductivity type MOS transistor, A method of manufacturing a semiconductor device, comprising simultaneously diffusing a first conductivity type impurity into a semiconductor region forming first and second first conductivity type semiconductor regions.
位とは異なる第３の電源電位が供給される第３の電源ノ
ードに接続される第２の第２導電型半導体領域と、 この第２の第２導電型半導体領域の表面に形成され、第
１導電型MOSトランジスタのソース及びドレイン領域と
なる一対の第１導電型の拡散領域とを有するものであ
り、 上記第２導電型半導体領域及び第２の第２導電型半導体
領域を形成する半導体領域への第２導電型不純物の拡散
を同時に行うことを特徴とする請求項４記載の半導体装
置の製造方法。5. The semiconductor device according to claim 1, wherein the semiconductor device is formed on one main surface of the semiconductor substrate and connected to a third power supply node to which a third power supply potential different from the first and second power supply potentials is supplied. And a pair of first conductive type diffusion regions formed on the surface of the second second conductive type semiconductor region and serving as source and drain regions of the first conductive type MOS transistor. 5. The semiconductor according to claim 4, wherein the second conductivity type impurity is diffused simultaneously into the second conductivity type semiconductor region and the semiconductor region forming the second second conductivity type semiconductor region. Device manufacturing method.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2172407A JP2609743B2 (en) | 1990-06-28 | 1990-06-28 | Semiconductor device |
| KR1019910010679A KR950009893B1 (en) | 1990-06-28 | 1991-06-26 | Semiconductor memory device |
| US07/722,164 US5281842A (en) | 1990-06-28 | 1991-06-27 | Dynamic random access memory with isolated well structure |
| DE4121292A DE4121292C2 (en) | 1990-06-28 | 1991-06-27 | Semiconductor memory device |
| DE4143521A DE4143521C2 (en) | 1990-06-28 | 1991-06-27 | Semiconductor storage (memory) device |
| US08/496,569 USRE35613E (en) | 1990-06-28 | 1995-06-29 | Dynamic random access memory with isolated well structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2172407A JP2609743B2 (en) | 1990-06-28 | 1990-06-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0461269A JPH0461269A (en) | 1992-02-27 |
| JP2609743B2 true JP2609743B2 (en) | 1997-05-14 |
Family
ID=15941386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2172407A Expired - Lifetime JP2609743B2 (en) | 1990-06-28 | 1990-06-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2609743B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3529549B2 (en) * | 1996-05-23 | 2004-05-24 | 東芝マイクロエレクトロニクス株式会社 | Method for manufacturing semiconductor device |
| US6107672A (en) * | 1997-09-04 | 2000-08-22 | Matsushita Electronics Corporation | Semiconductor device having a plurality of buried wells |
| JP3196714B2 (en) | 1998-03-05 | 2001-08-06 | 日本電気株式会社 | Manufacturing method of semiconductor integrated circuit having triple well structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6110268A (en) * | 1984-06-26 | 1986-01-17 | Nec Corp | Complementary mos semiconductor device and manufacture thereof |
| JPS61115349A (en) * | 1984-11-09 | 1986-06-02 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPH0671067B2 (en) * | 1985-11-20 | 1994-09-07 | 株式会社日立製作所 | Semiconductor device |
-
1990
- 1990-06-28 JP JP2172407A patent/JP2609743B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0461269A (en) | 1992-02-27 |
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