JP2603247B2 - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JP2603247B2 JP2603247B2 JP62074777A JP7477787A JP2603247B2 JP 2603247 B2 JP2603247 B2 JP 2603247B2 JP 62074777 A JP62074777 A JP 62074777A JP 7477787 A JP7477787 A JP 7477787A JP 2603247 B2 JP2603247 B2 JP 2603247B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- insulating film
- thin film
- thin
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 38
- 239000010408 film Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 13
- 230000007423 decrease Effects 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 230000000737 periodic effect Effects 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- -1 for example Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000002123 temporal effect Effects 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005516 deep trap Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000003599 detergent Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、液晶デイスプレイ中のスイツチング用薄膜
トランジスタ（以下TFTと呼ぶ）、フアクシミリ、デジ
タルコピア等の密着型原稿読取り装置中の駆動用TFT、T
FTを光センサとして用いたTFT型センサ等、薄膜半導体
を用いて形成される薄膜トランジスタに係る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a driving thin film transistor (hereinafter referred to as a TFT) in a liquid crystal display, a driving TFT in a contact type document reading apparatus such as a facsimile, a digital copier or the like.
The present invention relates to a thin film transistor formed using a thin film semiconductor, such as a TFT sensor using FT as an optical sensor.
従来、薄膜トランジスタとしては次の技術が先行技術
として提案されている。Conventionally, the following technology has been proposed as a prior art for a thin film transistor.
すなわち、第４図に示す薄膜トランジスタ（特願昭61
−144990及び特願昭61−153281。以下この技術を先行例
という。なお、この技術は公知ではない）である。That is, the thin film transistor shown in FIG.
−144990 and Japanese Patent Application No. 61-153281. Hereinafter, this technique is referred to as a prior art. This technique is not known).
第４図は本出願人によって既に提案されている薄膜ト
ランジスタの概略を説明するための基本構成図である。FIG. 4 is a basic configuration diagram for explaining an outline of a thin film transistor already proposed by the present applicant.
第４図において、透明又は不透明の絶縁基板１上に
は、透明又は不透明の導電層がパターニングされてゲー
ト電極５が形成され、さらに、SiOxやSiNx等の絶縁膜ｂ
がスパツタリング法やグロー放電法等によって形成され
ている。絶縁膜ｂ上にはＡ−Si:H（水素化アモルフアス
シリコン）からなる半導体層２、ドーピング半導体層3,
3′、主電極4,4′（ここでドレイン電極４及びソース電
極４′とする。）が各々形成されている。In FIG. 4, a transparent or opaque conductive layer is patterned on a transparent or opaque insulating substrate 1 to form a gate electrode 5, and an insulating film b such as SiOx or SiNx is formed.
Are formed by a sputtering method, a glow discharge method, or the like. On the insulating film b, a semiconductor layer 2 made of A-Si: H (hydrogenated amorphous silicon), a doped semiconductor layer 3,
3 'and main electrodes 4, 4' (here, drain electrodes 4 and source electrodes 4 ') are formed.
しかし、上記先行技術には次に述べるような問題点が
ある。However, the above prior art has the following problems.
すなわち、第４図に示すTFTにおいては、 ゲート絶縁膜と半導体層との界面近傍に多量のトラツ
プが存在するため、ここに徐々にキヤリアが捕獲される
て。その結果、しきい値電圧Vtの移動が生じ、ドレイン
電流の経時変化が起こされるという問題点がある。That is, in the TFT shown in FIG. 4, since a large amount of trap exists near the interface between the gate insulating film and the semiconductor layer, the carrier is gradually captured here. This results in movement of the threshold voltage V t, there is a problem that aging of the drain current is caused.
界面の影響（イオンや、トラツプ）を受けやすく、ま
た、界面近傍の半導体層の安定性、再現性が乏しい。It is susceptible to the influence of an interface (ion or trap), and the stability and reproducibility of the semiconductor layer near the interface are poor.
上記問題点は、基板の絶縁性表面上に設けられた、薄
膜半導体層と該薄膜半導体層に配設されたソース及びド
レイン電極と該薄膜半導体層に絶縁膜を介して配設され
たゲート電極とを有する薄膜トランジスタにおいて、前
記薄膜半導体層は、シリコン原子に対して10原子％以下
の水素を含有するとともに、周期律表第Ｖ族に属する原
子の少なくとも１種を10ppb乃至20ppm含有する水素化非
晶質シリコンであり、前記周期律表第Ｖ族に属する原子
は、前記薄膜半導体層の膜厚方向において、前記絶縁膜
近傍で多く、該絶縁膜から離れるに従って少なくなるよ
うに分布していることを特徴とする薄膜トランジスタに
よって解決される。The above problems are caused by a thin-film semiconductor layer provided on an insulating surface of a substrate, source and drain electrodes provided on the thin-film semiconductor layer, and a gate electrode provided on the thin-film semiconductor layer via an insulating film. Wherein the thin film semiconductor layer contains 10 atomic% or less of hydrogen with respect to silicon atoms and at least 10 ppb to 20 ppm of at least one atom belonging to Group V of the periodic table. Amorphous silicon, and the atoms belonging to Group V of the periodic table are distributed in such a manner as to increase in the thickness direction of the thin film semiconductor layer near the insulating film and decrease as the distance from the insulating film decreases. The problem is solved by a thin film transistor characterized by the following.
絶縁基板としては、たとえばガラス，セラミツクス等
を使用すれば良い。また、透明な絶縁基板を使用しても
不透明な絶縁基板を使用してもよい。As the insulating substrate, for example, glass, ceramics, or the like may be used. Further, a transparent insulating substrate or an opaque insulating substrate may be used.
絶縁基板上に形成された半導体層の材料としては、水
素化アモルフアスシリコンが良好に実施され、通常のシ
リコン原子に対して水素を０原子％乃至10原子％含有す
る。As a material of the semiconductor layer formed on the insulating substrate, hydrogenated amorphous silicon is favorably implemented, and contains 0 to 10 atomic% of hydrogen with respect to normal silicon atoms.
該半導体層上に対応して形成された一対の主電極と、
該半導体層と絶縁膜を介して形成されるゲート電極の位
置関係としては、第３図（Ｄ）に示す下ゲートスタガー
型，或いは下ゲートコプレナー型，上ゲートコプレナー
型とすることができる。A pair of main electrodes correspondingly formed on the semiconductor layer,
The positional relationship between the semiconductor layer and the gate electrode formed via the insulating film can be a lower gate stagger type, a lower gate coplanar type, or an upper gate coplanar type shown in FIG. .
第Ｖ族に属する原子としては、主としてＶ（ｂ）に属
する原子が用いられる。たとえば、N,P,As,Sb,Biであ
る。As an atom belonging to Group V, an atom mainly belonging to V (b) is used. For example, N, P, As, Sb, Bi.
また、これらの原子は１種でもよく、２種以上を併用
してもよい。In addition, these atoms may be used alone or in combination of two or more.
不純物のドープ領域は、半導体層と絶縁膜との少なく
とも界面近傍とし、該領域における不純物濃度は、10pp
b以上、乃至2ppm含むことが好ましい。The impurity-doped region is at least near the interface between the semiconductor layer and the insulating film, and the impurity concentration in the region is 10 pp.
It is preferable to contain b or more and 2 to 2 ppm.
また、本発明においては、膜厚方向に傾斜を持たせ、
ゲート絶縁膜近傍の不純物濃度を多くし、絶縁膜から離
れるに従って不純物を下げたことにより、絶縁膜近傍で
のｎ型半導体のバンドをより急激に絶縁膜に向かって深
く曲げることができ、off抵抗を下げずにon抵抗を向上
できる。Further, in the present invention, by giving a gradient in the film thickness direction,
By increasing the impurity concentration near the gate insulating film and decreasing the impurity as the distance from the insulating film increases, the band of the n-type semiconductor near the insulating film can be bent more sharply toward the insulating film and the off resistance The on resistance can be improved without lowering the resistance.
なお、主電極には、Al,Cr等の導電性の金属を用いれ
ばよい。その形成手段も例えばスパツタ法等の常用手段
によればよい。Note that a conductive metal such as Al or Cr may be used for the main electrode. The forming means may be a conventional means such as a spatter method.
また、不純物のドーピング手段としては、SiH4ガスの
グロー放電分解法の場合、PH3,N2,NH3,AsH3ガス等を混
合してドープする等、通常知られるもろもろの手段を用
いることができる。In addition, in the case of the glow discharge decomposition method of SiH 4 gas, various known means such as doping by mixing PH 3 , N 2 , NH 3 , AsH 3 gas, or the like may be used as the impurity doping means. Can be.
まず、ドーピングによってゲート絶縁膜の近傍をｎ型
化した場合の作用について図面を用いて説明する。First, the operation when the vicinity of the gate insulating film is made n-type by doping will be described with reference to the drawings.
第１図はTFTにおける半導体層13のバンド状態を示す
モデル図である。FIG. 1 is a model diagram showing a band state of the semiconductor layer 13 in the TFT.
第１図（Ａ）は先行例の場合、すなわち半導体層13に
ｉ層のみのＡ−Si:H半導体層を用いた場合である。FIG. 1A shows the case of the prior art, that is, the case where only the i-layer A-Si: H semiconductor layer is used for the semiconductor layer 13.
半導体層13のゲート絶縁膜12近傍をドーピングにより
ｎ型化することで、第１図（Ｂ）に示すように、絶縁膜
12近傍の半導体層13のバンドは、絶縁膜12からある厚さ
のところをピークに絶縁膜12に近づくにつれ下がってい
く。By making the vicinity of the gate insulating film 12 of the semiconductor layer 13 n-type by doping, as shown in FIG.
The band of the semiconductor layer 13 in the vicinity of 12 peaks at a certain thickness from the insulating film 12 and decreases as approaching the insulating film 12.
そして本発明においては、上記界面近傍の深いトラツ
プは、半導体層16のフエルミ準位の位置を適当に選ぶこ
とにより、実効的に不活性化することができる。In the present invention, the deep trap near the interface can be effectively inactivated by appropriately selecting the position of the Fermi level of the semiconductor layer 16.
以下より詳細に説明する。 This will be described in more detail below.
ノンドープの場合（先行例の場合）においては、第１
図（ａ）（Ａ）に示すように、ゲート絶縁膜12と半導体
層13の界面近傍のアクセプタ型のトラツプ40は、ゲート
電極11へのバイアス電圧が零電圧（VG＝０）のとき、フ
エルミ準位（EF）よりわずかに上位のエネルギーレベル
に位置する。In the case of non-doping (in the case of the preceding example), the first
As shown in FIGS. 5A and 5A, the acceptor trap 40 near the interface between the gate insulating film 12 and the semiconductor layer 13 has a bias voltage to the gate electrode 11 of zero voltage (V G = 0). It is located at an energy level slightly higher than the Fermi level (E F ).
また、第１図（ｂ）（Ｂ）に示すように、ゲート電極
11へ正のバイアス電圧を印加（VG＞０）すると、界面近
傍のトラツプ40はフエルミ準位の下位へ移動するため、
上記トラツプ40は比較的緩慢に電子を捕獲し、負に帯電
する。このためTFTのドレイン電流の経時的な減少を生
ずる。Also, as shown in FIGS. 1B and 1B, the gate electrode
When a positive bias voltage is applied to 11 (V G > 0), the trap 40 near the interface moves to the lower level of the Fermi level.
The trap 40 captures electrons relatively slowly and becomes negatively charged. For this reason, the drain current of the TFT decreases with time.
一方、半導体層13にｎ型のドーパントを10ppb乃至2pp
m、より好ましくは100ppb乃至200ppb混入した場合（本
発明の実施例の場合）においては、 第１図（ｂ）（Ｂ）に示すように、ゲート電極11への
バイアス電圧が零電圧（VG＝０）のときにも、トラツプ
40はフエルミ準位より下位のエネルギーレベルに位置す
る。On the other hand, an n-type dopant is added to the semiconductor layer 13 in an amount of 10 ppb to 2 pp.
m, more preferably 100 ppb to 200 ppb (in the case of the embodiment of the present invention), the bias voltage applied to the gate electrode 11 becomes zero voltage (V G = 0)
40 is located at an energy level lower than the Fermi level.
また、第１図（ａ）（Ｂ）に示すように、ゲート電極
11への正のバイアス電圧を印加（VG＝０）しても上記位
置関係は変化しない。Also, as shown in FIGS. 1A and 1B, the gate electrode
Positive applied bias voltage (V G = 0) and the positional relation even to 11 does not change.
このため、ゲート電極11への正のバイアスを印加して
もTFTのドレイン電流の経時的な減少は小さくおさえる
ことができる。Therefore, even if a positive bias is applied to the gate electrode 11, a decrease in the drain current of the TFT over time can be suppressed small.
図中、トラツプレベルの斜線は、電子のトラツプされ
ている状態を示している。In the figure, the hatching at the trap level indicates a state where electrons are trapped.
ノンドープの場合（先行例）の場合にはゲートバイア
ス正（TFTのON状態）へ変化したときアクセプタレベル
へ電子がトラツプする状態へ変化し、本発明では、ゲー
トバイアス正へ変化したときにも０〜負のゲートバイア
ス時にも電子がトラツプされた状態のままであり、変化
を生じない。In the case of non-doping (previous example), when the gate bias is changed to positive (TFT ON state), the state changes to a state where electrons are trapped at the acceptor level. -Even when a negative gate bias is applied, electrons remain trapped and no change occurs.
（第１実施例） 第３図は本発明の実施例に係るTFTを作成する工程を
説明するための断面図である。First Embodiment FIG. 3 is a cross-sectional view for explaining a step of manufacturing a TFT according to an embodiment of the present invention.
まず、両面研磨済みのガラス基板101（コーニング社
製＃7059）に中性洗剤を用いて洗浄を施す。First, the glass substrate 101 (Corning # 7059) polished on both sides is cleaned with a neutral detergent.
次に、スパツタ法でAl102を0.1μｍ厚に堆積させ、ポ
ジ型フオトレジスト（OFPR−800東京応化工業性）を用
いて所望の形状にフオトレジストのパターンを形成した
後、リン酸（85％水溶液）、硝酸（60％水溶液）、酢酸
及び水を16:1:2:1の容積比で混合した液（以下「Al用エ
ツチング液」という。）でエツチングし、制御電極とし
てゲート電極を形成した。Next, Al102 is deposited to a thickness of 0.1 μm by a sputter method, and a photoresist pattern is formed in a desired shape using a positive photoresist (OFPR-800, Tokyo Ohka Kogyo Co., Ltd.). ), Nitric acid (60% aqueous solution), acetic acid and water mixed at a volume ratio of 16: 1: 2: 1 (hereinafter referred to as “etching solution for Al”) to form a gate electrode as a control electrode. .
フオトレジスト剥離後、容量結合型のグロー放電分解
装置内にガラス基板をセツトし、１×10-6Torrの排気真
空下で350℃に維持した。After the photoresist was stripped, the glass substrate was set in a capacitively coupled glow discharge decomposition apparatus and maintained at 350 ° C. under an exhaust vacuum of 1 × 10 −6 Torr.
次に該装置内に水素希釈10％SiH4ガス（小松電子製）
を100sccm、99.999％のNH3ガスを280sccmの流量で流入
させ、ガス圧力を0.2Toorに設定した後、13.56MHzの高
周波電源を用いRF（Radio−Frequency）放電パワー30W
でグロー放電を行い、3000ÅのＡ−SiNx:H層103を形成
した。Next, 10% SiH 4 gas diluted with hydrogen (made by Komatsu Electronics)
100 sccm, 99.999% NH 3 gas was introduced at a flow rate of 280 sccm, the gas pressure was set to 0.2 Toor, and RF (Radio-Frequency) discharge power 30 W using a 13.56 MHz high frequency power supply
Glow discharge was performed to form a 3000 ° A-SiNx: H layer 103.
続いて基板温度を210℃に保持し、10％SiH4（H2ベー
ス）600sccmと、10ppmPH3（H2ベース）を0sccm乃至10sc
cm混合させ、ガス圧力0.5Torrの条件でRF放電パワー70W
のグロー放電を行い、ｎ型アモルフアスシリコン半導体
層105を厚さ4000Å形成した。この時、10ppmPH3（H2ベ
ース）ガスの流量比を以下の如く４点振り、特性を比較
した。Subsequently, the substrate temperature was maintained at 210 ° C., and 10% SiH 4 (H 2 base) at 600 sccm and 10 ppm PH 3 (H 2 base) at 0 sccm to 10 sccm
cm discharge, RF discharge power 70 W under the condition of gas pressure 0.5 Torr
Glow discharge was performed to form an n-type amorphous silicon semiconductor layer 105 having a thickness of 4000. At this time, the flow rate ratio of 10 ppm PH 3 (H 2 based) gas was changed at four points as follows, and the characteristics were compared.
（ａ）PH3/SiH4＝2ppb （ｂ）PH3/SiH4＝20ppb （ｃ）PH3/SiH4＝200ppb （ｄ）PH3/SiH4＝2ppm 次に、10％SiH4（H2ベース）30sccm、PH3150sccm、ガ
ス圧力を0.5Torrとし、基板温度を190℃に保持し、RF放
電パワーを200Wでグロー放電を行い、オーミツクコンタ
クト層のn+層106を厚さ1500Å形成した。(A) PH 3 / SiH 4 = 2 ppb (b) PH 3 / SiH 4 = 20 ppb (c) PH 3 / SiH 4 = 200 ppb (d) PH 3 / SiH 4 = 2 ppm Next, 10% SiH 4 (H 2 Base) 30 sccm, PH 3 150 sccm, gas pressure 0.5 Torr, substrate temperature is maintained at 190 ° C., RF discharge power is 200 W, glow discharge is performed, and the n + layer 106 of the ohmic contact layer is formed to a thickness of 1500 Å. .
次に、スパツタ法により、Al（膜厚１μｍ）を堆積し
（第３図（Ａ））、ポジ型フオトレジストを用いて所望
の形状にフオトレジストパターンを形成し、Al用エツチ
ング液でAlをエツチングして主電極4,4′を形成した
（第３図（Ｂ））。Next, Al (1 μm thick) is deposited by a sputter method (FIG. 3 (A)), a photoresist pattern is formed in a desired shape using a positive type photoresist, and Al is etched with an etching solution for Al. Etching was performed to form main electrodes 4, 4 '(FIG. 3 (B)).
主電極4,4′をマスクにしてフツ酸（59％水溶液）、
硝酸（70％水溶液）、酢酸を2:10:88の容積比で混合し
た液にヨウ素を過飽和溶解させた溶液でn+層を選択的に
エツチングして除去し、フオトレジストを剥離した。Fluoric acid (59% aqueous solution) using the main electrodes 4, 4 'as a mask,
The n + layer was selectively etched and removed with a solution in which iodine was supersaturated and dissolved in a mixture of nitric acid (70% aqueous solution) and acetic acid at a volume ratio of 2:10:88, and the photoresist was stripped.
フオトレジストパターンを形成し、リアクテイブイオ
ンエツチング装置（RIE）を用いて不要な部分のＡ−Si:
H及びＡ−SiNx:H層を除去し、素子間の分離を行った
（第３図（Ｃ））。A photoresist pattern is formed, and an unnecessary portion of A-Si is formed using a reactive ion etching apparatus (RIE).
The H and A-SiNx: H layers were removed to separate the elements (FIG. 3C).
しかる後に電極の取り出し部以外のところにシリコー
ン樹脂を塗布し、パツシベーシヨン材とした。Thereafter, a silicone resin was applied to a portion other than the portion from which the electrode was taken out to obtain a passivation material.
この時、PH3/SiH4の各流量比に対する、n-型Ａ−Si:H
層中におけるリンの濃度をSIMSを用いて調べたところ以
下の如くなった。At this time, for each flow ratio of PH 3 / SiH 4 , n - type A-Si: H
When the concentration of phosphorus in the layer was examined using SIMS, it was as follows.
（ａ）検出限界下 （ｂ）8ppb （ｃ）100ppb （ｄ）1ppm このようにして作成したTFTについて、その特性を調
べた。その結果を第２図（Ａ）、（Ｂ）、（Ｃ）に示
す。これらより、ドーピングの濃度を増すに従い （１）off時のドレイン電流Idが上昇する （２）しきい値電圧Vth（初期）が負側に変わる （３）一定時間のon動動後のVth変動△Vthが小さくなる （４）（３）に関連してon時のドレイン電流の経時変化
が小さくなる といった作用が出ることがわかる。(A) Under detection limit (b) 8 ppb (c) 100 ppb (d) 1 ppm The characteristics of the TFT thus prepared were examined. The results are shown in FIGS. 2 (A), (B) and (C). From these, as the doping concentration increases, (1) the drain current Id at the time of off increases, (2) the threshold voltage V th (initial) changes to the negative side, and (3) V after the on operation for a certain time. The th variation ΔV th becomes smaller. (4) It can be seen that, in connection with (3), there is an effect that the temporal change of the drain current at the time of on becomes smaller.
このことにより、好ましい量のリンのＡ−Si:H半導体
層へのドーピングにより、Vthの制御が可能となり、Vth
の変動も少なく、ドレイン電流の経時変化を小さく抑え
るといった効果を見い出すことができる。Thus, the preferred amounts of phosphorus A-Si: by doping into H semiconductor layer, it is possible to control the V th, V th
And the effect of suppressing the temporal change of the drain current can be found.
そして、アモルフアスシリコン半導体層105の成膜中
にPH3の濃度を徐々に減少させれば、周期律表第Ｖ族に
属する原子が、薄膜半導体層の膜厚方向において、絶縁
膜近傍で多く、絶縁膜から離れるに従って少なくなる分
布を得ることができる。If the concentration of PH 3 is gradually reduced during the formation of the amorphous silicon semiconductor layer 105, the number of atoms belonging to Group V of the periodic table increases in the thickness direction of the thin film semiconductor layer near the insulating film. It is possible to obtain a distribution that decreases as the distance from the insulating film increases.
（第２実施例） 第１実施例において、ｎ型Ａ−Si:H層のドーピングガ
スとしてN2を用い、n-型Ａ−Si:H層を形成した以外は、
同じ条件で作成したTFT。Second Example In the first example, N 2 was used as a doping gas for the n - type A-Si: H layer, and an n − -type A-Si: H layer was formed.
TFT created under the same conditions.
以上のように作成したTFTにおいても、実施例１と同
様の効果が得られた。The same effect as in the first embodiment was obtained in the TFT prepared as described above.
［発明の効果］ 本発明によれば次の効果が得られる。According to the present invention, the following effects can be obtained.
しきい値電圧の変化が少なく、ドレイン電流の経時変
化が起きない。The change in threshold voltage is small, and the drain current does not change with time.
n-ドーピング領域はフェルミレベルの制御を容易に、
しきい値電圧の制御が可能となり、均一性、再現性を向
上できる。n - doping region facilitates control of Fermi level,
The threshold voltage can be controlled, and uniformity and reproducibility can be improved.
絶縁膜近傍でのｎ型半導体のバンドはより急激に絶縁
膜に向かって深く曲げることができる。The band of the n-type semiconductor near the insulating film can be bent more sharply toward the insulating film.
第１図はTFTにおける半導体層13のバンド状態を示すモ
デル図である。第２図（Ａ），（Ｂ），（Ｃ）は、第１
実施例に係るTFTでの特性を示すグラフである。第３図
は第１実施例に係るTFTの製造過程を示すための断面図
である。第４図は先行列に係るTFTを示す断面図であ
る。 １……絶縁基板、２……半導体層、3,3′……ドーピン
グ半導体層、4,4′……電極、５……ゲート電極、６…
…絶縁膜、７……直流電源、８……可変直流電源、11…
…ゲート電極、12……ゲート絶縁膜、13……半導体層、
14,15……ｎ型高密度不純物層、16……ｎ領域、40……
トラップ、101……ガラス基板、102……ゲート電極（A
l）、103……絶縁膜、105……ｎ型半導体領域、106……
オーミックコンタクト層、107……主電極 第２図の説明 （ａ）PH3/SiH4＝2ppb （ｂ）PH3/SiH4＝20ppb （ｃ）PH3/SiH4＝200ppb （ｄ）PH3/SiH4＝2ppm 図（Ａ）ドレイン電圧VD＝1Vで測定 図（Ｂ）ドレイン電圧VD＝20Vで測定 図（Ｃ）ドレイン電圧VD＝2V ゲート電圧VG＝20v 劣化時間 120分で測定FIG. 1 is a model diagram showing a band state of the semiconductor layer 13 in the TFT. 2 (A), (B) and (C) show the first
4 is a graph showing characteristics of a TFT according to an example. FIG. 3 is a cross-sectional view for illustrating a manufacturing process of the TFT according to the first embodiment. FIG. 4 is a cross-sectional view showing a TFT relating to the front matrix. DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Semiconductor layer, 3,3 '... Doping semiconductor layer, 4,4' ... Electrode, 5 ... Gate electrode, 6 ...
... insulating film, 7 ... DC power supply, 8 ... variable DC power supply, 11 ...
... gate electrode, 12 ... gate insulating film, 13 ... semiconductor layer,
14,15 ... n-type high-density impurity layer, 16 ... n region, 40 ...
Trap, 101 glass substrate, 102 gate electrode (A
l), 103 ... insulating film, 105 ... n-type semiconductor region, 106 ...
Ohmic contact layer, 107... Main electrode Description of FIG. 2 (a) PH 3 / SiH 4 = 2 ppb (b) PH 3 / SiH 4 = 20 ppb (c) PH 3 / SiH 4 = 200 ppb (d) PH 3 / SiH 4 = 2ppm Figure (A) Measured at drain voltage VD = 1V Figure (B) Measured at drain voltage VD = 20V Figure (C) Drain voltage VD = 2V Gate voltage VG = 20v Degradation time Measured at 120 minutes
Claims (2)
導体層と該薄膜半導体層に配設されたソース及びドレイ
ン電極と該薄膜半導体層に絶縁膜を介して配設されたゲ
ート電極とを有する薄膜トランジスタにおいて、 前記薄膜半導体層は、シリコン原子に対して10原子％以
下の水素を含有するとともに、周期律表第Ｖ族に属する
原子の少なくとも１種を10ppb乃至20ppm含有する水素化
非晶質シリコンであり、前記周期律表第Ｖ族に属する原
子は、前記薄膜半導体層の膜厚方向において、前記絶縁
膜近傍で多く、該絶縁膜から離れるに従って少なくなる
ように分布していることを特徴とする薄膜トランジス
タ。1. A thin-film semiconductor layer provided on an insulating surface of a substrate, source and drain electrodes provided on the thin-film semiconductor layer, and a gate electrode provided on the thin-film semiconductor layer via an insulating film. Wherein the thin film semiconductor layer contains 10 atomic% or less of hydrogen with respect to silicon atoms and at least 10 ppb to 20 ppm of an atom belonging to Group V of the periodic table. Amorphous silicon, and the atoms belonging to Group V of the periodic table are distributed in such a manner as to increase in the thickness direction of the thin film semiconductor layer near the insulating film and decrease as the distance from the insulating film decreases. A thin film transistor characterized by the above-mentioned.
As,Sb,Biから選択される原子である特許請求の範囲第１
項に記載の薄膜トランジスタ。2. The atoms belonging to Group V of the periodic table are N, P,
Claim 1 which is an atom selected from As, Sb and Bi
Item 14. The thin film transistor according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62074777A JP2603247B2 (en) | 1987-03-27 | 1987-03-27 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62074777A JP2603247B2 (en) | 1987-03-27 | 1987-03-27 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6439067A JPS6439067A (en) | 1989-02-09 |
| JP2603247B2 true JP2603247B2 (en) | 1997-04-23 |
Family
ID=13557060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62074777A Expired - Fee Related JP2603247B2 (en) | 1987-03-27 | 1987-03-27 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2603247B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2952887B2 (en) * | 1989-05-20 | 1999-09-27 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5456380A (en) * | 1977-10-14 | 1979-05-07 | Asahi Chemical Ind | Thin film ic |
| JPS6226861A (en) * | 1985-07-29 | 1987-02-04 | Hitachi Ltd | Amorphous silicon thin film transistor |
-
1987
- 1987-03-27 JP JP62074777A patent/JP2603247B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6439067A (en) | 1989-02-09 |
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