JP2590681B2 - Semiconductor logic circuit device - Google Patents
Semiconductor logic circuit deviceInfo
- Publication number
- JP2590681B2 JP2590681B2 JP5096358A JP9635893A JP2590681B2 JP 2590681 B2 JP2590681 B2 JP 2590681B2 JP 5096358 A JP5096358 A JP 5096358A JP 9635893 A JP9635893 A JP 9635893A JP 2590681 B2 JP2590681 B2 JP 2590681B2
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- JP
- Japan
- Prior art keywords
- mos transistor
- transistor
- drain
- level
- circuit
- Prior art date
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- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体論理回路装置に関
し、特にＢｉＣＭＯＳやＣＭＯＳ技術を用いた半導体論
理回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit device, and more particularly to a semiconductor logic circuit device using BiCMOS or CMOS technology.
【０００２】[0002]
【従来の技術】従々来の半導体論理回路装置は、例え
ば、図６〜図９に示す様な回路構成となっている。2. Description of the Related Art A conventional semiconductor logic circuit device has a circuit configuration as shown in FIGS. 6 to 9, for example.
【０００３】図６はＣＭＯＳ構成の、図７はＢｉＣＭＯ
Ｓ構成のＮＯＲ回路の１例であり、どちらも２つの入力
信号端子Ａ，Ｂがともにロウ（以下Ｌ）レベルの時のみ
ハイ（以下Ｈ）レベルを出力し、それ以外の時はＬレベ
ルを出力する。FIG. 6 shows a CMOS configuration, and FIG. 7 shows a BiCMO.
This is an example of a NOR circuit having an S configuration. Both circuits output a high (H) level only when both input signal terminals A and B are at a low (L) level, and output an L level otherwise. Output.
【０００４】図８はＣＭＯＳ構成の、図９はＢｉＣＭＯ
Ｓ構成のＮＡＮＤ回路の１例であり、どちらも２つの入
力信号端子Ａ，ＢがともにＨレベルの時のみＬレベルを
出力し、それ以外の時はＨレベルを出力する。FIG. 8 shows a CMOS configuration, and FIG. 9 shows a BiCMO.
This is an example of a NAND circuit having an S configuration, and both output an L level only when the two input signal terminals A and B are both at an H level, and output an H level otherwise.
【０００５】また、面積を縮小する効果を目的とした最
新の従来技術としては、「特開平２−２７１７１４」で
示されている図１０〜図１３の様な半導体論理回路装置
がある。Further, as the latest prior art for the purpose of reducing the area, there is a semiconductor logic circuit device shown in FIG. 10 to FIG. 13 shown in Japanese Patent Laid-Open No. 2-271714.
【０００６】図１０はＸＯＲ回路であり、２つの入力信
号端子Ａ，Ｂの論理値が相異なる時Ｈレベルを出力し、
一致する時Ｌレベルを出力する。FIG. 10 shows an XOR circuit which outputs an H level when the logic values of two input signal terminals A and B are different from each other,
When they match, an L level is output.
【０００７】図１１はＸＮＯＲ回路であり、２つの入力
信号端子Ａ，Ｂの論理値が相異なる時Ｌレベルを出力
し、一致する時Ｈレベルを出力する。FIG. 11 shows an XNOR circuit which outputs an L level when the logic values of the two input signal terminals A and B are different, and outputs an H level when they match.
【０００８】図１２はＯＲ回路であり、２つの入力信号
端子Ａ，ＢがともにＬレベルの時のみＬレベルを出力
し、それ以外の時はＨレベルを出力する。FIG. 12 shows an OR circuit which outputs an L level only when the two input signal terminals A and B are both at an L level, and outputs an H level otherwise.
【０００９】図１３はＡＮＤ回路であり、２つの入力信
号端子Ａ，ＢがともにＨレベルの時のみＨレベルを出力
し、それ以外の時はＬレベルを出力する。FIG. 13 shows an AND circuit which outputs an H level only when the two input signal terminals A and B are both at an H level, and outputs an L level otherwise.
【００１０】[0010]
【発明が解決しようとする課題】上述した様な従々来技
術では、ＭＯＳトランジスタで論理演算を行う部分で２
入力信号がともにゲートに接続され、かつ、図６，７で
はＰ型ＭＯＳトランジスタが、図８，９ではＮ型ＭＯＳ
トランジスタがそれぞれ２個直列に接続されているた
め、論理回路の遅延時間（ｔPD）が増加し、面積も増え
る。また、ゲート容量が大きなため、前段の回路の負荷
が大きくなってしまう、という問題点があった。In the conventional technology as described above, a portion where a logical operation is performed by a MOS transistor is used.
The input signals are both connected to the gate, and the P-type MOS transistor is used in FIGS.
Since two transistors are connected in series, the delay time (t PD ) of the logic circuit increases, and the area also increases. In addition, there is a problem that the load of the circuit in the preceding stage increases due to the large gate capacitance.
【００１１】また、前記問題点のうち面積の縮小を目的
とした「特開平２−２７１７１４」に示された最新の従
来技術の回路構成ではＮＯＲやＮＡＮＤ回路は構成でき
ず、図１２，１３の前または後にインバータ回路を接続
したような構成をとらねばならず、面積縮小の効果が得
られない。しかも根本的な問題として、図１０，１２で
はＢ＝Ｌ、図１１，１３ではＢ＝Ｈの時、実際には出力
はフローティング状態で確定しないため、この回路では
「特開平２−２７１７１４」で期待されている論理動作
を行えない、という問題点があった。Of the above problems, a NOR or NAND circuit cannot be constructed with the latest prior art circuit configuration disclosed in Japanese Patent Application Laid-Open No. 2-271714 for the purpose of reducing the area. It is necessary to adopt a configuration in which an inverter circuit is connected before or after, and the effect of reducing the area cannot be obtained. In addition, as a fundamental problem, when B = L in FIGS. 10 and 12 and B = H in FIGS. 11 and 13, the output is not actually determined in a floating state. There has been a problem that the expected logical operation cannot be performed.
【００１２】[0012]
【課題を解決するための手段】２つの入力信号から論理
出力信号を生成する半導体論理回路において、ソースが
第１の入力信号端子に接続され、ゲートが第２の入力信
号端子に接続されたＭＯＳ型トランジスタを少なくとも
１つ有すること。また前記手段において、第１の入力信
号端子が接続されたＭＯＳ型トランジスタのソース部
を、同一信号が入力される他のＭＯＳ型トランジスタの
ソース部とマスクパタン上共通にすること。SUMMARY OF THE INVENTION In a semiconductor logic circuit for generating a logic output signal from two input signals, a MOS transistor having a source connected to a first input signal terminal and a gate connected to a second input signal terminal. Having at least one type transistor. Further, in the above means, the source portion of the MOS transistor to which the first input signal terminal is connected is made common to the source portion of another MOS transistor to which the same signal is input on a mask pattern.
【００１３】[0013]
【実施例１】次に本発明について図面を参照して説明す
る。Embodiment 1 Next, the present invention will be described with reference to the drawings.
【００１４】図１は本発明の実施例１を示す回路図であ
る。この実施例はソース部が第１の信号入力端子Ａに接
続され、ゲート部が第２の信号入力端子Ｂに接続され、
ドレイン部が出力信号端子ＯＵＴに接続されたＰ型の第
１のＭＯＳトランジスタＰ11と、ソース部が低電位側の
電源供給端子ＧＮＤに接続され、ゲート部が第２の信号
入力端子Ｂに接続され、ドレイン部が出力信号端子ＯＵ
Ｔに接続されたＮ型の第２のＭＯＳトランジスタＮ
11と、ソース部が低電位側の電源供給端子に接続され、
ゲート部が高電位側の電源供給端子ＶＣＣに接続され、
ドレイン部が出力信号端子ＯＵＴと接続されたＮ型の第
３のＭＯＳトランジスタＮ12とを有する構成となってい
る。FIG. 1 is a circuit diagram showing Embodiment 1 of the present invention. In this embodiment, the source section is connected to the first signal input terminal A, the gate section is connected to the second signal input terminal B,
A first MOS transistor P 11 the drain portion is connected to P-type to the output signal terminal OUT, and the source unit is connected to the power supply terminal GND on the low potential side, the gate portion is connected to the second signal input terminal B And the drain is connected to the output signal terminal OU.
N-type second MOS transistor N connected to T
11 and the source part is connected to the power supply terminal on the low potential side,
The gate is connected to the power supply terminal VCC on the high potential side,
It has a configuration having a first 3 MOS transistor N 12 of the N-type drain part is connected to the output signal terminal OUT.
【００１５】次にこの実施例の動作について説明する。Next, the operation of this embodiment will be described.
【００１６】第１の入力信号端子ＡがＬレベルすなわち
低電位側にあるときは、トランジスタＰ11は常にＯＦＦ
状態であり、第２の入力信号端子ＢがＨレベルすなち高
電位側にある時はトランジスタＮ11はＯＮ状態となり、
出力信号端子ＯＵＴはＬレベルとなる。また、第２の入
力信号端子ＢがＬレベルの時はＰ11，Ｎ11ともＯＦＦ状
態となるが、ゲート部が高電位電源端子にあるため常に
ＯＮ状態であるトランジスタＮ12により、出力信号端子
ＯＵＴはフローティング状態にはならず、Ｌレベルを出
力する。[0016] When the first input signal terminal A is at the L level, that is the low potential side, the transistor P 11 is always OFF
A state, when the second input signal terminal B is at the H level sand high potential side transistor N 11 is turned ON,
The output signal terminal OUT becomes L level. When the second input signal terminal B is at the L level, both P 11 and N 11 are in the OFF state. However, since the gate portion is at the high potential power supply terminal, the transistor N 12 which is always in the ON state provides the output signal terminal. OUT does not enter a floating state but outputs an L level.
【００１７】次に、第１の入力信号端子ＡがＨレベルに
ある時は、第２の入力信号端子ＢがＨレベルの時はトラ
ンジスタＰ11はＯＦＦ、Ｎ11，Ｎ12はＯＮなので出力信
号端子ＯＵＴはＬレベルとなる。第２の入力信号端子Ｂ
がＬレベルの時はトランジスタＰ11，Ｎ12はＯＮ，Ｎ11
はＯＦＦとなり、この時トランジスタＮ12のサイズがト
ランジスタＰ11のサイズに比べて充分に小さい、すなわ
ちＯＮ状態での抵抗成分が充分に大きいとすれば、出力
信号端子ＯＵＴはＨレベルを出力する。Next, when the first input signal terminal A is at the H level, the transistor P 11 when the second input signal terminal B is H level OFF, N 11, N 12 is ON since the output signal The terminal OUT becomes L level. Second input signal terminal B
Are at L level, transistors P 11 and N 12 are ON and N 11
Next is OFF, this time the size of the transistor N 12 is sufficiently small compared to the size of the transistors P 11, i.e. assuming that there is sufficiently large resistance component in the ON state, the output signal terminal OUT outputs a H level.
【００１８】従って、この実施例は２入力信号Ａ，Ｂの
４通りの組み合わせに対し、Ａ＝Ｈ，Ｂ＝Ｌの選択状態
の時のみＨレベルを出力し、それ以外の時はＬレベルを
出力するという図６，７で示したＮＯＲ回路と同等の論
理動作を行う。Accordingly, this embodiment outputs an H level only when A = H and B = L is selected for four combinations of two input signals A and B, and otherwise outputs an L level. A logical operation equivalent to that of the NOR circuit shown in FIGS.
【００１９】このとき図１と図６を比較して明らかなよ
うに本実施例の方が素子数が少なくて済み面積縮小の効
果が得られる。また本実施例では図６のトランジスタＰ
61，Ｐ62の様な直列接続が存在しないのでｔPDの高速化
がはかれる。At this time, as is apparent from a comparison between FIG. 1 and FIG. 6, in this embodiment, the number of elements is smaller and the effect of reducing the area can be obtained. In this embodiment, the transistor P shown in FIG.
61, since the series connection, such as the P 62 does not exist t PD high-speed can be achieved.
【００２０】実際、図６の回路のトランジスタＰ61，Ｐ
62のサイズが３０μｍ、Ｎ61，Ｎ62のサイズが１５μ
ｍ、負荷容量が０．１ｐＦの場合と比較して、図１の回
路はトランジスタＰ11のサイズが２０μｍ、Ｎ11のサイ
ズが１０μｍ、Ｎ12のサイズが２μｍでｔPDが０．２５
ｎｓから０．２ｎｓへと２０％改善する。かつ、この数
値例からわかるように従来の回路以上の性能を得るため
に素子数が少なくてすむだけでなく素子サイズ自身も小
さくてすみ、さらなる面積縮小の効果が得られる。In fact, the transistors P 61 and P 61 in the circuit of FIG.
The size of 62 is 30 μm, the size of N 61 and N 62 is 15 μm
m, the load capacity as compared with the 0.1 pF, the circuit of Figure 1 the size of the transistor P 11 is 20 [mu] m, the size of the N 11 is 10 [mu] m, the size of the N 12 is the t PD at 2 [mu] m 0.25
20% improvement from ns to 0.2 ns. In addition, as can be seen from the numerical examples, in order to obtain a performance higher than that of the conventional circuit, not only the number of elements can be reduced but also the element size itself can be reduced, and the effect of further reducing the area can be obtained.
【００２１】また、従来例ＭＯＳトランジスタのゲート
容量とソース・ドレイン部の拡散容量では拡散容量の方
が大きかったが、近年の微細化技術によるゲート酸化膜
の薄膜化によるゲート容量の増大および拡散層の面積の
縮小や深さ方向の薄層化による底面・側面容量の低下に
より、ゲート容量と拡散容量がほぼ同等となってきてい
る。このため、本実施例の回路を従来例と置き換えて使
用する分には何ら問題ないだけでなく、本実施例の回路
が図２の様に、入力信号端子Ａが複数の回路で共通に接
続されている場合、図３の様にソース部をマスクデータ
上共通にすることにより前段の回路（入力信号Ａを発生
させる回路）からみた負荷を半減させることができる。Although the diffusion capacitance of the gate capacitance and the diffusion capacitance of the source / drain portion of the conventional MOS transistor is larger, the increase in the gate capacitance due to the thinning of the gate oxide film by the recent miniaturization technology and the diffusion layer The gate capacitance and the diffusion capacitance have become almost equal due to the reduction in the bottom surface and the side surface capacitance due to the reduction in the area of the device and the reduction in the thickness in the depth direction. Therefore, not only is there no problem in using the circuit of the present embodiment in place of the conventional example, but also the circuit of the present embodiment has an input signal terminal A commonly connected to a plurality of circuits as shown in FIG. In this case, the load seen from the circuit at the preceding stage (the circuit for generating the input signal A) can be reduced by half by making the source portion common to the mask data as shown in FIG.
【００２２】図４は本実施例のＮＡＮＤ回路（ＢｉＣＭ
ＯＳ構成）の１例である。この場合は入力信号端子Ａが
Ｈレベル、入力信号端子ＢがＬレベルの時のみ出力信号
端子ＯＵＴがＬレベルとなり、それ以外の時はＨレベル
を出力するという図８，９で示したＮＡＮＤ回路と同等
の回路動作を行う。FIG. 4 shows a NAND circuit (BiCM) of this embodiment.
OS configuration). In this case, the NAND circuit shown in FIGS. 8 and 9 outputs the output signal terminal OUT only when the input signal terminal A is at the H level and the input signal terminal B is at the L level, and outputs the H level otherwise. Performs the same circuit operation as.
【００２３】[0023]
【実施例２】図５は本発明の実施例２を示す回路図であ
る。Embodiment 2 FIG. 5 is a circuit diagram showing Embodiment 2 of the present invention.
【００２４】図１に示す実施例１では、入力信号端子Ａ
がＨレベル、ＢがＬレベルの時トランジスタＰ11とＮ12
が共にＯＮ状態となるため、入力信号端子Ａから低電位
側電源端子に電流が流れ、回路数が多ければパワーの増
加につながる可能性がある。また、この電流と入力信号
Ａ自身の配線抵抗とトランジスタＰ11のＯＮ状態での抵
抗成分で出力信号端子ＯＵＴのＨレベルが多少電位ドロ
ップしてしまう。In the first embodiment shown in FIG. 1, the input signal terminal A
Transistor P 11 and N 12 when but H level, B is the L level
Are both turned on, a current flows from the input signal terminal A to the low potential side power supply terminal, and if the number of circuits is large, the power may increase. Moreover, resulting in less potential drop is H level of the output signal terminal OUT in the resistance component of the ON state of the wiring resistance and the transistor P 11 of the current and the input signal A itself.
【００２５】実施例２はこういった問題を解消すべく発
明されたものであり、図１では高電位側の電源端子に接
続されていたトランジスタＮ12のゲート部を、入力信号
ＡをＣＭＯＳインバータ回路ＩＮＶ１で反転させた信号
に接続した構成となっている。[0025] Example 2 has been invented to solve the problems saying, the gate portion of the transistor N 12 which is connected to the power supply terminal of the high-potential side in Fig. 1, CMOS inverter input signal A The configuration is such that the signal is connected to the signal inverted by the circuit INV1.
【００２６】これにより、トランジスタＮ12は入力信号
ＡがＬレベルの時のみＯＮ状態となり上記電流は０とな
る。実際には実施例１に比べＩＮＶ１分だけ面積の増加
が生じるが、このインバータは小さなサイズでよく、ま
た図２の様な複数の回路に共通に入力信号Ａが接続され
ている場合にもこのインバータは１個でよいので、この
面積の増加はほとんど問題にならない。[0026] Thus, the transistor N 12 is the current in an ON state only when the input signal A is L level is 0. Actually, the area is increased by INV1 compared to the first embodiment. However, this inverter may be small in size, and this inverter can be used even when the input signal A is commonly connected to a plurality of circuits as shown in FIG. Since only one inverter is required, this increase in the area hardly causes a problem.
【００２７】[0027]
【発明の効果】以上述べてきたように、本発明は２入力
の半導体論理回路装置において入力信号の一方をＭＯＳ
トランジスタのソース部に接続することで、論理回路の
遅延時間の高速化および素子数減による占有面積の縮小
という効果を得ることができる。また、マスクデータ上
工夫することにより前段の回路からみた負荷を従来の半
分に減少させる効果も得られる。As described above, according to the present invention, in a two-input semiconductor logic circuit device, one of the input signals is MOS.
By connecting to the source portion of the transistor, the effect of increasing the delay time of the logic circuit and reducing the occupied area by reducing the number of elements can be obtained. Further, by devising the mask data, it is possible to obtain an effect of reducing the load viewed from the circuit in the preceding stage to half that of the conventional circuit.
【図１】本発明の実施例１を示す回路図、FIG. 1 is a circuit diagram showing a first embodiment of the present invention;
【図２】本発明の実施例１の使用例を示す回路図、FIG. 2 is a circuit diagram showing a usage example of the first embodiment of the present invention;
【図３】図２の回路図のマスクパタンを示す図、FIG. 3 is a view showing a mask pattern in the circuit diagram of FIG. 2;
【図４】本発明の実施例１の応用例を示す回路図、FIG. 4 is a circuit diagram showing an application example of the first embodiment of the present invention;
【図５】本発明の実施例２を示す回路図、FIG. 5 is a circuit diagram showing a second embodiment of the present invention;
【図６】従来例を示す回路図、FIG. 6 is a circuit diagram showing a conventional example;
【図７】従来例を示す回路図、FIG. 7 is a circuit diagram showing a conventional example;
【図８】従来例を示す回路図、FIG. 8 is a circuit diagram showing a conventional example,
【図９】従来例を示す回路図、FIG. 9 is a circuit diagram showing a conventional example;
【図１０】従来例を示す回路図、FIG. 10 is a circuit diagram showing a conventional example;
【図１１】従来例を示す回路図、FIG. 11 is a circuit diagram showing a conventional example.
【図１２】従来例を示す回路図、FIG. 12 is a circuit diagram showing a conventional example.
【図１３】従来例を示す回路図。FIG. 13 is a circuit diagram showing a conventional example.
Ａ，Ｂ，Ｂ１，Ｂ２ 入力信号端子 ＯＵＴ，ＯＵＴ１，ＯＵＴ２ 出力信号端子 Ｐ11，Ｐ61，Ｐ62 Ｐ型ＭＯＳトランジスタ Ｎ11，Ｎ12，Ｎ61，Ｎ62 Ｎ型ＭＯＳトランジスタ ＩＮＶ１ インバータ回路A, B, B1, B2 input signal terminal OUT, OUT1, OUT2 output signal terminal P 11, P 61, P 62 P -type MOS transistor N 11, N 12, N 61 , N 62 N -type MOS transistor INV1 inverter circuit
Claims (4)
される第１および第２の入力端子と、ソースが前記第１
の入力端子に接続され、ゲートが前記第２の入力端子に
接続され、ドレインが出力端子に接続された第１の極性
の第１のＭＯＳトランジスタと、ゲートが前記第２の入
力端子に接続され、ソースが第１の電源に接続され、ド
レインが前記出力端子に接続された第２の極性の第２の
ＭＯＳトランジスタと、ドレインおよびソースが前記第
２のトランジスタのドレインおよびソースにそれぞれ接
続された第２の極性の第３のトランジスタと、少なくと
も前記第１および前記第２のＭＯＳトランジスタが両方
とも非導通の時に前記第３のＭＯＳトランジスタを導通
せしめる手段とを有する半導体論理回路装置。A first and a second input terminal to which a first and a second input signal are respectively inputted; and a source connected to the first and the second input signals.
A first MOS transistor having a first polarity, a gate connected to the second input terminal, a drain connected to the output terminal, and a gate connected to the second input terminal. A source is connected to the first power supply, a drain is connected to the output terminal, a second MOS transistor of a second polarity, and a drain and a source are connected to a drain and a source of the second transistor, respectively. a third transistor of a second polarity, the semiconductor logic circuit device having a means for allowed to conduct the third MOS transistor when at least both the first and the second MOS transistor is non-conduction.
される第１および第２の入力端子と、ソースが前記第１
の入力端子に接続され、ゲートが前記第２の入力端子に
接続された第１の極性の第１のＭＯＳトランジスタと、
ソースが第１の電源に接続され、ゲートが前記第２の入
力端子に接続され、ドレインが前記第１のＭＯＳトラン
ジスタのドレインに接続された第２の極性の第２のＭＯ
Ｓトランジスタと、ソースが前記第１の電源に接続さ
れ、ドレインが前記第１のＭＯＳトランジスタのドレイ
ンに接続された第２の極性の第３のＭＯＳトランジスタ
と、ソースが前記第１の入力端子に接続され、ゲートが
前記第２の入力端子に接続され、ドレインが出力端子に
接続された第１の極性の第４のＭＯＳトランジスタと、
エミッタが前記出力端子に接続され、コレクタが前記第
１の電源に接続され、ベースが前記第１のＭＯＳトラン
ジスタのドレインに接続されたバイポーラトランジスタ
と、少なくとも前記第１および前記第２のＭＯＳトラン
ジスタが両方とも非導通の時に前記第３のＭＯＳトラン
ジスタを導通せしめる手段とを有する半導体論理回路装
置。2. A first and second input terminal to which first and second input signals are respectively input, and a source connected to the first and second input signals.
A first MOS transistor of a first polarity, the gate of which is connected to the input terminal of
A second MO of a second polarity having a source connected to the first power supply, a gate connected to the second input terminal, and a drain connected to the drain of the first MOS transistor.
And S transistor, a source connected to said first power supply, and a second third MOS transistor polarity having a drain connected to a drain of said first MOS transistor, the source of the first input terminal A fourth MOS transistor of a first polarity, the first MOS transistor being connected to the second input terminal, the drain being connected to the output terminal,
A bipolar transistor having an emitter connected to the output terminal, a collector connected to the first power supply, and a base connected to the drain of the first MOS transistor, and at least the first and second MOS transistors both semiconductor logic circuit device having a means for allowed to conduct the third MOS transistor when a non-conduction.
スタのゲートを第２の電源に接続して前記第３のＭＯＳ
トランジスタを導通状態にする請求項１または２記載の
半導体論理回路装置。3. The device according to claim 3, wherein the means connects the gate of the third MOS transistor to a second power supply and connects the third MOS transistor to the third MOS transistor.
3. The semiconductor logic circuit device according to claim 1, wherein the transistor is turned on.
号を前記第２のＭＯＳトランジスタのゲートに印加する
インバータでなる請求項１または２記載の半導体論理回
路装置。4. The semiconductor logic circuit device according to claim 1, wherein said means is an inverter that applies an inverted signal of said first input signal to a gate of said second MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5096358A JP2590681B2 (en) | 1993-04-23 | 1993-04-23 | Semiconductor logic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5096358A JP2590681B2 (en) | 1993-04-23 | 1993-04-23 | Semiconductor logic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06311022A JPH06311022A (en) | 1994-11-04 |
| JP2590681B2 true JP2590681B2 (en) | 1997-03-12 |
Family
ID=14162776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5096358A Expired - Fee Related JP2590681B2 (en) | 1993-04-23 | 1993-04-23 | Semiconductor logic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2590681B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7649800B2 (en) | 2004-12-22 | 2010-01-19 | Nec Electronics Corporation | Logic circuit and word-driver circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0495102B1 (en) * | 1990-08-07 | 1996-01-31 | Mitsubishi Materials Corporation | Surge-absorbing element for protection against overvoltage and overcurrent |
| JP2011234157A (en) * | 2010-04-28 | 2011-11-17 | Elpida Memory Inc | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6362412A (en) * | 1986-09-02 | 1988-03-18 | Mitsubishi Electric Corp | Logical gate circuit |
| JPH01144724A (en) * | 1987-11-30 | 1989-06-07 | Nec Corp | Logical operating circuit |
| JPH02271714A (en) * | 1989-04-12 | 1990-11-06 | Nec Corp | Logic circuit |
-
1993
- 1993-04-23 JP JP5096358A patent/JP2590681B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7649800B2 (en) | 2004-12-22 | 2010-01-19 | Nec Electronics Corporation | Logic circuit and word-driver circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06311022A (en) | 1994-11-04 |
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