JP2580667B2 - Method for manufacturing multilayer printed wiring board - Google Patents
Method for manufacturing multilayer printed wiring boardInfo
- Publication number
- JP2580667B2 JP2580667B2 JP411888A JP411888A JP2580667B2 JP 2580667 B2 JP2580667 B2 JP 2580667B2 JP 411888 A JP411888 A JP 411888A JP 411888 A JP411888 A JP 411888A JP 2580667 B2 JP2580667 B2 JP 2580667B2
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- forming
- stainless steel
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層印刷配線板の製造方法に関し、特にバイ
アホールを有する多層印刷配線板の製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a multilayer printed wiring board having via holes.
従来、多層印刷板の製造方法としては、あらかじめ回
路形成が施された片面印刷配線板、あるいは、両面印刷
配線板を複数個用意し、これをプリプレグを介し、か
つ、最外層には銅板あるいは銅張積層板を用い、積層す
ることにより積層板を形成し、このようにして得られた
積層板を穴あけ後スルーホールめっきを施し、最外層の
回路形成を行なうことにより多層印刷配線板を得てい
た。Conventionally, as a method of manufacturing a multilayer printed board, a single-sided printed wiring board or a double-sided printed wiring board on which a circuit has been formed in advance is prepared, and a plurality of these are passed through a prepreg, and the outermost layer is made of a copper plate or copper. A laminated printed circuit board is obtained by forming a laminated board by laminating using a laminated laminated board, forming a hole in the thus obtained laminated board, performing through-hole plating, and forming a circuit of the outermost layer. Was.
しかし、上述した従来の多層印刷配線板の製造方法
は、内層として用いる片面印刷配線板あるいは両面印刷
配線板が薄いため、その作製工程で、例えば、現像装
置，エッチング装置，剥離装置等で搬送が困難となるば
かりでなく、剛性がないため折れ易く、基板の寸法変化
による回路位置精度の悪化等の問題点を有するばかりで
なく、積層時の内層の寸法変化や内層回路相互の位置ず
れ等の問題点を有していた。However, in the conventional method for manufacturing a multilayer printed wiring board described above, since the single-sided printed wiring board or the double-sided printed wiring board used as the inner layer is thin, it is transported in a manufacturing process, for example, by a developing device, an etching device, a peeling device, or the like. Not only is it difficult, it is easy to break due to lack of rigidity, and not only has problems such as deterioration of circuit position accuracy due to dimensional change of the substrate, but also dimensional change of the inner layer during lamination and misalignment between the inner layer circuits. Had problems.
本発明の目的は、取り扱いが容易で、回路位置精度の
高い多層印刷配線板の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board that is easy to handle and has high circuit position accuracy.
本発明の多層印刷配線板の製造方法は、ステンレス板
表面に第１の導電層を形成する工程と、前記第１の導電
層表面のバイアホール形成部を残して絶縁層を形成する
工程と、前記バイアホール形成部を導電体で充填しバイ
アホールを形成する工程と、前記絶縁層表面を粗化処理
する工程と、前記絶縁層表面及び前記バイアホール上に
第２の導電層を形成する工程と、前記第２の導電層をエ
ッチングし導電回路を形成する工程と、前記導電回路が
形成された２組のステンレス板をあらかじめ回路が形成
された印刷配線板およびプリプレグを介し前記導電回路
が形成された面を内側にして積層した後前記ステンレス
板を取り除き積層板を形成する工程と、前記積層板に貫
通孔を設けスルーホールめっきをした後エンチッグによ
り表面回路を形成する工程とを含んで構成されている。The method for manufacturing a multilayer printed wiring board according to the present invention includes a step of forming a first conductive layer on the surface of a stainless steel plate, and a step of forming an insulating layer while leaving a via hole forming portion on the surface of the first conductive layer; Filling the via hole forming portion with a conductor to form a via hole; roughening the insulating layer surface; and forming a second conductive layer on the insulating layer surface and the via hole. Forming a conductive circuit by etching the second conductive layer; and forming the conductive circuit on the two sets of stainless steel plates on which the conductive circuit is formed via a printed wiring board and a prepreg in which a circuit is formed in advance. Forming a laminated circuit by removing the stainless steel plate and forming a laminated plate with the formed surface facing inward, forming a through hole in the laminated plate and plating through holes, and then forming a surface circuit by etching. It is configured to include a step.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｌ）は本発明の一実施例を説明する
ための工程順に示した多層印刷配線板の断面図である。1 (a) to 1 (l) are cross-sectional views of a multilayer printed wiring board shown in the order of steps for explaining one embodiment of the present invention.
まず、第１図（ａ）に示すように、ステンレス板１を
用意し、第１図（ｂ）に示すように、裏面にあらかじめ
レジストフィルムをラミネートし、第１のレジスト層２
を形成した後、ステンレス板１に電気銅めっきを施し、
ステンレス板１の表面に第１の導電層３を形成した。First, as shown in FIG. 1 (a), a stainless steel plate 1 is prepared, and as shown in FIG. 1 (b), a resist film is preliminarily laminated on the back surface, and a first resist layer 2 is formed.
After forming, the stainless steel plate 1 is subjected to electrolytic copper plating,
The first conductive layer 3 was formed on the surface of the stainless steel plate 1.
次に、第１図（ｃ）に示すように、ステンレス板１の
表面にポリイミド樹脂をコーティングして絶縁層４を形
成し、更に、絶縁層４の表面にレジストフィルムをラミ
ネートし、露光，現像することにより、バイアホール６
形成部以外の部分に第１のレジスト層２を形成した。Next, as shown in FIG. 1 (c), the surface of the stainless steel plate 1 is coated with a polyimide resin to form an insulating layer 4, and a resist film is further laminated on the surface of the insulating layer 4, and exposed and developed. By doing, via hole 6
The first resist layer 2 was formed in a portion other than the formation portion.
次に、第１図（ｄ）に示すように、ステンレス板１を
水酸化ナトリウム水溶液にスプレー浸漬し、絶縁層４の
バイアホール形成部をエッチング除去し、絶縁層パター
ン５を形成した。Next, as shown in FIG. 1 (d), the stainless plate 1 was spray-immersed in an aqueous sodium hydroxide solution, and the via-hole forming portion of the insulating layer 4 was removed by etching to form an insulating layer pattern 5.
次に、第１図（ｅ）に示すように、ステンレス板１
に、電気銅めっきを施し、バイアホール形成部に銅めっ
きを施した後、導電体を充填し、バイアホール６を形成
した。Next, as shown in FIG.
Was subjected to electrolytic copper plating, and copper plating was applied to the via-hole forming portion, and then filled with a conductor to form a via hole 6.
次に、第１図（ｆ）に示すように、第１のレジスト層
２を除去した。Next, as shown in FIG. 1 (f), the first resist layer 2 was removed.
次に、第１図（ｇ）に示すように、ステンレス板１を
触媒液に浸漬し、活性化処理を行なった後、無電解銅め
っきを行ない、更に、電気銅めっきを施し、第２の導電
層７を形成した。Next, as shown in FIG. 1 (g), after immersing the stainless steel plate 1 in a catalyst solution and performing an activation treatment, electroless copper plating is performed, and further, electrolytic copper plating is performed. The conductive layer 7 was formed.
次に、第１図（ｈ）に示すように、ステンレス板１の
表面にドライフィルムをラミネートした後、露光，現像
し、第２の導電層７の上に第２のレジスト層８を形成し
た。Next, as shown in FIG. 1 (h), after a dry film was laminated on the surface of the stainless steel plate 1, it was exposed and developed to form a second resist layer 8 on the second conductive layer 7. .
次に第１図（ｉ）に示すように、ステンレス板１をエ
ッチング液にスプレー浸漬し、第２の導電層をエッチン
グすることにより、導電回路９を形成した。Next, as shown in FIG. 1 (i), the stainless steel plate 1 was spray-immersed in an etching solution and the second conductive layer was etched to form a conductive circuit 9.
次に、第１図（ｊ）に示すように、このようにして得
られた２組のステンレス板１の導電回路９を持つ面を内
側にし、あらかじめ、両面に回路形成した印刷配線板10
を複数のプリプレグ11を介し配置した後、ステンレス板
1,印刷配線板10,およびプリプレグ11にあらかじめ、積
層位置合わせ用のパイロット穴を設けておき、ピンによ
り位置決めを行ない、加熱，加圧することにより積層
し、積層板を形成した。Next, as shown in FIG. 1 (j), the two surfaces of the two stainless steel plates 1 thus obtained with the conductive circuit 9 on the inside are turned inside, and the printed wiring board 10 with a circuit formed on both surfaces in advance is prepared.
After arranging through a plurality of prepregs 11, stainless steel plate
1. A printed wiring board 10 and a prepreg 11 were previously provided with pilot holes for stacking alignment, positioned by pins, and stacked by heating and pressing to form a stacked board.
次に、ステンレス板１を除去した後、ドリル穴あけに
より、スルーホール形成部に貫通孔12を形成した。Next, after the stainless steel plate 1 was removed, a through hole 12 was formed in the through hole forming portion by drilling.
次に、第１図（ｌ）に示すように、活性化処理，電電
解銅めっきおよび電気銅めっきを施し、パネルめっきを
行ない、スルーホール13を形成し、第１の導電層２を印
刷−エッチングし、表面回路14を形成することにより、
多層印刷配線板20を得た。Next, as shown in FIG. 1 (l), activation treatment, electro-electrolytic copper plating and electrolytic copper plating are performed, panel plating is performed, through holes 13 are formed, and the first conductive layer 2 is printed. By etching and forming the surface circuit 14,
A multilayer printed wiring board 20 was obtained.
なお、第１の導電層２と第２の導電層６の形成は、電
気銅めっきを使用した実施例について説明したが、電気
銅めっきを使用せずに無電解等めっきのみで形成するこ
とも出来、上述の実施例と同じ効果が得られた。Although the formation of the first conductive layer 2 and the second conductive layer 6 has been described with reference to the embodiment using the copper electroplating, the first conductive layer 2 and the second conductive layer 6 may be formed only by the electroless plating without using the copper electroplating. As a result, the same effects as in the above-described embodiment were obtained.
以上説明したように本発明は、ステンレス板を多層印
刷配線板の製造に用いることにより、多層印刷配線板の
各層の回路パターン，バイアホールおよびスルーホール
の相互位置精度およびパターン伸縮，歪等を大幅に減少
させることができる効果がある。As described above, the present invention significantly reduces the circuit pattern of each layer of the multilayer printed wiring board, the mutual positional accuracy of via holes and through holes, and the pattern expansion, contraction, distortion, and the like by using the stainless steel plate for manufacturing the multilayer printed wiring board. There is an effect that can be reduced.
また、ステンレス板を支持体とするので、工程中の取
り扱いが容易となり、多層印刷配線板を歩留り良く製造
することができ、また、ステンレス板は積層の際の当て
板を兼ね、しかも、繰り返し使用できるので製造コスト
を減少させることができるという効果もある。In addition, since the stainless steel plate is used as a support, handling during the process becomes easy, a multilayer printed wiring board can be manufactured with good yield, and the stainless steel plate also serves as a backing plate for lamination and is used repeatedly. Therefore, there is also an effect that the manufacturing cost can be reduced.
第１図（ａ）〜（ｌ）は本発明の一実施例を説明するた
めの工程順に示した多層印刷配線板の断面図である。 １……ステンレス板、２……第１のレジスト層、３……
第１の導電層、４……絶縁層、５……絶縁層パターン、
６……バイアホール、７……第２の導電層、８……第２
のレジスト層、９……導電回路、10……印刷配線板、11
……プリプレグ、12……貫通孔、13……スルーホール、
14……表面回路、20……多層印刷配線板。1 (a) to 1 (l) are cross-sectional views of a multilayer printed wiring board shown in the order of steps for explaining one embodiment of the present invention. 1 ... Stainless steel plate, 2 ... First resist layer, 3 ...
A first conductive layer, 4 ... an insulating layer, 5 ... an insulating layer pattern,
6 via hole, 7 second conductive layer, 8 second
Resist layer, 9: conductive circuit, 10: printed wiring board, 11
... prepreg, 12 ... through-hole, 13 ... through-hole,
14 ... Surface circuit, 20 ... Multilayer printed wiring board.
Claims (1)
る工程と、前記第１の導電層表面のバイアホール形成部
を残して絶縁層を形成する工程と、前記バイアホール形
成部を導電体で充填しバイアホールを形成する工程と、
前記絶縁層表面を粗化処理する工程と、前記絶縁層表面
及び前記バイアホール上に第２の導電層を形成する工程
と、前記第２の導電層をエッチングし導電回路を形成す
る工程と、前記導電回路が形成された２組のステンレス
板をあらかじめ回路が形成された印刷配線板およびプリ
プレグを介し前記導電回路が形成された面を内側にして
積層した後前記ステンレス板を取り除き積層板を形成す
る工程と、前記積層板に貫通孔を設けスルーホールめっ
きをした後エンチッグにより表面回路を形成する工程と
を含むことを特徴とする多層印刷配線板の製造方法。A step of forming a first conductive layer on a surface of a stainless steel plate; a step of forming an insulating layer while leaving a via hole forming portion on the surface of the first conductive layer; Forming a via hole by filling with a body,
A step of roughening the surface of the insulating layer, a step of forming a second conductive layer on the surface of the insulating layer and the via hole, and a step of forming a conductive circuit by etching the second conductive layer; Two sets of stainless steel plates on which the conductive circuits are formed are laminated with the surface on which the conductive circuits are formed inside through a printed wiring board and a prepreg on which circuits are formed in advance, and then the stainless steel plates are removed to form a laminate. And a step of forming a surface circuit by etching after providing a through hole in the laminated board and plating the through hole, and a method of manufacturing a multilayer printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP411888A JP2580667B2 (en) | 1988-01-11 | 1988-01-11 | Method for manufacturing multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP411888A JP2580667B2 (en) | 1988-01-11 | 1988-01-11 | Method for manufacturing multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01181599A JPH01181599A (en) | 1989-07-19 |
| JP2580667B2 true JP2580667B2 (en) | 1997-02-12 |
Family
ID=11575872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP411888A Expired - Lifetime JP2580667B2 (en) | 1988-01-11 | 1988-01-11 | Method for manufacturing multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2580667B2 (en) |
-
1988
- 1988-01-11 JP JP411888A patent/JP2580667B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01181599A (en) | 1989-07-19 |
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