JP2576526B2 - I / O signal monitoring circuit - Google Patents
I / O signal monitoring circuitInfo
- Publication number
- JP2576526B2 JP2576526B2 JP22154587A JP22154587A JP2576526B2 JP 2576526 B2 JP2576526 B2 JP 2576526B2 JP 22154587 A JP22154587 A JP 22154587A JP 22154587 A JP22154587 A JP 22154587A JP 2576526 B2 JP2576526 B2 JP 2576526B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- signal
- output
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はデイジタル通信方式に関し、特に端局中継装
置の入出力監視回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication system, and more particularly to an input / output monitoring circuit of a terminal repeater.
第２図は従来の入出力監視回路を符号化回路に用いた
例を示すブロック図である。FIG. 2 is a block diagram showing an example in which a conventional input / output monitoring circuit is used for an encoding circuit.
第２図において、入力信号８は分配回路９により２つ
に分けられ１つはメモリ回路10へ、もう１つは入出力監
視回路14へ送られる。メモリ回路10に書込まれた信号は
符号化回路11に周期した速度で読出され、符号化回路11
で符号変換を受けて分配回路12へ送られる。分配回路12
では信号を出力信号13と入出力監視回路14に分ける。入
出力監視回路14では入力信号を分岐した信号１と出力信
号を分岐した信号７との間の監視を行なう。In FIG. 2, an input signal 8 is divided into two by a distribution circuit 9 and one is sent to a memory circuit 10 and the other is sent to an input / output monitoring circuit 14. The signal written in the memory circuit 10 is read out at a speed that is periodic to the encoding circuit 11, and
, And is sent to the distribution circuit 12. Distribution circuit 12
Then, the signal is divided into an output signal 13 and an input / output monitoring circuit 14. The input / output monitoring circuit 14 monitors between the signal 1 obtained by branching the input signal and the signal 7 obtained by branching the output signal.
入出力監視回路14は第３図に示す構成となっている。
すなわち、出力信号を分岐した信号７は複合化回路６に
より複合化されメモリ回路５に書き込まれる。入力信号
を分岐した信号１は可変長シフトレジスタ３を通過後、
ビット誤の検出回路４へ送られる。メモリ回路５に書き
込まれた信号は信号１のクロック速度で読み出され同期
化されてビット誤の検出回路４へ送られる。ビット誤の
検出回路４へ入力される２つの信号の遅延時間が等しく
なるように可変長シフトレジスタ３の長さが調整されて
ビット誤の検出回路は誤り監視をする。The input / output monitoring circuit 14 has the configuration shown in FIG.
That is, the signal 7 obtained by branching the output signal is compounded by the compounding circuit 6 and written into the memory circuit 5. After the signal 1 obtained by branching the input signal passes through the variable length shift register 3,
It is sent to the bit error detection circuit 4. The signal written in the memory circuit 5 is read out at the clock speed of the signal 1, synchronized, and sent to the bit error detection circuit 4. The length of the variable length shift register 3 is adjusted so that the delay times of the two signals input to the bit error detection circuit 4 become equal, and the bit error detection circuit monitors errors.
上述した従来の入出力監視装置は、入力信号１のクロ
ックで可変長シフトレジスタ３、ビット誤り検出回路
４、メモリ回路５が動作するので、入力信号１にジッタ
が加わるとメモリ回路５にかかるジッタは複合化回路６
の出力ジッタと入力信号１のジッタを加えたものとな
る。入力信号のジッタによりメモリ回路10よりも先に入
出力監視回路中のメモリ回路５が誤りを生じると、主信
号回路のメモリ回路10が誤ったのか入出力監視回路のメ
モリ回路５の誤りか区別がつかなくなるため、入力信号
１に加えうる最大のジッタを入力してしてもメモリ回路
５が誤らないようにメモリのビット数を大きくとらなけ
ればならないという欠点がある。In the conventional input / output monitoring device described above, the variable-length shift register 3, the bit error detection circuit 4, and the memory circuit 5 operate with the clock of the input signal 1, so that when the input signal 1 is subjected to jitter, the jitter applied to the memory circuit 5 Is the composite circuit 6
And the jitter of the input signal 1 are added. If an error occurs in the memory circuit 5 in the input / output monitoring circuit before the memory circuit 10 due to the jitter of the input signal, it is determined whether the memory circuit 10 in the main signal circuit is wrong or the memory circuit 5 in the input / output monitoring circuit is wrong. Therefore, there is a disadvantage that the number of bits of the memory must be increased so that the memory circuit 5 does not make an error even when the maximum jitter that can be added to the input signal 1 is input.
本発明によれば、入力信号を符号変換して出力する信
号系に対して、出力信号を複合化してメモリ回路に書き
込み、メモリ回路の読出しを入力信号に同期さたて行な
って入力信号とメモリ回路の読出し信号間の誤り検出を
行なう入出力監視回路において、入力信号に対するジッ
タ抑圧回路を含むことを特徴とする入出力監視回路が得
られる。According to the present invention, for a signal system for transcoding an input signal and outputting the decoded signal, the output signal is compounded and written into a memory circuit, and the memory circuit is read out in synchronization with the input signal, and the input signal and the memory are read out. According to the present invention, there is provided an input / output monitoring circuit for detecting an error between read signals of a circuit, the input / output monitoring circuit including a jitter suppression circuit for an input signal.
次に本発明の実施例について図面を参照しと説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の実施例のブロック図である。 FIG. 1 is a block diagram of an embodiment of the present invention.
図において、１は入力信号で、ジッタ抑制回路２は入
力信号１の中のジッタを抑圧して可変長シフトレジスタ
３へデータ・クロックを出力する。入力信号７は複合化
回路６へ供給され、変換を受けた後、メモリ回路５に書
込まれる。メモリ回路５はエラスティックストアとなっ
ていて、ジッタを抑圧されたクロックで順次読出され、
ビット誤り検出回路４へ出力される。可変長シフトレジ
スタ３に書込まれたデータは、ビット誤り検出回路４の
制御により可変長シフトレジスタ３からビット誤り検出
回路４に入力するデータとメモリ回路５から入力するデ
ータの遅延時間が等しくなるように、任意の時間の遅延
を受けて出力される。ビット誤の検出回路４は２つの入
力データをbit−by−bitで比較して誤り検出をする。In the figure, reference numeral 1 denotes an input signal, and a jitter suppression circuit 2 suppresses jitter in the input signal 1 and outputs a data clock to a variable length shift register 3. The input signal 7 is supplied to the decoding circuit 6, converted, and written into the memory circuit 5. The memory circuit 5 is an elastic store, and is sequentially read by a clock with jitter suppressed,
Output to the bit error detection circuit 4. The data written in the variable length shift register 3 has the same delay time as the data input from the variable length shift register 3 to the bit error detection circuit 4 and the data input from the memory circuit 5 under the control of the bit error detection circuit 4. As described above, the data is output with an arbitrary time delay. The bit error detection circuit 4 compares two pieces of input data on a bit-by-bit basis to detect an error.
以上説明したように本発明は、入力信号中のジッタを
抑圧したクロックでメモリ回路のデータを読出すことに
より、メモリ回路に加わるジッタを低減してメモリの所
要ビット数を下げる効果がある。As described above, the present invention has the effect of reducing the jitter applied to the memory circuit and reducing the required number of bits of the memory by reading the data of the memory circuit with the clock in which the jitter in the input signal is suppressed.
第１図は本発明の実施例を示すブロック図、第２図は従
来の入出力監視回路を備えた符号化回路のブロック図、
第３図は従来の入出力監視回路のブロック図である。 １……入出力監視回路入力信号、２……ジッタ抑圧回
路、３……可変長シフトレジスタ、４……ビット誤り検
出回路、５……メモリ回路、６……複合化回路、７……
入出力監視回路入力信号、８……入力信号、９……分配
回路、10……メモリ回路、11……符号化回路、12……分
配回路、13……出力信号、14……入出力監視回路、FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of an encoding circuit having a conventional input / output monitoring circuit,
FIG. 3 is a block diagram of a conventional input / output monitoring circuit. DESCRIPTION OF SYMBOLS 1 ... Input / output monitoring circuit input signal, 2 ... Jitter suppression circuit, 3 ... Variable length shift register, 4 ... Bit error detection circuit, 5 ... Memory circuit, 6 ... Composite circuit, 7 ...
Input / output monitoring circuit input signal, 8: input signal, 9: distribution circuit, 10: memory circuit, 11: encoding circuit, 12: distribution circuit, 13: output signal, 14: input / output monitoring circuit,
Claims (1)
対して、出力信号を複合化してメモリ回路に書き込み前
記メモリ回路の読出しを前記入力信号に同期させて行な
って前記入力信号と前記メモリ回路の読出し信号間の誤
り検出を行なう入出力監視回路において、前記入力信号
に対するジッタ抑圧回路を含むことを特徴とする入出力
監視回路。An output signal is converted to a signal system for code conversion, and the output signal is compounded and written to a memory circuit. The memory circuit is read out in synchronism with the input signal so that the input signal and the input signal are output. An input / output monitoring circuit for detecting an error between read signals of a memory circuit, the input / output monitoring circuit including a jitter suppression circuit for the input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22154587A JP2576526B2 (en) | 1987-09-03 | 1987-09-03 | I / O signal monitoring circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22154587A JP2576526B2 (en) | 1987-09-03 | 1987-09-03 | I / O signal monitoring circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6464431A JPS6464431A (en) | 1989-03-10 |
| JP2576526B2 true JP2576526B2 (en) | 1997-01-29 |
Family
ID=16768401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22154587A Expired - Lifetime JP2576526B2 (en) | 1987-09-03 | 1987-09-03 | I / O signal monitoring circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2576526B2 (en) |
-
1987
- 1987-09-03 JP JP22154587A patent/JP2576526B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6464431A (en) | 1989-03-10 |
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