JP2561039B2 - Method of connecting semiconductor chip and circuit board - Google Patents
Method of connecting semiconductor chip and circuit boardInfo
- Publication number
- JP2561039B2 JP2561039B2 JP6287722A JP28772294A JP2561039B2 JP 2561039 B2 JP2561039 B2 JP 2561039B2 JP 6287722 A JP6287722 A JP 6287722A JP 28772294 A JP28772294 A JP 28772294A JP 2561039 B2 JP2561039 B2 JP 2561039B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor chip
- plating
- chip
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
Landscapes
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体チップの電極およ
び回路基板の電極の接続方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting electrodes of a semiconductor chip and electrodes of a circuit board.
【０００２】[0002]
【従来の技術】半導体チップの電極と回路基板の電極と
の接続に、無電解メッキ法を用いた従来の半導体チップ
の実装構造の接続方法は、例えば、特開平２−６６９５
３号公報に開示されている。2. Description of the Related Art A conventional method of connecting a semiconductor chip mounting structure using an electroless plating method for connecting an electrode of a semiconductor chip and an electrode of a circuit board is disclosed in, for example, Japanese Patent Laid-Open No. 2-6695.
It is disclosed in Japanese Patent No.
【０００３】図７（ａ）を参照すると、従来の半導体チ
ップの実装構造の接続方法は、半導体素子７１上にチタ
ン，銅，金あるいはチタン，白金，金、あるいは、チタ
ン，パラジウム，金等の金属の組み合わせでスパッタ，
メッキ等を行うことによりマイクロバンプ７２を形成
し、それ以外の領域には、ポリイミド等の有機膜により
第１絶縁層７３を形成する。また回路基板７４上にはチ
タン，銅，あるいはニッケル等のメタライズを行い基板
電極７５を形成し、その他の領域にポリイミド等の有機
膜により第２絶縁層７６を形成する。Referring to FIG. 7 (a), a conventional method for connecting a semiconductor chip mounting structure is such that titanium, copper, gold or titanium, platinum, gold, titanium, palladium, gold or the like is formed on a semiconductor element 71. Sputtering with a combination of metals,
The micro bumps 72 are formed by performing plating or the like, and the first insulating layer 73 is formed of an organic film such as polyimide in other regions. Further, on the circuit board 74, metallization of titanium, copper, nickel or the like is performed to form a board electrode 75, and a second insulating layer 76 is formed in the other region by an organic film such as polyimide.
【０００４】次に、半導体素子７１と回路基板７４のマ
イクロバンプ７２および基板電極７５を除く一部の領域
に光硬化性樹脂を滴下し、樹脂層７７を形成する。Next, a photocurable resin is dropped onto a part of the semiconductor element 71 and the circuit board 74 except the micro bumps 72 and the substrate electrodes 75 to form a resin layer 77.
【０００５】次に、半導体素子７１と回路基板７４とを
後でメッキを行うに十分な空間を挟んでアライメントを
行ない、アライメント完了後紫外線を照射し、半導体素
子７１と回路基板７４とを接着する構成である。Next, the semiconductor element 71 and the circuit board 74 are aligned with each other with a space sufficient for plating later, and after the alignment is completed, ultraviolet rays are irradiated to bond the semiconductor element 71 and the circuit board 74. It is a composition.
【０００６】次に、図７（ｂ）を参照すると、この接続
方法は、半導体素子７１および回路基板７４の両者をニ
ッケルメッキ液中、あるいは金メッキ液中等に浸し無電
解メッキを行い、ニッケルあるいは金を成分とする接続
電極７８を形成する。この接続電極７８によりマイクロ
バンプ７２と基板電極７５との電気的接続が行われる。Next, referring to FIG. 7B, in this connection method, both the semiconductor element 71 and the circuit board 74 are dipped in a nickel plating solution or a gold plating solution to perform electroless plating, and nickel or gold is used. Forming a connection electrode 78 containing The connection electrodes 78 electrically connect the micro bumps 72 to the substrate electrodes 75.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、この従
来の無電解メッキ法を用いた半導体チップの電極と回路
基板の電極との接続方法は次のような問題点があった。However, the conventional method of connecting the electrode of the semiconductor chip and the electrode of the circuit board using the electroless plating method has the following problems.
【０００８】まず、第一に、半導体チップの位置決め、
支持等に光硬化性樹脂が用いられているため、硬化時間
分の位置決め、支持装置の停止が必要であり、装置のイ
ンデックスがおちる。First, the positioning of the semiconductor chip,
Since the photo-curable resin is used for supporting and the like, positioning for the curing time and stopping of the supporting device are required, and the index of the device falls.
【０００９】また、半導体チップと回路基板との間隔を
高い精度で確保するためには、位置決め装置および支持
装置のそれぞれで保持した状態の下で紫外線を照射して
光硬化性樹脂を硬化させなければならない。Further, in order to secure the distance between the semiconductor chip and the circuit board with high accuracy, it is necessary to irradiate the photocurable resin with ultraviolet rays while holding it by the positioning device and the supporting device. I have to.
【００１０】さらにまた、半導体チップ直下に回った光
硬化性樹脂，あるいは半導体チップの搭載場所，他部品
との関係で紫外線照射の影となった光硬化性樹脂は未硬
化，半硬化の部分が必ず発生する。そして、光硬化性樹
脂が未硬化，半硬化の状態で無電解メッキ液中に入った
場合、液中に溶解し、無電解メッキ液中の有機物，不純
物濃度等を高め、液を使用不能としてしまう。Furthermore, the photo-curable resin that has struck just below the semiconductor chip, or the photo-curable resin that has been shaded by ultraviolet irradiation due to the mounting location of the semiconductor chip and the relationship with other parts, has uncured and semi-cured parts. Must occur. When the photo-curable resin enters the electroless plating solution in an uncured or semi-cured state, it dissolves in the solution and increases the concentration of organic substances and impurities in the electroless plating solution, rendering the solution unusable. I will end up.
【００１１】また、有機物，不純物濃度等が高い状態で
メッキを行っても良好なメッキは得られない。無電解メ
ッキ完了後、洗浄乾燥を行っても、光硬化性樹脂の未硬
化，半硬化部分には、メッキ液残渣が残る。メッキ液残
渣中には半導体チップに有害である、Ｋ，Ｓ，Ｃｌ，Ｎ
ａ等が含まれているため、半導体装置の信頼性に悪影響
をおよぼす。Further, even if the plating is carried out in a state where the concentration of organic substances and impurities is high, good plating cannot be obtained. Even after washing and drying after completion of electroless plating, the plating solution residue remains on the uncured and semi-cured portions of the photocurable resin. K, S, Cl, N, which are harmful to semiconductor chips, remain in the plating solution residue.
Since a and the like are included, the reliability of the semiconductor device is adversely affected.
【００１２】第二に、半導体チップおよび回路基板のメ
ッキ不要部が絶縁物で被覆されていないため、半導体チ
ップの材質は一般に半導体であるために、メッキ不要部
（主に半導体チップの裏面，端面）がメッキされてしま
い、回路のショートが発生する。回路基板の材質に絶縁
物を使用している場合は問題ないが、シリコン回路基板
については、やはり半導体であるためにメッキ不要部
（主に回路基板の裏面，端面）がメッキされてしまい、
回路のショートが発生する。また、メッキ不要部に形成
されたメッキ薄膜を完全に除去することは非常に難し
い。Secondly, since the non-plating portions of the semiconductor chip and the circuit board are not covered with an insulating material, the material of the semiconductor chip is generally a semiconductor, and thus the non-plating portions (mainly the back surface and end surface of the semiconductor chip). ) Is plated, causing a short circuit. There is no problem if an insulating material is used as the material of the circuit board, but since the silicon circuit board is also a semiconductor, unnecessary parts (mainly the back surface and end surface of the circuit board) are plated,
A short circuit occurs. Further, it is very difficult to completely remove the plating thin film formed on the plating unnecessary portion.
【００１３】[0013]
【課題を解決するための手段】本発明の半導体チップお
よび回路基板の接続方法は、半導体チップの電極および
回路基板の電極の接続を無電解メッキ法を用いた半導体
チップおよび回路基板の接続方法において、前記半導体
チップの電極と前記回路基板の電極との位置決め工程お
よび支持工程にメッキレジストを使用し、前記半導体チ
ップの電極と前記回路基盤との接続が完了した後前記メ
ッキレジストを除去する工程を含む構成である。A method of connecting a semiconductor chip and a circuit board according to the present invention relates to a method of connecting a semiconductor chip and a circuit board using an electroless plating method for connecting an electrode of the semiconductor chip and an electrode of the circuit board. A step of using a plating resist in the step of positioning and supporting the electrodes of the semiconductor chip and the electrodes of the circuit board, and removing the plating resist after the connection between the electrodes of the semiconductor chip and the circuit board is completed. It is a configuration including.
【００１４】また、本発明の半導体チップおよび回路基
板の接続方法は、前記半導体チップのメッキ不要部に第
１の絶縁物を形成する工程を含む構成とすることもでき
る。The method of connecting a semiconductor chip and a circuit board of the present invention can also be configured so as to include a step of forming a first insulator on a portion of the semiconductor chip where plating is unnecessary.
【００１５】さらにまた、本発明の半導体チップおよび
回路基板の接続方法は、前記回路基板のメッキ不要部に
第２の絶縁物を形成する工程を含む構成とすることもで
きる。Furthermore, the method of connecting a semiconductor chip and a circuit board according to the present invention may be configured to include a step of forming a second insulating material on a plating unnecessary portion of the circuit board.
【００１６】さらにまた、本発明の半導体チップおよび
回路基板の接続方法の前記第１の絶縁物は前記メッキレ
ジストまたは二酸化シリコン膜である構成とすることも
でき、半導体チップおよび回路基板の接続方法の前記第
２の絶縁物は前記メッキレジストまたは二酸化シリコン
膜である構成とすることもできる。Furthermore, the first insulator in the method of connecting a semiconductor chip and a circuit board of the present invention may be the plating resist or a silicon dioxide film, and the method of connecting a semiconductor chip and a circuit board can be used. The second insulator may be the plating resist or the silicon dioxide film.
【００１７】[0017]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【００１８】図１〜図３は本発明の第１の実施例の半導
体チップと回路基板の接続方法で処理された半導体装置
の実装構造の断面図である。1 to 3 are sectional views of a mounting structure of a semiconductor device processed by the method of connecting a semiconductor chip and a circuit board according to the first embodiment of the present invention.
【００１９】まず、この実施例の接続方法は、電気特性
チェック済ウェハース中にあるチップ１の裏面にレジス
ト３を塗布し、プリキュアーを行う。チップ１にはパッ
ド２が形成されている（図１（ａ））。次に、チップ１
の表面にレジスト４を塗布、プリキュアーを行う（図１
（ｂ））。First, in the connection method of this embodiment, the resist 3 is applied to the back surface of the chip 1 in the wafer whose electrical characteristics have been checked, and pre-curing is performed. Pads 2 are formed on the chip 1 (FIG. 1A). Next, chip 1
Resist 4 is applied to the surface of and the pre-curing is performed (Fig. 1
(B)).
【００２０】さらに、ウェハー表面の目合わせ、両面露
光現像を行い、所望の高さのレジスト４を形成する（図
１（ｃ））。レジスト４の高さは、無電解メッキによる
チップ１と回路基板１０との間隔に合わせるようにす
る。一般的には１０〜１００μｍ位の高さである。チッ
プ１に貼付テープ５を温度５０〜６０℃、荷重０．５〜
５ｋｇ／ｃｍ2 位の条件下で貼付する（図１（ｄ））。Further, the wafer surface is aligned and both surfaces are exposed and developed to form a resist 4 having a desired height (FIG. 1 (c)). The height of the resist 4 is adjusted to match the distance between the chip 1 and the circuit board 10 formed by electroless plating. Generally, the height is about 10 to 100 μm. Attach the tape 5 to the chip 1 at a temperature of 50 to 60 ° C and a load of 0.5 to
It is attached under the condition of about 5 kg / cm 2 (Fig. 1 (d)).
【００２１】さらに、刃幅４０〜５０μｍのダイヤモン
ドホイールを用いてフルカットダイシングを行い、ダイ
シング溝６を形成する（図２（ａ））。その後、ダイシ
ング溝６にレジストをスピンコートまたはディスペンス
法等により塗布し、露光，現像，プリキュアーを行い、
レジスト７を形成する。次に、刃幅２０〜３０μｍダイ
ヤモンドホイールを用いてダイシングを行い、ダイシン
グ溝８を形成する（図２（ｂ））。ウェハース状態から
チップ１の単品に分割する（図２（ｃ））。Further, full-cut dicing is performed using a diamond wheel having a blade width of 40 to 50 μm to form the dicing groove 6 (FIG. 2 (a)). After that, a resist is applied to the dicing groove 6 by spin coating or a dispensing method, and exposure, development, and precure are performed,
A resist 7 is formed. Next, dicing is performed using a diamond wheel having a blade width of 20 to 30 μm to form the dicing groove 8 (FIG. 2B). The wafer 1 is divided into individual chips 1 (FIG. 2C).
【００２２】ここまでの加工工程によって、チップ１に
は、裏面にレジスト３が形成され、端面にレジスト７が
形成され、表面にチップ１と回路基板１０との間隔維持
と支持および位置決めのためのレジスト４が形成された
ことになる。Through the processing steps up to this point, the chip 1 has the resist 3 formed on the back surface and the resist 7 formed on the end surface thereof, for maintaining the space between the chip 1 and the circuit board 10 for supporting and positioning. The resist 4 is formed.
【００２３】従って、この実施例の接続方法で処理され
たチップ１は、メッキ不要部へのレジスト形成によるメ
ッキ不着機能とチップ１と回路基板１０との間隔維持と
支持，位置決め機能との二つの機能を持つことになる。Therefore, the chip 1 processed by the connection method of this embodiment has two functions, that is, a non-plating function by resist formation on an unnecessary plating portion, a space maintenance between the chip 1 and the circuit board 10, and a supporting and positioning function. It will have a function.
【００２４】次に、搭載機を用いて、回路基板１０の回
路基板パッド９とチップ１のパッド２とを目合わせを行
い、軽く押下げ、レジスト４の粘着力を利用して接着す
る。チップ１と回路基板１０との間隔は、レジスト４の
高さでほぼ決定する（図２（ｄ））。Next, using the mounting machine, the circuit board pads 9 of the circuit board 10 and the pads 2 of the chip 1 are aligned with each other, lightly pressed down, and bonded by using the adhesive force of the resist 4. The distance between the chip 1 and the circuit board 10 is substantially determined by the height of the resist 4 (FIG. 2 (d)).
【００２５】次に、搭載完了したものを無電解メッキ液
１１中に浸漬する。浸漬時間は無電解メッキ液および析
出速度、液温等によって異なってくるが、回路基板パッ
ド９とチップ１のパッド２との間隔を析出速度で除した
時間より少し長い時間で行う。所定時間浸漬することに
より析出メタル１２により電気的な接続が完了する（図
３（ａ））。Next, the completed mounting is immersed in the electroless plating solution 11. Although the immersion time varies depending on the electroless plating solution, the deposition rate, the solution temperature, etc., the immersion time is a little longer than the time obtained by dividing the distance between the circuit board pad 9 and the pad 2 of the chip 1 by the deposition rate. By immersing for a predetermined time, the deposited metal 12 completes the electrical connection (FIG. 3A).
【００２６】最終工程としてチップ１の裏面に形成され
ていたレジスタ３，端面に形成されていたレジスト７お
よび表面に形成されていたレジスト４のそれぞれを、レ
ジスト除去剤（例えば、ＭＥＫではＴａ＝２５℃で０．
５〜５分程度）で除去し、乾燥する（図３（ｂ））。As a final step, the resist 3 formed on the back surface of the chip 1, the resist 7 formed on the end surface, and the resist 4 formed on the front surface are respectively removed by a resist removing agent (Ta = 25 in MEK, for example). 0 ° C.
It is removed in about 5 to 5 minutes) and dried (FIG. 3 (b)).
【００２７】以上述べた本発明の第１の実施例の半導体
チップおよび回路基板の接続方法による効果は、次の通
りである。The effects of the method of connecting the semiconductor chip and the circuit board according to the first embodiment of the present invention described above are as follows.
【００２８】まず第一に、チップの位置決めおよび支持
に所望高さのメッキレジストを設けているため、チップ
と回路基板との間隔を精度よく形成できる。また、接続
完了後、レジストを除去できるため、メッキ液残渣によ
る半導体装置への悪影響もなくなる。First of all, since the plating resist having a desired height is provided for positioning and supporting the chip, the distance between the chip and the circuit board can be accurately formed. Further, since the resist can be removed after the connection is completed, the adverse effect of the plating solution residue on the semiconductor device is eliminated.
【００２９】第二に、チップのメッキ不要部を絶縁物で
被覆しているため、メッキの形成がないので回路のショ
ートが発生しない。また除去工程も不要となる。更に接
続完了後レジストを除去できるため、メッキ液残渣によ
る半導体装置への悪影響もなくなる。Secondly, since the non-plating portion of the chip is covered with an insulating material, there is no plating, so that no short circuit occurs in the circuit. Further, the removing step is also unnecessary. Further, since the resist can be removed after the connection is completed, there is no adverse effect on the semiconductor device due to the plating solution residue.
【００３０】本実施例の接続方法の説明では、半導体チ
ップについてのみ述べているが、回路基板にも適用でき
るものであり、特にシリコン回路基板または導電性材料
ベースの回路基盤には効果が大きい。In the description of the connection method of the present embodiment, only the semiconductor chip is described, but it can also be applied to a circuit board, and is particularly effective for a silicon circuit board or a circuit board based on a conductive material.
【００３１】次に、本発明の第２の実施例の半導体チッ
プと回路基板の接続方法について説明する。Next, a method of connecting the semiconductor chip and the circuit board according to the second embodiment of the present invention will be described.
【００３２】図４〜図６は、この実施例の接続方法で処
理された半導体素子の実装構造の断面図である。4 to 6 are sectional views of the mounting structure of the semiconductor element processed by the connecting method of this embodiment.
【００３３】まず第一に、この実施例の接続方法は、電
気特性チェック済ウェハース中にあるチップ１の裏面を
酸化させて、二酸化シリコン膜１３を形成する。酸化は
酸化雰囲気（例えばａｉｒ，Ｏ2 ）中で温度５００℃以
下で実施する。二酸化シリコン膜１３の膜厚は、自然酸
化膜レベルでも良く、従って短時間で容易に処理できる
（図４（ａ））。First of all, in the connection method of this embodiment, the back surface of the chip 1 in the wafer with the checked electrical characteristics is oxidized to form the silicon dioxide film 13. The oxidation is performed at a temperature of 500 ° C. or lower in an oxidizing atmosphere (for example, air, O 2 ). The film thickness of the silicon dioxide film 13 may be at the level of a natural oxide film, and therefore can be easily processed in a short time (FIG. 4A).
【００３４】次に、裏面酸化済チップ１をフルカットダ
イシングのために貼付テープ５に貼付ける。この貼付テ
ープは高耐熱性の材質のものを使用する（図４
（ｂ））。Next, the back surface oxidized chip 1 is attached to the attaching tape 5 for full cut dicing. For this adhesive tape, use a material with high heat resistance (Fig. 4
(B)).
【００３５】次に、刃幅２０〜５０μｍ位のダイヤモン
ドホイールを使用してフルカットダイシングを行い、ダ
イシング溝６を形成する（図４（ｃ））。さらに、フル
カットダイシングされたチップ１の端面に二酸化シリコ
ン膜１３を酸化雰囲気中（ａｉｒ，Ｏ2 等）で加熱（３
５０℃以下）して形成する（図４（ｄ））。Next, full cut dicing is performed using a diamond wheel having a blade width of about 20 to 50 μm to form the dicing groove 6 (FIG. 4 (c)). Further, the silicon dioxide film 13 is heated on the end surface of the chip 1 which has been subjected to full-cut dicing in an oxidizing atmosphere (air, O 2, etc.) (3
It is formed at 50 ° C. or lower) (FIG. 4D).
【００３６】その後、チップ１の表面にレジスト用ドラ
イフィルム１４を貼付ける（図５（ａ））。さらに、目
合わせ，露光，現像，プリキュアーを行い、レジスト用
ドライフィルム１４を形成して、ウェハース状態からチ
ップ１の単品に分割する（図５（ｂ））。Thereafter, a dry film for resist 14 is attached to the surface of the chip 1 (FIG. 5A). Further, alignment, exposure, development, and precure are performed to form a resist dry film 14, and the wafer 1 is divided into individual chips 1 (FIG. 5B).
【００３７】ここまでの加工工程によって、チップ１に
は、裏面と端面に二酸化シリコン膜１３が形成され、表
面にはチップ１と回路基板１０との間隔維持と支持，位
置決めのためのレジスト用ドライフィルム１４が形成さ
れたことになる。Through the processing steps up to this point, a silicon dioxide film 13 is formed on the back surface and the end surface of the chip 1, and a resist dry film for maintaining the distance between the chip 1 and the circuit board 10 and supporting and positioning the same on the front surface. The film 14 is formed.
【００３８】従って、この実施例の接続方法で処理され
たチップ１はメッキ不要部への二酸化シリコン膜形成に
よるメッキ不着機能とチップ１と回路基板１０との間隔
維持と支持，位置決め機能との二つの機能を持つことに
なる（図５（ｃ））。Therefore, the chip 1 processed by the connection method of this embodiment has two functions of non-plating by forming a silicon dioxide film on the non-plating portion, maintenance of the space between the chip 1 and the circuit board 10, and support and positioning. It will have two functions (Fig. 5 (c)).
【００３９】次に、搭載機を用いて回路基板１０の回路
基板パッド９とチップ１のパッド２とを目合わせを行
い、軽く押下げ、レジスト用ドライフィルム１４の粘着
力を利用して接着する。チップ１と回路基板１０との間
隔はレジスト用ドライフィルム１４の高さで決定する
（図５（ｄ））。Next, the circuit board pad 9 of the circuit board 10 and the pad 2 of the chip 1 are aligned with each other using a mounting machine, lightly pressed down, and bonded by utilizing the adhesive force of the dry film 14 for resist. . The distance between the chip 1 and the circuit board 10 is determined by the height of the dry film 14 for resist (FIG. 5D).
【００４０】その後に、搭載完了したものを無電解メッ
キ液１１中に浸漬する。浸漬時間は無電解メッキ液およ
び析出速度、液温等によって異なってくるが、回路基板
パッド９とチップ１のパッド２との間隔を析出速度で除
した時間に若干プラスした時間で行う。所定時間浸漬す
ることにより析出メタル１２により電気的な接続が完了
する（図６（ａ））。Then, the completed mounting is immersed in the electroless plating solution 11. Although the immersion time varies depending on the electroless plating solution, the deposition rate, the solution temperature, etc., the immersion time is slightly added to the time obtained by dividing the interval between the circuit board pad 9 and the pad 2 of the chip 1 by the deposition rate. By immersing for a predetermined time, the deposited metal 12 completes the electrical connection (FIG. 6A).
【００４１】最終工程としてレジスト用ドライフィルム
１４を除去剤で除去し、乾燥する（図６（ｂ））。In the final step, the resist dry film 14 is removed with a remover and dried (FIG. 6B).
【００４２】以上述べた第２の実施例の接続方法による
効果は次の通りである。The effects of the connection method of the second embodiment described above are as follows.
【００４３】まず第一に、チップの位置決めおよび支持
に所望の高さのメッキレジスト用ドライフィルムを設け
ているため、チップと回路基板との間隔を精度よく形成
できる。また接続完了後、メッキレジスト用ドライフィ
ルムを除去できるため、メッキ液残渣による半導体装置
への悪影響もなくなる。First, since the plating resist dry film having a desired height is provided for positioning and supporting the chip, the interval between the chip and the circuit board can be accurately formed. Further, since the dry film for the plating resist can be removed after the connection is completed, the adverse effect on the semiconductor device due to the residue of the plating solution is eliminated.
【００４４】第二に、チップのメッキ不要部を二酸化シ
リコン膜の無機絶縁物で被覆しているため、メッキ形成
がないので回路のショートが発生しない。またメッキ液
の汚染もない。更にメッキ液残渣による半導体装置への
悪影響もなくなる。Second, since the non-plating portion of the chip is covered with the inorganic insulator of the silicon dioxide film, there is no plating, so that no short circuit occurs in the circuit. Moreover, there is no contamination of the plating solution. Further, the adverse effect on the semiconductor device due to the plating solution residue is eliminated.
【００４５】この実施例の接続方法の説明では半導体チ
ップについてのみ述べているが、回路基板にも適用でき
るものであり、特にシリコン回路基板には効果が大き
い。Although only the semiconductor chip is described in the description of the connection method of this embodiment, it can be applied to a circuit board, and the effect is particularly great on a silicon circuit board.
【００４６】さらに、本発明の実施例の二例ともに、メ
ッキ液の汚染が最小限に防止できるので液の長寿命化、
管理の容易化等を図ることができるため、純度の高い安
定した析出メタルが得られる。Further, in both of the two examples of the present invention, since the contamination of the plating solution can be prevented to a minimum, the life of the solution is prolonged,
Since management can be facilitated, a stable and highly precipitated metal can be obtained.
【００４７】その結果、チップの電極と回路基板の電極
との信頼性の高い接続が得られる。As a result, a highly reliable connection between the electrode of the chip and the electrode of the circuit board can be obtained.
【００４８】[0048]
【発明の効果】以上説明したように、本発明は、半導体
チップの電極と回路基板の電極との接続に無電解メッキ
法を用いた接続方法において、半導体チップの位置決
め、支持にメッキレジストを使用し、接続完了後除去す
るようにしたので、半導体チップと回路基板との間隔を
精度よく形成することができ、またメッキ液の汚染を最
小限にでき、また、メッキ液残渣による半導体装置への
悪影響が防止でき、搭載後の半導体チップの搭載インデ
ックスＵＰができる効果を有する。As described above, according to the present invention, a plating resist is used for positioning and supporting the semiconductor chip in the connection method using the electroless plating method for connecting the electrode of the semiconductor chip and the electrode of the circuit board. Since the connection is removed after the connection is completed, the distance between the semiconductor chip and the circuit board can be accurately formed, the contamination of the plating solution can be minimized, and the semiconductor device due to the residue of the plating solution can be removed. It is possible to prevent adverse effects and to increase the mounting index UP of the semiconductor chip after mounting.
【００４９】また、半導体チップ，回路基板等のメッキ
不要部にメッキレジストおよび酸化膜等の絶縁物を形成
させたので、メッキの形成がないので回路のショートが
発生しない。また、メッキ薄膜を除去する工程が不要と
なり、メッキ液の汚染を最小限にできる効果を有する。Further, since the plating resist and the insulating material such as the oxide film are formed on the portions of the semiconductor chip, the circuit board and the like which do not require plating, the circuit is not short-circuited because the plating is not formed. Further, the step of removing the plating thin film is unnecessary, and the effect of minimizing the contamination of the plating solution is obtained.
【図１】本発明の第１の実施例の半導体チップおよび回
路基板の接続方法を適用した半導体チップの断面図を示
し、分図（ａ）乃至分図（ｄ）はその工程フロー別の断
面図である。FIG. 1 is a cross-sectional view of a semiconductor chip to which a method for connecting a semiconductor chip and a circuit board according to a first embodiment of the present invention is applied, and FIGS. 1A to 1D are cross-sectional views for each process flow. It is a figure.
【図２】本発明の第１の実施例の半導体チップおよび回
路基板の接続方法を適用した半導体チップの断面図を示
し、分図（ａ）乃至分図（ｄ）はその工程フロー別の断
面図である。FIG. 2 is a cross-sectional view of a semiconductor chip to which the method for connecting a semiconductor chip and a circuit board according to the first embodiment of the present invention is applied, and FIGS. 2A to 2D are cross-sectional views for each process flow. It is a figure.
【図３】本発明の第１の実施例の半導体チップおよび回
路基板の接続方法を適用した半導体チップおよび回路基
板の断面図のそれぞれを示し、分図（ａ）乃至分図
（ｃ）はその工程フロー別の断面図である。3A and 3B are cross-sectional views of a semiconductor chip and a circuit board to which the method for connecting a semiconductor chip and a circuit board according to the first embodiment of the present invention is applied, and FIGS. It is sectional drawing according to process flow.
【図４】本発明の第２の実施例の半導体チップおよび回
路基板の接続方法を適用した半導体チップの断面図を示
し、分図（ａ）乃至分図（ｄ）はその工程フロー別の断
面図である。FIG. 4 is a cross-sectional view of a semiconductor chip to which a method for connecting a semiconductor chip and a circuit board according to a second embodiment of the present invention is applied, and FIGS. 4A to 4D are cross-sectional views for each process flow. It is a figure.
【図５】本発明の第２の実施例の半導体チップおよび回
路基板の接続方法を適用した半導体チップおよび回路基
板の断面図のそれぞれを示し、分図（ａ）乃至分図
（ｄ）はその工程フロー別の断面図である。5A and 5B are cross-sectional views of a semiconductor chip and a circuit board to which a method for connecting a semiconductor chip and a circuit board according to a second embodiment of the present invention is applied, and FIGS. It is sectional drawing according to process flow.
【図６】本発明の第１の実施例の半導体チップおよび回
路基板の接続方法を適用した半導体チップおよび回路基
板の断面図のそれぞれを示し、分図（ａ）乃至分図
（ｂ）はその工程フロー別の断面図である。FIG. 6 is a cross-sectional view of a semiconductor chip and a circuit board to which the method for connecting a semiconductor chip and a circuit board according to the first embodiment of the present invention is applied, and FIGS. It is sectional drawing according to process flow.
【図７】従来の半導体チップおよび回路基板の接続方法
を適用した半導体チップおよび回路基板の断面図のそれ
ぞれを示し、分図（ａ）および（ｂ）のそれぞれはその
工程フロー別の断面図である。7A and 7B are cross-sectional views of a semiconductor chip and a circuit board to which a conventional method for connecting a semiconductor chip and a circuit board is applied, and FIGS. 7A and 7B are cross-sectional views for each process flow. is there.
１ 半導体チップ ２ パッド ３，４，７ レジスト ５ 貼付テープ ６，８ ダイシング溝 ９ 回路基板パッド １０，７４ 回路基板 １１ 無電解メッキ液 １２ 析出メタル １３ 二酸化シリコン膜 １４ ドライフィルム ７１ 半導体素子 ７２ マイクロバンプ ７３，７６ 絶縁膜 ７５ 基板電極 ７７ 樹脂層 ７８ 接続電極 1 Semiconductor Chip 2 Pad 3, 4, 7 Resist 5 Adhesive Tape 6, 8 Dicing Groove 9 Circuit Board Pad 10, 74 Circuit Board 11 Electroless Plating Liquid 12 Precipitated Metal 13 Silicon Dioxide Film 14 Dry Film 71 Semiconductor Element 72 Micro Bump 73 , 76 Insulating film 75 Substrate electrode 77 Resin layer 78 Connection electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 日下 輝雄 東京都港区芝五丁目７番１号 日本電気 株式会社内 (56)参考文献 特開 昭48−95773（ＪＰ，Ａ) 特開 平７−86340（ＪＰ，Ａ) 特開 平６−224265（ＪＰ，Ａ) 特開 平２−66953（ＪＰ，Ａ) 特開 昭62−296431（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Teruo Kusaka, Inventor Teruo Kusaka 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (56) Reference JP-A-48-95773 (JP, A) JP-A 7-86340 (JP, A) JP-A-6-224265 (JP, A) JP-A-2-66953 (JP, A) JP-A-62-296431 (JP, A)
Claims (5)
極の接続を無電解メッキ法を用いた半導体チップおよび
回路基板の接続方法において、前記半導体チップの電極
と前記回路基板の電極との位置決め工程および支持工程
にメッキレジストを使用し、前記半導体チップの電極と
前記回路基盤との接続が完了した後前記メッキレジスト
を除去する工程を含むことを特徴とする半導体チップお
よび回路基板の接続方法。1. A method of connecting a semiconductor chip electrode and a circuit board electrode using an electroless plating method for connecting a semiconductor chip electrode and a circuit board electrode, wherein a step of positioning the electrode of the semiconductor chip and the electrode of the circuit board, and A method of connecting a semiconductor chip and a circuit board, which comprises using a plating resist in a supporting step, and removing the plating resist after the connection between the electrode of the semiconductor chip and the circuit board is completed.
の絶縁物を形成する工程を含むことを特徴とする請求項
１記載の半導体チップおよび回路基板の接続方法。2. A first portion of the semiconductor chip that does not require plating.
2. The method of connecting a semiconductor chip and a circuit board according to claim 1, further comprising the step of forming the insulating material.
縁物を形成する工程を含むことを特徴とする請求項１ま
たは２記載の半導体チップおよび回路基板の接続方法。3. The method of connecting a semiconductor chip and a circuit board according to claim 1, further comprising the step of forming a second insulating material on a portion of the circuit board that does not require plating.
または二酸化シリコン膜である請求項２または３記載の
半導体チップおよび回路基板の接続方法。4. The method for connecting a semiconductor chip and a circuit board according to claim 2, wherein the first insulator is the plating resist or a silicon dioxide film.
または二酸化シリコン膜である請求項３または４記載の
半導体チップおよび回路基板の接続方法。5. The method of connecting a semiconductor chip and a circuit board according to claim 3, wherein the second insulator is the plating resist or a silicon dioxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6287722A JP2561039B2 (en) | 1994-11-22 | 1994-11-22 | Method of connecting semiconductor chip and circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6287722A JP2561039B2 (en) | 1994-11-22 | 1994-11-22 | Method of connecting semiconductor chip and circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08148531A JPH08148531A (en) | 1996-06-07 |
| JP2561039B2 true JP2561039B2 (en) | 1996-12-04 |
Family
ID=17720904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6287722A Expired - Fee Related JP2561039B2 (en) | 1994-11-22 | 1994-11-22 | Method of connecting semiconductor chip and circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2561039B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4206779B2 (en) * | 2002-02-25 | 2009-01-14 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| CN100446244C (en) * | 2003-05-15 | 2008-12-24 | 财团法人熊本高新技术产业财团 | Semiconductor chip mounting body and manufacturing method thereof |
| JP2004363573A (en) * | 2003-05-15 | 2004-12-24 | Kumamoto Technology & Industry Foundation | Semiconductor chip mounted body and its manufacturing method |
| JP4492520B2 (en) | 2005-01-26 | 2010-06-30 | セイコーエプソン株式会社 | Droplet discharge head and droplet discharge device. |
| JP4927343B2 (en) * | 2005-03-18 | 2012-05-09 | ルネサスエレクトロニクス株式会社 | Semiconductor chip and manufacturing method thereof |
| US8102045B2 (en) * | 2007-08-08 | 2012-01-24 | Infineon Technologies Ag | Integrated circuit with galvanically bonded heat sink |
| JP5533199B2 (en) * | 2010-04-28 | 2014-06-25 | ソニー株式会社 | Device board mounting method and board mounting structure thereof |
| WO2018047551A1 (en) * | 2016-09-09 | 2018-03-15 | 富士電機株式会社 | Semiconductor device manufacturing method and semiconductor device |
| JP7328560B2 (en) * | 2019-12-24 | 2023-08-17 | 日亜化学工業株式会社 | Light-emitting device manufacturing method and light-emitting device |
-
1994
- 1994-11-22 JP JP6287722A patent/JP2561039B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08148531A (en) | 1996-06-07 |
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