JP2560894B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2560894B2 JP2560894B2 JP19751290A JP19751290A JP2560894B2 JP 2560894 B2 JP2560894 B2 JP 2560894B2 JP 19751290 A JP19751290 A JP 19751290A JP 19751290 A JP19751290 A JP 19751290A JP 2560894 B2 JP2560894 B2 JP 2560894B2
- Authority
- JP
- Japan
- Prior art keywords
- metal base
- external lead
- semiconductor device
- conductor
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ダイオード，サイリスタなどの複数個の半
導体チッウを組合わせて構成したパワーモジュールを実
施対象とする半導体装置の構成に関する。The present invention relates to a configuration of a semiconductor device for which a power module configured by combining a plurality of semiconductor chips such as diodes and thyristors is implemented.
まず、パワーダイオードモジュールを対象とした半導
体装置の従来における構造例を第６図，第７図に示す。
なお、第６図，第７図は、いずれも第８図に示した三相
全波ブリッジ回路のうちの点線で囲んだ部分に対応した
ものである。First, FIGS. 6 and 7 show an example of a conventional structure of a semiconductor device intended for a power diode module.
It should be noted that FIGS. 6 and 7 both correspond to the portion enclosed by the dotted line in the three-phase full-wave bridge circuit shown in FIG.
第６図において、１は半導体チップ（ダイオード）、
２は半導体チップ１をマウントした金属ベース、３は放
熱基板、４は半導体チップ1,金属ベース２を包囲して放
熱基板３に結合したパッケージのケース、５はその蓋
部、6,7,8は蓋部５を貫通して引出した外部導出導体
（なお、図中のP,N,Wはそれぞれ第８図のブリッジ回路
に付した端子記号P,N,Wに対応する）、９は半導体チッ
プ１の上面電極と外部導出導体6,7,8との間に介挿した
補助接続導体片、10は半導体チップ１を封止するようパ
ッケージ内に充填したエポキシ樹脂などの充填材であ
る。なお、第６図の構造例では、２個の半導体チップ１
が共通な金属ベース２にマウントされている。また、パ
ッケージはケース４と蓋部５とが一体化したものを使用
する場合もある。In FIG. 6, 1 is a semiconductor chip (diode),
Reference numeral 2 is a metal base on which the semiconductor chip 1 is mounted, 3 is a heat dissipation board, 4 is a case of a package that surrounds the semiconductor chip 1 and the metal base 2, and is bonded to the heat dissipation board 3, 5 is its lid, 6, 7, 8 Are external lead-out conductors that extend through the lid 5 (note that P, N, and W in the figure correspond to the terminal symbols P, N, and W attached to the bridge circuit in FIG. 8), and 9 is a semiconductor An auxiliary connection conductor piece is interposed between the upper surface electrode of the chip 1 and the external lead-out conductors 6, 7, 8 and 10 is a filler such as an epoxy resin filled in the package so as to seal the semiconductor chip 1. In the structure example of FIG. 6, two semiconductor chips 1
Are mounted on a common metal base 2. Further, a package in which the case 4 and the lid 5 are integrated may be used in some cases.
ここで、外部導出導体6,7,8と補助接続導体片９との
接続構造について説明すると、第６図（ｂ）で示すよう
に補助接続導体片９は金属平板をＬ字状に屈曲し、かつ
上端に段付き挿入部9aを形成したものであり、その底辺
の平板部が半導体チップ１の上面電極に半田付け接合さ
れる。これに対して外部導出導体６（外部導出導体7,8
も同様である）の下端には直角に屈曲した水平方向の脚
部6aが形成され、かつこの脚部6aには補助接続導体片９
の挿入部9aと嵌合し合う穴6bが開口しており、（ｃ）図
のように穴6bに補助接続導体片９の挿入部9aを嵌め合わ
せた上で両者間が半田付け接合（17は半田を示す）され
ている。Here, the connection structure of the external lead-out conductors 6, 7, 8 and the auxiliary connecting conductor piece 9 will be described. As shown in FIG. 6 (b), the auxiliary connecting conductor piece 9 is formed by bending a metal flat plate into an L-shape. In addition, the stepped insertion portion 9a is formed on the upper end, and the flat plate portion on the bottom side is soldered to the upper surface electrode of the semiconductor chip 1. On the other hand, the external lead-out conductor 6 (external lead-out conductors 7, 8
Is also the same), a leg portion 6a in the horizontal direction bent at a right angle is formed at the lower end, and an auxiliary connecting conductor piece 9 is formed on this leg portion 6a.
Has a hole 6b which is fitted with the insertion portion 9a of the auxiliary connection conductor piece 9a, and the insertion portion 9a of the auxiliary connection conductor piece 9 is fitted into the hole 6b as shown in FIG. Is solder).
また、第７図は半導体チップ1,金属ベース２と外部導
出導体6,7,8との間に介挿した補助接続導体片として、
（ａ）図のように丸棒の一端に偏平なヘッドを形成した
ピン状の補助接続導体片11を採用し、これに対向して外
部導出導体6,7,8の先端には丸穴6cを穿孔したものであ
り、該丸穴6cにピン状補助接続導体片11の先端を差し込
んで両者間を半田付けするようにしている。In addition, FIG. 7 shows an auxiliary connecting conductor piece inserted between the semiconductor chip 1, the metal base 2 and the external lead-out conductors 6, 7, and 8.
(A) As shown in the figure, a pin-shaped auxiliary connecting conductor piece 11 in which a flat head is formed at one end of a round bar is adopted, and a round hole 6c is provided at the tip of the external lead-out conductors 6, 7, 8 facing this. The tip end of the pin-shaped auxiliary connecting conductor piece 11 is inserted into the round hole 6c to solder the two.
かかる半導体装置は次記のような手順で組立てられ
る。すなわち、最初に半導体チプ１を金属ベース２にマ
ウントし、半導体チップ１の上面電極，および金属ベー
ス２にそれぞれ補助接続導体片9,あるいは11を半田付け
する。次に前記組立体の金属ベース２を放熱板３の上に
並べて取付け、さらに外部導出導体7,8,9を一括して治
具に取付けた状態で、上方より外部導出導体の脚部に穿
孔した穴6b,あるいは6cに補助接続導体片9,11を嵌め込
んで仮保持し、この状態で外部導出導体と補助接続導体
片との間を半田付け嵌合する。続いて放熱板３の上にケ
ース４を載せて接着，硬化させた後に、ケース内に樹脂
充填材10を注入し、さらに蓋部５を被せて外部導出導体
6,7,8をパッケージ外に引き出す。なお、必要により外
部導出導体の突出端をケース蓋の上面側に折り曲げて外
部接続端子とする。なお、ケースと蓋とが一体なパッケ
ージでは、別に充填材の注入穴を設けておき、パッケー
ジを装着した後に注入穴を通じて樹脂充填材をパッケー
ジ内い充填する。Such a semiconductor device is assembled by the following procedure. That is, first, the semiconductor chip 1 is mounted on the metal base 2, and the auxiliary connection conductor pieces 9 or 11 are soldered to the upper surface electrode of the semiconductor chip 1 and the metal base 2, respectively. Next, the metal bases 2 of the assembly are mounted side by side on the heat dissipation plate 3, and the outer lead conductors 7, 8 and 9 are collectively attached to the jig, and the legs of the outer lead conductor are punched from above. The auxiliary connecting conductor pieces 9 and 11 are fitted and temporarily held in the holes 6b or 6c, and in this state, the external lead conductor and the auxiliary connecting conductor piece are soldered and fitted. Subsequently, the case 4 is placed on the heat dissipation plate 3, adhered and cured, and then the resin filler 10 is injected into the case, and further, the lid 5 is covered to cover the outer lead conductor.
Pull 6,7,8 out of the package. If necessary, the projecting end of the external lead-out conductor is bent toward the upper surface of the case lid to form an external connection terminal. In addition, in a package in which the case and the lid are integrated, a filling material injection hole is provided separately, and after the package is mounted, the resin filling material is filled into the package through the injection hole.
ところで、前記した従来構造では、半導体装置の組
立，半田付け性の面で次記のような欠点がある。The conventional structure described above has the following drawbacks in terms of assembling and soldering the semiconductor device.
（１）放熱板３上に並べて取付けられた半導体チップ1,
金属ベース２にそれぞれ半田付け接合されている補助接
続導体片9,ないし11に対し、外部導出導体6,7,8を治具
に一括保持したまま差し込んで半田付けするようにして
いるので、補助接続導体片と外部導出導体との間に僅か
な位置ずれがあっても、補助接続導体片を外部導出導体
の脚部に穿孔した穴へ正しく嵌め込むことがでない。し
たがってこの半田付け工程では高い組立，決め精度が要
求される。(1) Semiconductor chips 1, which are mounted side by side on the heat sink 3.
Since the external lead-out conductors 6, 7 and 8 are inserted into the jig and soldered to the auxiliary connecting conductor pieces 9 to 11 respectively soldered to the metal base 2, Even if there is a slight misalignment between the connecting conductor piece and the external lead-out conductor, the auxiliary connecting conductor piece cannot be correctly fitted into the hole drilled in the leg of the external lead-out conductor. Therefore, in this soldering process, high assembly and determination accuracy is required.
（２）このために、従来では外部導出導体6,7,8に穿孔
した穴6b,6cをあらかじめ多少大きめに開けて多少の位
置ずれを吸収するようにしているが、一方では穴6b,6c
が大きいと、補助接続導体片9,ないし11との差し込み状
態で両者間に隙間が生じ、続く半田付けの際に第６図
（ｃ）に示したように溶融半田が前記の隙間を通じて下
方へ垂れ流れて半田接合の不良を引き起こしたり、半田
付け部から垂れ落ちた半田が半導体チップ１に付着する
と言った不具合が生じるおそれがある。(2) For this reason, conventionally, the holes 6b, 6c drilled in the outer lead-out conductors 6, 7, 8 are made a little larger in advance to absorb some displacement, but one of them is the holes 6b, 6c.
Is large, a gap is created between the auxiliary connection conductor pieces 9 and 11 when they are inserted, and the molten solder moves downward through the gap as shown in FIG. 6 (c) during subsequent soldering. There is a possibility that such a problem may occur that the solder flows dripping and causes a defective solder joint, or that the solder dripping from the soldering portion adheres to the semiconductor chip 1.
本発明は上記の点にかんがみてさなれたものであり、
先記した半導体装置を対象に、その組立工程で外部導出
導体と補助接続導体片との間に多少の位置ずれがあって
も、支障なく外部導出導体と補助接続導体片を確実に半
田付け接合できるようにした半導体装置、特に外部導出
導体と補助接続導体片との間の接続構造を提供すること
を目的とする。The present invention has been made in consideration of the above points,
For the above-mentioned semiconductor device, even if there is some misalignment between the external lead-out conductor and the auxiliary connecting conductor piece during the assembly process, the external lead-out conductor and the auxiliary connecting conductor piece can be securely soldered and joined. It is an object of the present invention to provide a semiconductor device made possible, especially a connection structure between an external lead conductor and an auxiliary connecting conductor piece.
上記課題を解決するために、本発明の半導体装置は次
記のように構成するものである。In order to solve the above problems, the semiconductor device of the present invention is configured as follows.
（１）上下両端に互いに並行な平板部を屈曲形成した補
助接続導体片を前記半導体チップ，ないし金属ベースと
外部導出導体との間にそれぞれ介在させ、かつ該補助接
続導体片の一方の平板部を半導体チップの上面電極，な
いし金属ベースに、他方の平板部を外部導出導体の下端
に屈曲形成した脚部にて面接触させて半田付け接合す
る。(1) Auxiliary connecting conductor pieces, which are formed by bending flat plate portions parallel to each other at upper and lower ends, are respectively interposed between the semiconductor chip or the metal base and an external lead conductor, and one flat plate portion of the auxiliary connecting conductor piece is provided. To the upper surface electrode of the semiconductor chip, or the metal base, and the other flat plate portion is brought into surface contact with the leg portion formed by bending at the lower end of the external lead conductor to be soldered and joined.
（２）金属ベースにはベース板の側縁より上方に起立
し、さらにその上端をベース板面と平行に屈曲させた端
子部を形成し、該端子部の上面に外部導出導体の下端に
屈曲形成した脚部を面接触させて半田付け接合する。(2) A terminal portion is formed on the metal base so as to stand above the side edge of the base plate, and the upper end thereof is bent in parallel with the base plate surface, and the lower end of the externally derived conductor is bent on the upper surface of the terminal portion. The formed legs are brought into surface contact with each other for soldering.
（３）前記（２）の構成において、金属ベースの端子部
を、ベース板の周縁より上方に起立して半導体チップを
取り囲む外周側壁の一部に形成する。(3) In the configuration of (2), the terminal portion of the metal base is formed above a peripheral edge of the base plate and is formed on a part of an outer peripheral side wall surrounding the semiconductor chip.
（４）特に、隣り合う２個の半導体チップを対として各
半導体チップをマウントした金属ベースの双方にまたが
り外部導出導体を共通接続した構成のものに対し、各金
属ベースごとにベース板の側縁より起立して向かい合わ
せに並ぶ端子部を形成するとともに、該端子部に共通接
続する外部導出導体にはその下端に二股状に分岐した脚
部を屈曲形成し、かつ各分岐脚部を個々に金属ベース側
の端子部上面に面接触させて半田付け接合する。(4) In particular, for a structure in which two adjacent semiconductor chips are paired and the external lead conductors are commonly connected across both metal bases on which the semiconductor chips are mounted, the side edge of the base plate for each metal base. Further, the terminal portions are formed so as to stand upright and face each other, and the outer lead-out conductor commonly connected to the terminal portions is bent at its lower end to form a bifurcated leg portion, and each branch leg portion is individually formed. The upper surface of the terminal portion on the metal base side is brought into surface contact and soldered.
前項の解決手段（１）の構成により、外部導出導体と
補助接続導体片との間の半田付け工程で、外部導出導体
の位置が補助接続導体片に対して多少位置ずれがあって
も、外部導出導体の屈曲脚部と補助接続導体片の平板部
との間には面接触状態が保持されるので、これにより支
障なく両者間を確実に半田付け接合できる。しかも、半
田付けが水平な面同士の間で行われるので、溶融半田が
半田接合面から下方へ垂れ落ちるおそれはなく、これに
より半田付け不良，半導体チップへの半田の滴下などの
トラブルを確実に回避できる。With the configuration of the solution means (1) in the preceding paragraph, even if the position of the external lead-out conductor is slightly misaligned with respect to the auxiliary connecting conductor-piece during the soldering process between the external lead-out conductor and the auxiliary connecting-conductor piece, Since the surface contact state is maintained between the bent leg portion of the lead-out conductor and the flat plate portion of the auxiliary connection conductor piece, the two can be reliably soldered and joined together without any trouble. Moreover, since the soldering is performed between the horizontal surfaces, there is no fear that the molten solder will droop downward from the solder joint surface, which ensures troubles such as defective soldering and dropping of solder onto the semiconductor chip. It can be avoided.
また、解決手段（２）の構成でも、金属ベース側に形
成した端子部と外部導出導体との間の位置決め精度，半
田付け性に関して（１）項と同様な作用，硬化が得られ
る。Further, also with the configuration of the solving means (2), with respect to the positioning accuracy and the solderability between the terminal portion formed on the metal base side and the external lead conductor, the same action and hardening as those in the item (1) can be obtained.
一方、解決手段（３）のように、マウントした半導体
チップの周域を取り囲んで金属ベース板の周縁より起立
形成した外周側壁は次記のように機能する。On the other hand, as in the solution means (3), the outer peripheral side wall that surrounds the peripheral region of the mounted semiconductor chip and stands upright from the peripheral edge of the metal base plate functions as follows.
すなわち、半導体装置のパッケージ内に注入した封止
用の樹脂充填材は金属部品との接着性が低く、かつ熱膨
張係数も比較的大である。このために、半導体装置に加
わる熱サイクルにより、樹脂充填材が半導体チップをマ
ウントした金属ベースから剥離して膨張，収縮すると、
これに伴なって樹脂層内に埋没している接続導体を相対
的に動かすような応力が働き、この応力が接続導体を介
して半導体チップにストレスとして加わる。その結果、
半導体チップが特性劣化を来すおそれがある。That is, the encapsulating resin filler injected into the package of the semiconductor device has low adhesiveness to metal parts and has a relatively large coefficient of thermal expansion. For this reason, when the resin filler is separated from the metal base on which the semiconductor chip is mounted and expands and contracts due to the thermal cycle applied to the semiconductor device,
Along with this, a stress acts to relatively move the connection conductor buried in the resin layer, and this stress is applied to the semiconductor chip as a stress via the connection conductor. as a result,
The semiconductor chip may deteriorate in characteristics.
かかる点、半導体チップの周域を取り囲んで金属ベー
ス側に外周側壁を起立形成しておくことにより、該外周
側壁を境にその内側に注入した充填樹脂と外側に注入し
た樹脂とを切り離すとともに、側壁自身が充填樹脂と金
属ベースとの間の結着力を高めるように働く。これによ
り、樹脂充填材の膨張，収縮に伴って半導体チップに加
わるストレスを大幅に緩和できる。In this respect, by forming the outer peripheral side wall on the metal base side so as to surround the peripheral area of the semiconductor chip, the filling resin injected inside and the resin injected outside are separated from the outer peripheral side wall as a boundary, and The sidewall itself acts to enhance the binding force between the filling resin and the metal base. As a result, the stress applied to the semiconductor chip due to the expansion and contraction of the resin filler can be significantly reduced.
また、解決手段（４）のように、二つの金属ベースの
端子部にまたがって共通接続する外部導出導体の先端脚
部を二股状に分岐した上で、各分岐脚部を個別に相手側
の金属ベースの端子部に半田付け接合することにより、
充填樹脂の膨張，収縮に伴う応力が外部導出導体を介し
て双方の金属ベースの間で相互に機械的に干渉し合うこ
とがなくなり、これにより金属ベースなどに加わる応力
の緩和が図れる。Further, as in the solution means (4), the distal leg portions of the external lead conductor commonly connected to the two metal base terminal portions are bifurcated, and the branch leg portions are individually connected to each other. By soldering and joining to the terminal part of the metal base,
The stress caused by the expansion and contraction of the filling resin does not mechanically interfere with each other between the metal bases via the externally derived conductors, whereby the stress applied to the metal bases can be relaxed.
以下本発明の実施例を図面に基づいて説明する。な
お、各実施例において、第６図，第７図に対応する同一
部材には同じ符号が付してある。Embodiments of the present invention will be described below with reference to the drawings. In each embodiment, the same members corresponding to FIGS. 6 and 7 are designated by the same reference numerals.
実施例1: 第１図（ａ），（ｂ）はダイオードを組合わせて構成
したパワーモジュールに対する実施例を示すものであ
り、半導体チップ1,金属ベース２と外部導出導体6,7,8
との間に介在した補助接続導体片として、（ｂ）図に示
すような形状の補助接続導体片12を採用したものであ
る。すなわち、補助接続導体片12は、短冊状の金属板
（銅板）をその長手方向の二箇所で異なる方向へ直角に
屈曲してその上下両端に水平な平板部12a,12bと、この
間を連ねた垂直辺部12cを形成したものである。そし
て、下辺側の平辺部12bを半導体チップ1,ないし金属ベ
ース２の上面に面接触させて半田付け接合するととも
に、外部導出導体6,7,8の下端を直角に折り曲げて屈曲
形成した脚部を上辺側の平板部12aの上に面接触させて
半田付け接合する。Embodiment 1: FIGS. 1 (a) and 1 (b) show an embodiment for a power module configured by combining diodes, and include a semiconductor chip 1, a metal base 2 and external lead-out conductors 6, 7, 8
The auxiliary connecting conductor piece 12 having a shape as shown in FIG. 2B is adopted as the auxiliary connecting conductor piece interposed between the auxiliary connecting conductor piece 12 and. That is, the auxiliary connection conductor piece 12 is formed by bending a strip-shaped metal plate (copper plate) at two locations in the longitudinal direction at right angles to different directions and connecting flat plate portions 12a and 12b at the upper and lower ends thereof with a space between them. The vertical side portion 12c is formed. Then, the lower flat side 12b is brought into surface contact with the upper surface of the semiconductor chip 1 or the metal base 2 for soldering, and the lower ends of the external lead-out conductors 6, 7, 8 are bent at right angles to form legs. The portion is brought into surface contact with the flat plate portion 12a on the upper side and soldered and joined.
かかる構成により、前記放熱板３の上に取付けた半導
体チップ1,金属ベース2,,補助接続導体片12の組立体に
対し、外部導出導体6,7,8を治具に一括保持して上方よ
り補助接続導体片12に当てがって半田付け接合する場合
に、外部導出導体と補助接続導体片との間に多少の位置
ずれがあっても、互いに対向する外部導出導体6,7,8の
先端脚部と補助接続導体片12の平板部12aとが上下に重
なり合って面接触状態が保持される。したがって多少の
位置ずれに左右されることなく、両者間を確実に半田付
けすることができる。しかも、半田接合面が水平面であ
るので、溶融半田が半田接合面から不用意に垂れ落ちて
半導体チップ１に滴下するおよれもない。With such a configuration, the external lead-out conductors 6, 7, 8 are collectively held by the jig on the assembly of the semiconductor chip 1, the metal base 2, and the auxiliary connecting conductor piece 12 mounted on the heat dissipation plate 3 and the upper side. When the auxiliary connecting conductor piece 12 is applied to the auxiliary connecting conductor piece 12 for soldering, even if there is a slight positional deviation between the external lead conductor and the auxiliary connecting conductor piece, the external lead conductors 6, 7, 8 facing each other are provided. And the flat plate portion 12a of the auxiliary connecting conductor piece 12 are vertically overlapped with each other to maintain the surface contact state. Therefore, the two can be reliably soldered together without being affected by a slight displacement. Moreover, since the solder joint surface is a horizontal surface, there is no possibility that the molten solder drops from the solder joint surface inadvertently and drops onto the semiconductor chip 1.
実施例2: 第２図（ａ），（ｂ）は半導体チップ１の一方にサイ
リスタチップ（図中における右側の半導体チップ）を採
用した混合ブリッジ回路に適用するパワーモジュールの
実施例を示すものである。この実施例では、特に、サイ
リスタチップに使用する補助接続導体片として、（ｂ）
図で示すように上辺側に二つの平板部13a,13bを形成し
たＵ字形の補助接続導体片13を採用している。そして、
その底辺側の平板部13cをサイリスタチップのアノード
（上面電極）に半田付け接合するとともに、上辺側の平
板部13a,13bの一方には外部導出導体６を、残りの平板
部にはプリント配線板14を接続し、かつサイリスタチッ
プより補助接続導体片13の底辺側平板部13cに穿孔した
穴13dを通じて引出したゲートリード線15を前記のプリ
ント配線板14に接続し、ここからさらにパッケージの蓋
部５を貫通して外部に引出したものである。なお、半導
体チップ1,金属ベース２に接続した補助接続導体片12,1
3と外部導出導体6,7,8との間の位置決め，半田付け性に
ついては実施例１の場合と同様な効果が得られる。Embodiment 2: FIGS. 2 (a) and 2 (b) show an embodiment of a power module applied to a mixed bridge circuit in which a thyristor chip (semiconductor chip on the right side in the drawing) is adopted as one of the semiconductor chips 1. is there. In this embodiment, in particular, as the auxiliary connecting conductor piece used in the thyristor chip, (b)
As shown in the figure, a U-shaped auxiliary connecting conductor piece 13 in which two flat plate portions 13a and 13b are formed on the upper side is adopted. And
The flat plate portion 13c on the bottom side is soldered and bonded to the anode (upper surface electrode) of the thyristor chip, and the external lead-out conductor 6 is provided on one of the flat plate portions 13a and 13b on the upper side and the printed wiring board is provided on the remaining flat plate portions. 14 is connected to the printed wiring board 14 by connecting the gate lead wire 15 drawn from the thyristor chip through the hole 13d formed in the flat plate portion 13c on the bottom side of the auxiliary connecting conductor piece 13 to the printed wiring board 14. It penetrates 5 and is drawn out. Auxiliary connecting conductor pieces 12, 1 connected to the semiconductor chip 1 and the metal base 2
With respect to the positioning between the 3 and the externally-derived conductors 6, 7, 8 and the solderability, the same effects as in the case of the first embodiment can be obtained.
実施例3: 第３図（ａ），（ｂ）は実施例１（第１図）の応用実
施例を示すものであり、実施例１で述べた補助接続導体
片12に代えて、第３図（ｂ）で示すようにコ字形に屈曲
した補助接続導体片16（16a,16bは平板部、16cは垂直辺
部）を採用して半導体チップ１と外部導出導体6,7との
間を相互接続するとともに、金属ベース２と外部導出導
体８との間の接続構造として、金属ベース２側には側縁
より上方に起立した端子部2aを形成し、この端子部2aに
外部導出導体８を接続したものである。ここで、端子部
2aには上端部を外方へ直角に折り曲げて他の補助接続導
体片と同様な平板部2bが形成されており、この平板部2b
の上面に外部導出導体８の屈曲脚部を面接触させて両者
間を半田付け接合している。この実施例においても、実
施例１と同様な効果の得られることは明らかである。Example 3: FIGS. 3 (a) and 3 (b) show an application example of Example 1 (FIG. 1). Instead of the auxiliary connecting conductor piece 12 described in Example 1, a third example As shown in FIG. 2B, the auxiliary connecting conductor piece 16 (16a, 16b is a flat plate portion, 16c is a vertical side portion) bent in a U-shape is used to connect between the semiconductor chip 1 and the external lead conductors 6, 7. As a connection structure between the metal base 2 and the external lead-out conductor 8 which is interconnected, a terminal portion 2a standing above the side edge is formed on the metal base 2 side, and the external lead-out conductor 8 is formed on the terminal portion 2a. Is connected. Where the terminal part
A flat plate portion 2b similar to other auxiliary connecting conductor pieces is formed by bending the upper end portion outwardly at a right angle to 2a.
The bent leg portion of the externally-derived conductor 8 is brought into surface contact with the upper surface of the above, and the two are soldered and joined together. It is obvious that the same effect as in Example 1 can be obtained in this example as well.
なお、第３図において、金属ベース２側に起立形成し
た端子部2aの代わりに、半導体チップ１と外部導出導体
6,7との間に介挿した補助接続導体片16と同様な補助接
続導体片を使用して実施することもできる。In addition, in FIG. 3, instead of the terminal portion 2a formed upright on the metal base 2 side, a semiconductor chip 1 and an external lead conductor are formed.
It is also possible to use an auxiliary connection conductor piece similar to the auxiliary connection conductor piece 16 interposed between the auxiliary connection conductor pieces 6 and 7.
実施例4: 第４図（ａ）〜（ｂ）は先記した実施例３（第３図）
をさらに改良した応用実施例を示すものであり、
（ａ），（ｂ）図はそれぞれ組立状態の詳細構造を示す
一部切欠の上面図，側面図、（ｃ）図はパワーモジュー
ルの等価回路図、（ｄ）図は要部構造の斜視図を表して
いる。ここで、半導体チップ１をマウントした金属ベー
ス２には、半導体チップ１の周域を取り囲むように周囲
四辺より上方に立ち上がった外周側壁2cが起立形成され
ており、かつこの外周側壁2cの周縁一部にはその上縁か
ら延長した部分を外側へ直角に折り曲げた平板状の端子
部2aが形成してある。そして、この金属ベース２の端子
部2aの上面に外部導出導体6,7の屈曲脚部を面接触して
半田付け接合されている。なお、各半導体チップ１の上
面電極には実施例３で述べたと同様なコ字形の補助接続
導体片16が半田付けしてあり、該補助接続導体片16の上
面にまたがって外部導出導体８を下端より水平方向に延
長した脚部が半田付けされている。Example 4: FIGS. 4 (a) and 4 (b) are the same as Example 3 (FIG. 3) described above.
Shows an application example in which
(A) and (b) are respectively a partially cut-away top view and a side view showing the detailed structure of the assembled state, (c) is an equivalent circuit diagram of the power module, and (d) is a perspective view of the main structure. Is represented. Here, the metal base 2 on which the semiconductor chip 1 is mounted is provided with outer peripheral side walls 2c that stand up above the four peripheral sides so as to surround the peripheral region of the semiconductor chip 1, and the peripheral edge of the outer peripheral side wall 2c is formed. A plate-shaped terminal portion 2a is formed by bending a portion extending from the upper edge of the portion outwardly at a right angle. Then, the bent leg portions of the external lead-out conductors 6 and 7 are brought into surface contact with the upper surface of the terminal portion 2a of the metal base 2 for soldering. A U-shaped auxiliary connecting conductor piece 16 similar to that described in the third embodiment is soldered to the upper surface electrode of each semiconductor chip 1, and the external lead-out conductor 8 is laid across the upper surface of the auxiliary connecting conductor piece 16. The legs extending horizontally from the lower end are soldered.
上記構造の外周側壁2cは、先記の〔作用〕の項で説明
したように、パッケージ内に注入した封止用樹脂充填材
10の熱サイクルに伴う膨張，収縮に起因して半導体チッ
プ１に加わるストレスを低減する役目を果たす。The outer peripheral side wall 2c of the above-mentioned structure has the sealing resin filler injected into the package as described in the above [Operation] section.
It serves to reduce the stress applied to the semiconductor chip 1 due to the expansion and contraction accompanying the 10 thermal cycles.
実施例5: 第５図は２個の半導体チップ１を一組とし、該半導体
チップ１を個々にマウントして放熱板３の上に並置した
金属ベース２に対し、外部導出導体８を双方の金属ベー
ス２の間にまたがって共通接続したモジュールを対象と
する実施例である。Embodiment 5: FIG. 5 shows that two semiconductor chips 1 are set as a set, and the semiconductor chips 1 are individually mounted and a metal base 2 is juxtaposed on a heat dissipation plate 3 and an external lead conductor 8 is provided on both sides. This is an embodiment intended for modules commonly connected across the metal bases 2.
ここで、半導体チップ１を個々にマウントした金属ベ
ース２は、実施例４（第４図）で述べた外周側壁2c,お
よびその側壁の一部に形成した端子部2aを備えており、
かつ、（ａ），（ｂ）図のように、各金属ベース２は端
子部2aが互いに向かい合うように並べて放熱板３の上に
実装されている。一方、外部導出導体８の先端部には、
（ｃ）図に明示されているように、二股状に分けて屈曲
した分岐脚部8aと8bが形成してあり、各分岐脚部8a,8b
を個別に前記した金属ベース２の端子部2aの上面に当て
がって半田付け接合している。なお、上記の構成で各半
導体チップ１の極性を変えることにより、（ｄ）図に示
したイ，ロ，ハの三通りの回路を選択できる。Here, the metal base 2 on which the semiconductor chips 1 are individually mounted includes the outer peripheral side wall 2c described in the fourth embodiment (FIG. 4) and the terminal portion 2a formed on a part of the side wall,
Moreover, as shown in FIGS. 3A and 3B, the metal bases 2 are mounted on the heat sink 3 side by side so that the terminal portions 2a face each other. On the other hand, at the tip of the external lead conductor 8,
(C) As clearly shown in the figure, bifurcated bifurcated branch legs 8a and 8b are formed, and each branch leg 8a, 8b is formed.
Are individually applied to the upper surface of the terminal portion 2a of the metal base 2 and soldered and joined. By changing the polarities of the respective semiconductor chips 1 in the above-mentioned configuration, it is possible to select the three types of circuits (a), (b) and (c) shown in FIG.
かかる構成によれば、外部導出導体８の先端が二股状
に分岐しているので、パッケージ（図示せず）内に注入
した封止用の樹脂充填材の熱サイクルに伴う膨張，収縮
によって加えられる応力が外部導出導体８を介して金属
ベース２の間で相互干渉することが殆どなく、これによ
り金属ベース2,ないし金属ベース２と放熱板３との間に
介在するセラミック絶縁層などに加わる機械的なストレ
スを緩和できる。According to this structure, the tip of the external lead-out conductor 8 is bifurcated, so that the resin filler for sealing injected into the package (not shown) is added by expansion and contraction accompanying the thermal cycle. The stress hardly interferes with each other between the metal bases 2 via the externally derived conductors 8, so that the mechanical force applied to the metal base 2, or the ceramic insulating layer interposed between the metal base 2 and the heat dissipation plate 3 is increased. Stress can be relieved.
本発明の半導体装置は、以上説明したように構成され
ているので、次記の効果を奏する。Since the semiconductor device of the present invention is configured as described above, it has the following effects.
（１）半導体チップ，ないし金属ベースと外部導出導体
との間にそれぞれ介在させた補助接続導体片として、上
下両端に互いに並行な平板部を屈曲形成した補助接続導
体片を採用し、かつ該補助接続導体片の一方の平板部を
半導体チップの上面電極，ないし金属ベースに、他方の
平板部を外部導出導体の下端に屈曲形成した脚部に面接
触させて半田付け接合したことにより、外部導出導体と
補助接続導体片との間の半田付け工程で、外部導出導体
の位置が補助接続導体片に対して多少位置ずれがあって
も、外部導出導体の屈曲脚部と補助接続導体片の平板部
との間には面接触状態が保持されるので、これにより支
障なく両者間を確実に半田付け接合できる。しかも、半
田付けが水平な面同士の間で行われるので、溶融半田が
半田接合面から下方へ垂れ落ちるおそれはなく、これに
より半田付け不良，半導体チッウへの半田の滴下などの
トラブルを確実に回避して製品の歩留りを大幅に向上で
きる。(1) As the auxiliary connecting conductor pieces interposed between the semiconductor chip or the metal base and the external lead conductor, the auxiliary connecting conductor pieces in which flat plate portions parallel to each other are bent and formed at the upper and lower ends are adopted, and One side of the connecting conductor piece is connected to the upper surface electrode of the semiconductor chip or the metal base, and the other side of the plate portion is brought into surface contact with the leg portion bent at the lower end of the external lead-out conductor and soldered and joined to the external lead-out. In the soldering process between the conductor and the auxiliary connecting conductor piece, even if the position of the external lead conductor is slightly displaced from the auxiliary connecting conductor piece, the bent leg of the external lead conductor and the flat plate of the auxiliary connecting conductor piece Since the surface contact state is maintained between the parts, the two can be reliably soldered and joined together without any trouble. Moreover, since soldering is performed between horizontal surfaces, there is no risk of molten solder dripping downward from the solder joint surface, which ensures problems such as defective soldering and dropping of solder onto semiconductor chips. This can be avoided and the product yield can be greatly improved.
（２）また、半導体チップをマウントした金属ベースに
対して、そのベース板の側縁より上方に起立し、さらに
その上端をベース板面と平行に屈曲させた端子部を形成
し、該端子部の上面に外部導出導体の下端に屈曲形成し
た脚部を面接触させて半田付け接合することにより、前
記（１）と同様な効果を奏することができる。(2) Further, with respect to the metal base on which the semiconductor chip is mounted, a terminal portion is formed which is erected above the side edge of the base plate and whose upper end is bent parallel to the base plate surface. The same effect as in the above (1) can be obtained by surface-contacting the upper end of the leg portion bent and formed at the lower end of the outer lead conductor and soldering.
（３）前記（２）の構成において、金属ベースのベース
板周縁より上方に起立して半導体チップを取り囲む外周
側壁を形成し、その側壁上の一部に端子部を設けた構成
により、パッケージ内に注入した封止用の樹脂充填材の
熱サイクルに伴う膨張，収縮によって半導体チップに加
わるストレスを大幅に軽減できる。(3) In the structure of (2) above, an outer peripheral side wall that stands up above the periphery of the base plate of the metal base and surrounds the semiconductor chip is formed, and a terminal portion is provided on a part of the side wall. The stress applied to the semiconductor chip due to the expansion and contraction due to the thermal cycle of the sealing resin filler injected into the semiconductor chip can be greatly reduced.
（４）特に、隣り合う２個の半導体チップを対として各
半導体チップをマウントした金属ベースの双方にまたが
り外部導出導体を共通接続した構成のものに対し、各金
属ベースごとにベース板の側縁より起立して向かい合わ
せに並ぶ端子部を形成するとともに、該端子部に共通接
続する外部導出導体にはその下端に二股状に分岐した脚
部を屈曲形成し、かつ各分岐脚部を個々に金属ベース側
の端子部上面に面接触させて半田付け接合したことによ
り、パッケージ内に注入した樹脂充填材の膨張，収縮に
伴う応力が外部導出導体を介して双方の金属ベースの間
で相互に機械的に干渉し合うことがなくなり、これによ
り金属ベースなどに加わる応力の緩和が図れる。(4) In particular, for a structure in which two adjacent semiconductor chips are paired and the external lead conductors are commonly connected across both metal bases on which the semiconductor chips are mounted, the side edge of the base plate for each metal base. Further, the terminal portions are formed so as to stand upright and face each other, and the outer lead-out conductor commonly connected to the terminal portions is bent at its lower end to form a bifurcated leg portion, and each branch leg portion is individually formed. Since the upper surface of the terminal on the metal base side is brought into surface contact and soldered, the stress caused by the expansion and contraction of the resin filler injected into the package is mutually applied between the two metal bases via the external lead conductor. They do not mechanically interfere with each other, so that the stress applied to the metal base or the like can be relaxed.
第１図ないし第５図はそれぞれ異なる本発明の実施例を
示すものであり、第１図，第２図，第３図の（ａ），
（ｂ）はそれぞれ半導体装置の構成断面図、および補助
接続導体片の外形斜視図、第４図の（ａ），（ｂ）は一
部切欠した半導体装置の平面図，側面図、（ｃ）は等価
回路図、（ｄ）は要部の斜視構成図、第５図の（ａ），
（ｂ）は半導体装置の内部組立構造を示す平面図，側面
図、（ｃ）は外部導出導体の部分斜視図、（ｄ）は等価
回路図、第６図，第７図は従来の半導体装置の構造を示
し、第６図の（ａ），（ｂ），（ｃ）はそれぞれ組立断
面図，導体接続構造の部分斜視図，半田付け接合状態
図、第７図の（ａ），（ｂ）はそれぞれ組立断面図，導
体接続構造の部分斜視図、第８図は本発明装置の適用例
として挙げた三相全波ブリッジ回路図である。 1:半導体チップ、2:金属ベース、2a:端子部、2c:外周側
壁、3:放熱板、4:パッケージケース、6,7,8:外部導出導
体、8a,8b:分岐脚部、12,13,16:補助接続導体片。1 to 5 show different embodiments of the present invention, respectively, and are shown in FIGS. 1, 2, and 3 (a),
(B) is a sectional view of the structure of the semiconductor device, and an external perspective view of the auxiliary connecting conductor piece, (a) and (b) of FIG. 4 are a partially cutaway plan view, side view, and (c) of the semiconductor device, respectively. Is an equivalent circuit diagram, (d) is a perspective configuration diagram of a main part, (a) of FIG.
(B) is a plan view showing an internal assembly structure of a semiconductor device, a side view, (c) is a partial perspective view of an external lead conductor, (d) is an equivalent circuit diagram, and FIGS. 6 and 7 are conventional semiconductor devices. 6A, FIG. 6A, FIG. 6B, and FIG. 6C are assembly sectional views, a partial perspective view of a conductor connection structure, a soldering joint state diagram, and FIG. 7A and FIG. 8A and 8B are respectively an assembled sectional view, a partial perspective view of a conductor connection structure, and FIG. 1: semiconductor chip, 2: metal base, 2a: terminal part, 2c: outer peripheral side wall, 3: heat dissipation plate, 4: package case, 6, 7, 8: external lead conductor, 8a, 8b: branch leg part, 12, 13,16: Auxiliary connection conductor piece.
Claims (4)
ントしてパッケージに収容し、該パッケージに貫通装着
した外部導出導体と前記の各半導体チップ，および金属
ベースとの間を相互接続して構成した半導体装置におい
て、上下両端に互いに並行な平板部を屈曲形成した補助
接続導体片を前記半導体チップ，ないし金属ベースと外
部導出導体との間にそれぞれ介在させ、かつ該補助接続
導体片の一方の平板部を半導体チップの上面電極，ない
し金属ベースに、他方の平板部を外部導出導体の下端に
屈曲形成した脚部に面接触させて半田付け接合したこと
を特徴とする半導体装置。1. A structure in which a plurality of semiconductor chips are mounted on a metal base and accommodated in a package, and an external lead conductor penetratingly mounted in the package and each of the semiconductor chips and the metal base are interconnected. In the semiconductor device described above, the auxiliary connecting conductor pieces in which flat plate portions parallel to each other are bent and formed at the upper and lower ends are respectively interposed between the semiconductor chip or the metal base and the external lead conductor, and one of the auxiliary connecting conductor pieces is 2. A semiconductor device, wherein a flat plate portion is soldered to an upper surface electrode of a semiconductor chip, or a metal base, and the other flat plate portion is brought into surface contact with a leg portion bent and formed at a lower end of an external lead conductor.
にマウントしてパッケージに収容し、該パッケージに貫
通装着した外部導出導体と前記の各半導体チップ，およ
び金属ベースとの間を相互接続して構成した半導体装置
において、前記金属ベースにはベース板の側縁より上方
に起立し、さらにその上端をベース板面と平行に屈曲さ
せた端子部を形成し、該端子部の上面に外部導出導体の
下端に屈曲形成した脚部を面接触させて半田付け接合し
たことを特徴とする半導体装置。2. A plurality of semiconductor chips are individually mounted on a metal base and housed in a package, and an external lead conductor penetratingly mounted on the package and each of the semiconductor chips and the metal base are interconnected. In the semiconductor device configured as described above, a terminal portion is formed on the metal base, the terminal portion standing above the side edge of the base plate and having its upper end bent in parallel with the surface of the base plate. A semiconductor device characterized in that a bent leg portion of a conductor is brought into surface contact with each other and soldered and joined.
属ベースの端子部が、ベース板の周縁より上方に起立し
て半導体チップを取り囲む外周側壁の一部に形成されて
いることを特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein the terminal portion of the metal base is formed above a peripheral edge of the base plate and is formed on a part of an outer peripheral side wall surrounding the semiconductor chip. Semiconductor device.
にマウントしてパッケージに収容し、該パッケージに貫
通装着した外部導出導体と前記の各半導体チップ，およ
び金属ベースとの間を相互接続して構成した半導体装置
であり、隣り合う２個の半導体チップを対として、各半
導体チップをマウントした金属ベースの双方にまたがり
外部導出導体を共通接続したものにおいて、各金属ベー
スごとにベース板の側縁より起立して向かい合わせに並
ぶ端子部を形成するとともに、該端子部に共通接続する
外部導出導体にはその下端に二股状に分岐した脚部を屈
曲形成し、かつ各分岐脚部を個々に金属ベース側の端子
部上面に面接触させて半田付け接合したことを特徴とす
る半導体装置。4. A plurality of semiconductor chips are individually mounted on a metal base and housed in a package, and an external lead conductor penetratingly mounted on the package and each of the semiconductor chips and the metal base are interconnected. In the semiconductor device configured as described above, two adjacent semiconductor chips are paired, and the external lead conductor is commonly connected across both the metal bases on which the respective semiconductor chips are mounted. A terminal portion is formed standing upright from the edge and arranged facing each other, and a bifurcated leg portion is bent and formed at the lower end of the outer lead conductor commonly connected to the terminal portion, and each branch leg portion is individually formed. The semiconductor device is characterized in that the upper surface of the terminal portion on the metal base side is brought into surface contact with and soldered.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-109813 | 1989-09-20 | ||
| JP10981389 | 1989-09-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03174747A JPH03174747A (en) | 1991-07-29 |
| JP2560894B2 true JP2560894B2 (en) | 1996-12-04 |
Family
ID=14519860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19751290A Expired - Lifetime JP2560894B2 (en) | 1989-09-20 | 1990-07-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2560894B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227131A (en) * | 2007-03-13 | 2008-09-25 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| JPWO2015111691A1 (en) * | 2014-01-27 | 2017-03-23 | 三菱電機株式会社 | Electrode terminal, power semiconductor device, and method for manufacturing power semiconductor device |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0480065U (en) * | 1990-11-27 | 1992-07-13 | ||
| JP4620566B2 (en) * | 2005-10-07 | 2011-01-26 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| DE102006014582B4 (en) * | 2006-03-29 | 2011-09-15 | Infineon Technologies Ag | Semiconductor module |
| JP5103863B2 (en) | 2006-10-16 | 2012-12-19 | 富士電機株式会社 | Semiconductor device |
| JP2008205058A (en) * | 2007-02-19 | 2008-09-04 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| JP5034885B2 (en) * | 2007-11-14 | 2012-09-26 | 富士通株式会社 | Electronic device and method of manufacturing the same |
| JP5098951B2 (en) * | 2008-10-22 | 2012-12-12 | 富士電機株式会社 | Semiconductor device |
| JP5283277B2 (en) * | 2009-09-04 | 2013-09-04 | 日本インター株式会社 | Power semiconductor module |
| JP2012142622A (en) * | 2012-04-13 | 2012-07-26 | Fuji Electric Co Ltd | Semiconductor device |
| JP2016099127A (en) | 2014-11-18 | 2016-05-30 | 富士電機株式会社 | Manufacturing method of power semiconductor module and intermediate assembly unit thereof |
| DE112018007278T5 (en) * | 2018-03-14 | 2020-11-26 | Mitsubishi Electric Corporation | SEMI-CONDUCTOR POWER MODULE AND POWER CONVERTER |
-
1990
- 1990-07-25 JP JP19751290A patent/JP2560894B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008227131A (en) * | 2007-03-13 | 2008-09-25 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| JPWO2015111691A1 (en) * | 2014-01-27 | 2017-03-23 | 三菱電機株式会社 | Electrode terminal, power semiconductor device, and method for manufacturing power semiconductor device |
| US9899345B2 (en) | 2014-01-27 | 2018-02-20 | Mitsubishi Electric Cooperation | Electrode terminal, semiconductor device for electrical power, and method for manufacturing semiconductor device for electrical power |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03174747A (en) | 1991-07-29 |
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