JP2559757B2 - Hybrid board - Google Patents
Hybrid boardInfo
- Publication number
- JP2559757B2 JP2559757B2 JP62206808A JP20680887A JP2559757B2 JP 2559757 B2 JP2559757 B2 JP 2559757B2 JP 62206808 A JP62206808 A JP 62206808A JP 20680887 A JP20680887 A JP 20680887A JP 2559757 B2 JP2559757 B2 JP 2559757B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline
- grain size
- polycrystal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は微細なパターンを有する能動素子用のハイブ
リッド基板に関するものである。TECHNICAL FIELD The present invention relates to a hybrid substrate for active devices having a fine pattern.
［従来の技術］ 従来から、ベース基板上に多結晶膜を堆積した構成の
基板は存在した。例えば、石英基板上に、多結晶シリコ
ンを堆積して薄膜トランジスタを形成したものが実用化
されている。しかし、この例においては多結晶の粒径は
膜厚方向にわたってほぼ均一であった。[Prior Art] Conventionally, there has been a substrate having a structure in which a polycrystalline film is deposited on a base substrate. For example, a thin film transistor formed by depositing polycrystalline silicon on a quartz substrate has been put into practical use. However, in this example, the grain size of the polycrystal was almost uniform in the film thickness direction.
しかしながら、多結晶膜の膜厚を30μｍ以上と厚く堆
積した場合には、以下の様な問題点が生じる。However, when the polycrystalline film is thickly deposited to 30 μm or more, the following problems occur.
すなわち、粒径が例えば1000Å以下と細い時には、多
数の粒界の存在により熱伝導が悪くなり、基板表面に発
熱性の素子を構成する場合に問題となってくる。That is, when the grain size is as small as 1000 Å or less, the heat conduction is deteriorated due to the existence of many grain boundaries, which becomes a problem when a heat generating element is formed on the substrate surface.
また、粒径が例えば３μｍ以上と大きい時には、基板
表面の平坦性が著しく悪くなる。また、ベース基板と堆
積される多結晶との熱膨張係数の違いから、加熱堆積後
の冷却の工程で膜のヒビ割れや剥離が生じたりしてい
た。Further, when the particle size is large, for example, 3 μm or more, the flatness of the substrate surface is significantly deteriorated. Further, due to the difference in thermal expansion coefficient between the base substrate and the deposited polycrystal, cracking or peeling of the film occurs in the cooling step after heating and deposition.
［発明が解決しようとする問題点］ 本発明は以上説明したように、ベース基板上に多結晶
膜を30μｍ以上堆積した構成の基板において生じる問題
点をことごとく解決し、表面が平坦で、かつ、熱伝導性
の良好なハイブリッド基板を提供するものである。[Problems to be Solved by the Invention] As described above, the present invention solves all the problems that occur in a substrate having a structure in which a polycrystalline film is deposited to a thickness of 30 μm or more on a base substrate, has a flat surface, and A hybrid substrate having good thermal conductivity is provided.
［問題点を解決するための手段］ 本発明のハイブリッド基板は、セラミック基板上に、
当該セラミック基板と異種材料の多結晶の層を堆積させ
たハイブリッド基板において、前記多結晶の層は前記セ
ラミック基板側から順に第１の多結晶層、第２の多結晶
層及び第３の多結晶層の３層を有し、前記第２の多結晶
層の粒径が前記第１及び第３の多結晶層の粒径より大き
くされていることを特徴とする。[Means for Solving the Problems] The hybrid substrate of the present invention comprises a ceramic substrate,
In the hybrid substrate in which the ceramic substrate and a polycrystalline layer of a different material are deposited, the polycrystalline layer is a first polycrystalline layer, a second polycrystalline layer and a third polycrystalline layer in order from the ceramic substrate side. It has three layers, and the grain size of the second polycrystalline layer is larger than the grain sizes of the first and third polycrystalline layers.
［作用］ 第１図は本発明の構成を示すハイブリッド基板の一例
を示す断面構造である。セラミック基板１の表面に形成
された最下層２の多結晶は粒径が0.5μｍ以下と小さ
く、これは、セラミック基板表面のボイド等を埋めて、
さらに異種材料間の線膨張係数の差による歪を緩和して
いる。第２層３は粒径が２μｍ以上あり粒界が少なくな
っていて、高い熱伝導性を保持している。第３層４は粒
径が0.5μｍ以下と小さく基板表面の平坦性を向上させ
ている。[Operation] FIG. 1 is a cross-sectional structure showing an example of the hybrid substrate showing the configuration of the present invention. The polycrystal of the lowermost layer 2 formed on the surface of the ceramic substrate 1 has a small grain size of 0.5 μm or less, which fills voids and the like on the surface of the ceramic substrate.
Furthermore, the strain due to the difference in linear expansion coefficient between different materials is relaxed. The second layer 3 has a grain size of 2 μm or more and has few grain boundaries, and maintains high thermal conductivity. The third layer 4 has a small grain size of 0.5 μm or less and improves the flatness of the substrate surface.
従って、本発明のハイブリッド基板は、以上のように
膜厚方向に多結晶の粒径を変化させているために表面が
平坦で、かつ、熱伝導性が良好である。Therefore, the hybrid substrate of the present invention has a flat surface and good thermal conductivity because the grain size of the polycrystal is changed in the film thickness direction as described above.
［実施例］ 以下に本発明を実施例をあげて具体的に説明する。[Examples] The present invention will be specifically described below with reference to Examples.
第２図は、本発明のハイブリッド基板作成のためのシ
リコンエピ装置の概略図である。FIG. 2 is a schematic view of a silicon epi device for making a hybrid substrate of the present invention.
第２図において、石英ベルジャー５の中を真空ポンプ
によって排気して、そこにSiH2Cl2,HCl,H2を導入し減圧
状態でポリシリコン膜を堆積する。アルミナ基板６は高
周波コイル８によって加熱されたカーボンサセプター７
の上に保持されている。In FIG. 2, the inside of the quartz bell jar 5 is evacuated by a vacuum pump, SiH 2 Cl 2 , HCl, and H 2 are introduced therein, and a polysilicon film is deposited under a reduced pressure. The alumina substrate 6 is a carbon susceptor 7 heated by a high frequency coil 8.
Is held on.
次に堆積の過程を以下に述べる。 Next, the deposition process will be described below.
まず、アルミナ基板１を高温（900〜1100℃）に加熱
してHClを流して表面清浄化した後、H2で希釈したSiH2C
l2とHClの混合ガスの雰囲気下でポリシリコンを堆積す
る。First, the alumina substrate 1 is heated to a high temperature (900 to 1100 ° C.), HCl is flowed to clean the surface, and then SiH 2 C diluted with H 2 is used.
Polysilicon is deposited under an atmosphere of a mixed gas of l 2 and HCl.
各層の粒径の大きさは、各ガスの混合比、基板、高温
圧力によって制御することが出来る。The particle size of each layer can be controlled by the mixing ratio of each gas, the substrate, and the high temperature pressure.
第３図はHClの流量と粒径の関係を調べたものである
が、HClの流量がふえると粒径が大きくなる傾向を示し
ている。FIG. 3 shows the relationship between the flow rate of HCl and the particle size. It shows that the particle size tends to increase as the flow rate of HCl increases.
第４図は基板温度と粒径の関係を調べたものであるが
基板温度が高くなると粒径は小さくなっている。FIG. 4 shows the relationship between the substrate temperature and the grain size. The grain size decreases as the substrate temperature rises.
第５図は圧力と粒径の関係を調べたものであるが、圧
力が高くなると粒径は小さくなっている。FIG. 5 shows the relationship between the pressure and the particle size, and the particle size decreases as the pressure increases.
これらのパラメーターをコントロールすることによっ
て所望の粒径のポリシリコンを粒径を変化させながら積
層することが可能であり、所望のハイブリッド基板を得
ることができる。By controlling these parameters, it is possible to stack polysilicon having a desired particle size while changing the particle size, and a desired hybrid substrate can be obtained.
［発明の効果］ 以上説明したように、本発明によれば、表面平坦性の
悪いセラミック基板上へ、表面が平滑に多結晶膜を堆積
出来、しかも、熱伝導性の良好な高耐熱大面積基板が得
られる。[Effects of the Invention] As described above, according to the present invention, a polycrystalline film having a smooth surface can be deposited on a ceramic substrate having a poor surface flatness, and a high heat resistance large area having a good thermal conductivity. A substrate is obtained.
第１図は本発明の一例を示すセラミック／ポリシリコン
ハイブリッド基板の断面構造を示したものである。第２
図は粒径制御ポリシリコンを堆積させるエピ装置の概略
図である。第３図はポリシリコン粒径と原料ガス中のHC
l量の関係を示したグラフであり、第４図はポリシリコ
ン粒径と基板温度の関係を示したグラフである。また、
第５図はポリシリコン粒径と反応圧力の関係を示したグ
ラフである。 １……セラミック基板、２……粒径１μｍ以下の多結晶
層、３……粒径２μｍ以上の多結晶層、４……粒径0.5
μｍ以下の多結晶層、５……石英ベルジャー、６……ア
ルミナ基板、７……カーボンサセプタ、８……高周波コ
イル。FIG. 1 shows a sectional structure of a ceramic / polysilicon hybrid substrate showing an example of the present invention. Second
The figure is a schematic diagram of an epi device for depositing grain size controlled polysilicon. Figure 3 shows the grain size of polysilicon and HC in the source gas.
FIG. 4 is a graph showing the relationship between the amount of l and FIG. 4 is a graph showing the relationship between the polysilicon grain size and the substrate temperature. Also,
FIG. 5 is a graph showing the relationship between the polysilicon grain size and the reaction pressure. 1 ... ceramic substrate, 2 ... polycrystalline layer with grain size of 1 μm or less, 3 ... polycrystalline layer with grain size of 2 μm or more, 4 ... grain size 0.5
Polycrystalline layer of μm or less, 5 ... Quartz bell jar, 6 ... Alumina substrate, 7 ... Carbon susceptor, 8 ... High frequency coil.
Claims (7)
と異種材料の多結晶の層を堆積させたハイブリッド基板
において、前記多結晶の層は前記セラミック基板側から
順に第１の多結晶層、第２の多結晶層及び第３の多結晶
層の３層を有し、前記第２の多結晶層の粒径が前記第１
及び第３の多結晶層の粒径より大きくされていることを
特徴とするハイブリッド基板。1. A hybrid substrate in which a polycrystal layer of a different material is deposited on the ceramic substrate, wherein the polycrystal layer is a first polycrystal layer and a second polycrystal layer in order from the ceramic substrate side. Of the first polycrystalline layer and the third polycrystalline layer, wherein the grain size of the second polycrystalline layer is the same as that of the first polycrystalline layer.
And a grain size of the third polycrystalline layer larger than that of the third polycrystalline layer.
る前記第１の多結晶層の多結晶層の厚さが10μｍ以下で
あり、多結晶の粒径が１μｍ以下であることを特徴とす
る特許請求の範囲第１項に記載のハイブリッド基板。2. The thickness of the polycrystalline layer of the first polycrystalline layer, which is the lowermost layer deposited on the ceramic substrate, is 10 μm or less, and the grain size of the polycrystalline is 1 μm or less. The hybrid substrate according to claim 1.
厚さが10〜50μｍ以下であり、多結晶の粒径が２μｍ以
上であることを特徴とする特許請求の範囲第２項に記載
のハイブリッド基板。3. The second polycrystal layer laminated next to the bottom layer has a thickness of 10 to 50 μm or less, and the grain size of the polycrystal is 2 μm or more. The hybrid substrate according to item 2.
の粒径が0.5μｍ以下であることを特徴とする特許請求
の範囲第２項に記載のハイブリッド基板。4. The hybrid substrate according to claim 2, wherein the grain size of the polycrystal of the third polycrystal layer which is the uppermost layer is 0.5 μm or less.
結晶焼結体であることを特徴とする特許請求の範囲第１
項記載のハイブリッド基板。5. The ceramic substrate according to claim 1, wherein the ceramic substrate is an aluminum oxide polycrystalline sintered body.
The hybrid substrate according to the item.
を特徴とする特許請求の範囲第１項に記載のハイブリッ
ド基板。6. The hybrid substrate according to claim 1, wherein the polycrystalline layer is polysilicon.
許請求の範囲第１項に記載のハイブリッド基板。7. The hybrid substrate according to claim 1, wherein the layer thickness of the polycrystalline layer is 30 μm or more.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62206808A JP2559757B2 (en) | 1987-08-20 | 1987-08-20 | Hybrid board |
| EP88307734A EP0304337B1 (en) | 1987-08-20 | 1988-08-19 | Hybrid substrate |
| DE3851735T DE3851735T2 (en) | 1987-08-20 | 1988-08-19 | Hybrid substrate. |
| AU21460/88A AU621831B2 (en) | 1987-08-20 | 1988-08-22 | Ceramic base substrate wiyh a deposited multi-layer structure of a different material |
| US07/742,189 US5134018A (en) | 1987-08-20 | 1991-08-02 | Hybrid substrate |
| US07/884,178 US5232766A (en) | 1987-08-20 | 1992-05-18 | Hybrid substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62206808A JP2559757B2 (en) | 1987-08-20 | 1987-08-20 | Hybrid board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6450496A JPS6450496A (en) | 1989-02-27 |
| JP2559757B2 true JP2559757B2 (en) | 1996-12-04 |
Family
ID=16529431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62206808A Expired - Fee Related JP2559757B2 (en) | 1987-08-20 | 1987-08-20 | Hybrid board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2559757B2 (en) |
-
1987
- 1987-08-20 JP JP62206808A patent/JP2559757B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6450496A (en) | 1989-02-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |