JP2542650B2 - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JP2542650B2 JP2542650B2 JP62308659A JP30865987A JP2542650B2 JP 2542650 B2 JP2542650 B2 JP 2542650B2 JP 62308659 A JP62308659 A JP 62308659A JP 30865987 A JP30865987 A JP 30865987A JP 2542650 B2 JP2542650 B2 JP 2542650B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- metallized
- line pattern
- metallized layer
- aluminum nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は半導体回路用の回路基板に係り、特に窒化ア
ルミニウム基板を用いた回路基板に関する。Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to a circuit board for a semiconductor circuit, and more particularly to a circuit board using an aluminum nitride substrate.
（従来の技術） 従来、半導体回路基板として比較的安価なアルミナ
（Al2O3）基板を用いたものが多用されている。しか
し、近年、半導体装置の大出力化に伴って素子の発熱量
が増大し、これまでのAl2O3基板の放熱性では熱対策が
不十分となってきている。そこで最近では放熱性に優れ
た窒化アルミニウム（AlN）基板を用いた回路基板が利
用され始めている。(Prior Art) Conventionally, a semiconductor circuit board using a relatively inexpensive alumina (Al 2 O 3 ) board is widely used. However, in recent years, the amount of heat generated by the elements has increased with the increase in the output of semiconductor devices, and the heat dissipation measures of Al 2 O 3 substrates that have been used up to now have become insufficient heat countermeasures. Therefore, recently, a circuit board using an aluminum nitride (AlN) substrate having excellent heat dissipation properties has begun to be used.
このような回路基板では例えば第４図に示すように、
AlN基板１の表面にタングステン（Ｗ）またはモリブデ
ン（Mo）等のメタライズ層２を形成し、このメタライズ
層の表面にICチップ等の半導体素子３等を接合してい
る。In such a circuit board, for example, as shown in FIG.
A metallized layer 2 of tungsten (W) or molybdenum (Mo) is formed on the surface of the AlN substrate 1, and a semiconductor element 3 such as an IC chip is bonded to the surface of this metallized layer.
ところで、搭載する半導体素子３を大容量のものとし
た場合、回路基板の耐電圧効果をそれだけ高める必要が
あり、その一手段として第４図に示すように、AlN基板
１の外周部分を一定幅除いた部分にメタライズ層２を形
成することが考えられている。即ち、AlN基板１の周囲
に非メタライズ部分４を設け、周囲との絶縁性を高める
というものである。By the way, when the mounted semiconductor element 3 has a large capacity, it is necessary to enhance the withstand voltage effect of the circuit board, and as one means therefor, as shown in FIG. 4, the outer peripheral portion of the AlN substrate 1 has a constant width. It is considered to form the metallized layer 2 in the removed portion. That is, the non-metallized portion 4 is provided around the AlN substrate 1 to enhance the insulation with the surroundings.
（発明が解決しようとする問題点） しかしながら、非メタライズ部分４を設けた回路基板
にあっては、半導体素子３に過大な電圧が加わった場合
にその保護手段がなく、半導体素子３が破壊される可能
性がある。(Problems to be Solved by the Invention) However, in the circuit board provided with the non-metallized portion 4, when the semiconductor element 3 is applied with an excessive voltage, the semiconductor element 3 is destroyed without protection means. There is a possibility.
本発明はこのような事情に鑑みてなされたもので、比
較的簡単な手段で半導体素子等を過大電圧から保護する
ことができる回路基板を提供することを目的とする。The present invention has been made in view of such circumstances, and an object thereof is to provide a circuit board capable of protecting a semiconductor element or the like from an excessive voltage by a relatively simple means.
（問題点を解決するための手段） 本発明は窒化アルミニウム基板の表面の外周部分を一
定幅除いた部分にメタライズ層を形成した半導体回路用
の回路基板において、前記メタライズ層の周縁部の少な
くとも一個所から前記窒化アルミニウム基板の表面の非
メタライズ部分に線パターンをその基板の外周縁に向け
て突出させたことを特徴とする。(Means for Solving the Problems) The present invention relates to a circuit board for a semiconductor circuit in which a metallized layer is formed on a portion of the surface of an aluminum nitride substrate excluding an outer peripheral portion of a constant width, and at least one peripheral portion of the metallized layer is provided. It is characterized in that a line pattern is projected from a place to a non-metallized portion of the surface of the aluminum nitride substrate toward an outer peripheral edge of the substrate.
（作用） 本発明の回路基板によれば、メタライズ層の周縁部か
ら窒化アルミニウム基板表面の非メタライズ部分に線パ
ターンが突出しているので、メタライズ層に搭載した半
導体素子等に過大電圧が加わった場合には、線パターン
部からの放電によって電圧降下が促される。したがっ
て、半導体素子等を高電圧から保護できるようになる。
しかも、その保護手段はメタライズ層からの線パターン
の突出という比較的簡単なものであり、実施が極めて容
易に行なえる。(Function) According to the circuit board of the present invention, since the line pattern is projected from the peripheral portion of the metallized layer to the non-metallized portion of the surface of the aluminum nitride substrate, when an excessive voltage is applied to a semiconductor element or the like mounted on the metallized layer. , The voltage drop is promoted by the discharge from the line pattern portion. Therefore, the semiconductor element and the like can be protected from high voltage.
Moreover, the protection means is a relatively simple means of projecting the line pattern from the metallized layer, and can be implemented very easily.
（実施例） 以下、本発明の一実施例を第１図および第２図を参照
して説明する。(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
第１図は本発明の回路基板を示す斜視図、第２図はそ
の平面図である。FIG. 1 is a perspective view showing a circuit board of the present invention, and FIG. 2 is a plan view thereof.
この実施例の回路基板は、長方形状の窒化アルミニウ
ム（AlN）基板11の表面にタングステン（Ｗ）またはモ
リブデン（Mo）等のメタライズ層12が形成されている。
AlN基板11の熱伝導率は100W/m・Ｋとされている。In the circuit board of this embodiment, a metallized layer 12 of tungsten (W) or molybdenum (Mo) is formed on the surface of a rectangular aluminum nitride (AlN) substrate 11.
The thermal conductivity of the AlN substrate 11 is 100 W / m · K.
メタライズ層12は、AlN基板11の表面の外周部分を一
定幅除いた部分に長方形状に形成され、これによりメタ
ライズ層12の外周側にはAlN基板11の表面が直接表出す
る非メタライズ部分13が形成されている。The metallized layer 12 is formed in a rectangular shape in the outer peripheral portion of the surface of the AlN substrate 11 except for a constant width, whereby the non-metallized portion 13 where the surface of the AlN substrate 11 is directly exposed on the outer peripheral side of the metallized layer 12. Are formed.
そして、メタライズ層12の周縁の各辺縁部のそれぞれ
中央部分から小幅な線パターン14が一体的に突出し、こ
の線パターン14が非メタライズ部分13の表面上に沿い、
AlN基板11の外周縁部まで延在している。Then, a narrow line pattern 14 is integrally projected from the central portion of each of the peripheral edge portions of the metallized layer 12, the line pattern 14 along the surface of the non-metallized portion 13,
It extends to the outer peripheral edge of the AlN substrate 11.
メタライズ層12の表面中央部分には、半導体回路素
子、例えばICチップ15が搭載され、図示しないがメタラ
イズ層12に装着され電極を兼ねるリードフレーム等と接
合される。A semiconductor circuit element, for example, an IC chip 15 is mounted on the central portion of the surface of the metallization layer 12, and is bonded to a lead frame or the like which is mounted on the metallization layer 12 and which also serves as an electrode (not shown).
このような構成によると、ICチップ15に瞬間的に過度
の高電圧が加わったような場合、線パターン14がAlN基
板11の外周縁部に表出しているので、その部分で放電が
行なわれ、これにより電圧降下が促される。したがっ
て、ICチップ15が高電圧から保護される。According to such a configuration, when an excessively high voltage is momentarily applied to the IC chip 15, the line pattern 14 is exposed at the outer peripheral edge portion of the AlN substrate 11, and therefore discharge is performed at that portion. As a result, a voltage drop is promoted. Therefore, the IC chip 15 is protected from high voltage.
また、前記構成によると、線パターン14はメタライズ
層12から一体的に突出したものであるから、例えば多数
のメタライズ用材料板を接続脚で一体成形しておき、そ
の接続脚を切断することにより線パターン14付きのメタ
ライズ材とする等の簡単な構成で得られるので、その実
施が容易に行なえる。Further, according to the above-mentioned configuration, since the line pattern 14 is integrally projected from the metallization layer 12, for example, a large number of metallizing material plates are integrally molded with the connecting legs, and the connecting legs are cut. Since it can be obtained with a simple structure such as a metallized material with the line pattern 14, its implementation can be easily performed.
なお、前記実施例では、線パターン14を長方形状のメ
タライズ層12の外周各辺縁部中央からそれぞれ突出する
ものとして合計４本設けたが、本発明は必ずしもそのよ
うなものに限らず、線パターン14の配置、本数等につい
ては任意に設定することができる。In addition, in the above-mentioned embodiment, the line pattern 14 is provided as a total of four pieces projecting from the center of each peripheral edge portion of the rectangular metallized layer 12, but the present invention is not limited to such a case, and the line pattern 14 is not limited to this. The arrangement and the number of the patterns 14 can be set arbitrarily.
例えば第３図は本発明の他の実施例を示し、線パター
ン14をメタライズ層12の周縁一個所から１本のみ突出さ
せたものである。For example, FIG. 3 shows another embodiment of the present invention, in which only one line pattern 14 is projected from one peripheral edge of the metallized layer 12.
このような構成によっても、前記実施例と略同様の効
果が奏される。With such a configuration, the same effect as that of the above-described embodiment can be obtained.
また、図示しないが線パターンを２本、３本あるいは
他の本数突出させてもよく、さらにその突出位置はメタ
ライズ層の隅角部から突出させるようにしてもよい。Although not shown, two, three, or other line patterns may be projected, and the projecting position may be projected from the corner portion of the metallization layer.
以上のように、本発明によれば、窒化アルミニウム基
板の表面周縁の非メタライズ部分に線パターンが突出さ
せるという比較的簡単な構成で放電等を可能とし、それ
により過大電圧から半導体素子等を保護することがで
き、半導体用回路の大容量化に対処するうえで極めて有
効なものとなる。As described above, according to the present invention, it is possible to perform discharge or the like with a relatively simple structure in which the line pattern is projected on the non-metallized portion of the surface periphery of the aluminum nitride substrate, thereby protecting the semiconductor element or the like from excessive voltage. This is extremely effective in dealing with the increase in capacity of semiconductor circuits.
第１図は本発明に係る回路基板の一実施例を示す斜視
図、第２図は平面図、第３図は本発明の他の実施例を示
す平面図、第４図は従来例を示す斜視図である。 11……窒化アルミニウム基板、12……メタライズ層、13
……非メタライズ部分、14……線パターン、15……ICチ
ップ（半導体素子）。FIG. 1 is a perspective view showing an embodiment of a circuit board according to the present invention, FIG. 2 is a plan view, FIG. 3 is a plan view showing another embodiment of the present invention, and FIG. 4 is a conventional example. It is a perspective view. 11 …… Aluminum nitride substrate, 12 …… Metalized layer, 13
…… Unmetallized area, 14 …… Line pattern, 15 …… IC chip (semiconductor element).
Claims (1)
一定幅除いた部分にメタライズ層を形成した半導体回路
用の回路基板において、前記メタライズ層の周縁部の少
なくとも一個所から前記窒化アルミニウム基板の表面の
非メタライズ部分に線パターンをその基板の外周縁に向
けて突出させたことを特徴とする回路基板。1. A circuit board for a semiconductor circuit, wherein a metallized layer is formed on a portion of the surface of the aluminum nitride substrate excluding an outer peripheral portion with a constant width, wherein the surface of the aluminum nitride substrate is located at least at one peripheral edge of the metallized layer. A circuit board, wherein a line pattern is projected on the non-metallized portion of the board toward the outer peripheral edge of the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62308659A JP2542650B2 (en) | 1987-12-08 | 1987-12-08 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62308659A JP2542650B2 (en) | 1987-12-08 | 1987-12-08 | Circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01150381A JPH01150381A (en) | 1989-06-13 |
| JP2542650B2 true JP2542650B2 (en) | 1996-10-09 |
Family
ID=17983738
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62308659A Expired - Lifetime JP2542650B2 (en) | 1987-12-08 | 1987-12-08 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2542650B2 (en) |
-
1987
- 1987-12-08 JP JP62308659A patent/JP2542650B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01150381A (en) | 1989-06-13 |
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Legal Events
| Date | Code | Title | Description |
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