JP2532601B2 - Frequency modulation circuit - Google Patents
Frequency modulation circuitInfo
- Publication number
- JP2532601B2 JP2532601B2 JP63210224A JP21022488A JP2532601B2 JP 2532601 B2 JP2532601 B2 JP 2532601B2 JP 63210224 A JP63210224 A JP 63210224A JP 21022488 A JP21022488 A JP 21022488A JP 2532601 B2 JP2532601 B2 JP 2532601B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- digital
- modulation circuit
- frequency
- frequency modulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、入力データに応じて出力の周波数を変化さ
せる周波数変調回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency modulation circuit that changes an output frequency according to input data.
従来の技術 第２図は、従来の周波数変調回路の一例のブロック図
である。この例では、ディジタル積分手段を用いて、周
波数変調を行っている。つまり、加算手段10の出力を遅
延手段11で遅らせた後、前記加算手段10の入力に戻し、
入力データと加算する事により入力データを積分させ
る。加算手段の出力が、その桁あふれによって、入力デ
ータに応じた周期の鋸歯状波になる事を利用している。
加算手段の語長をｎビット、遅延手段の遅延時間をｔと
すると、出力周波数は、入力データ/2n/t（入力データ
＜2n-1）と表す事ができる。SIN変換手段12は、出力の
高調波成分を少なくさせる為のものである。（例えば、
「ディジタル信号処理の応用」電子通信学会編集p105） 発明が解決しようとする課題 上記の例では、高い周波数の出力を得ようとすると、
加算手段の語長ｎを少な目に選ぶ、または遅延手段の遅
延時間を短くする必要があった。しかし語長ｎを少な目
にすると、出力のジッタが増加する欠点があった。又、
遅延手段をディジタル的に、１クロック分、ラッチ回路
で遅らせる様に構成すると、遅延時間を短くする為に、
非常に高いクロックを必要とした。2. Description of the Related Art FIG. 2 is a block diagram of an example of a conventional frequency modulation circuit. In this example, frequency modulation is performed using digital integration means. That is, after delaying the output of the adding means 10 by the delay means 11, it is returned to the input of the adding means 10,
The input data is integrated by adding it to the input data. It is utilized that the output of the adding means becomes a sawtooth wave having a period corresponding to the input data due to the overflow.
When the word length of the adding means is n bits and the delay time of the delay means is t, the output frequency can be expressed as input data / 2 n / t (input data <2 n-1 ). The SIN conversion means 12 is for reducing the harmonic components of the output. (For example,
"Application of Digital Signal Processing" edited by IEICE p105) Problems to be solved by the invention In the above example, when an output of high frequency is obtained,
It was necessary to select a small word length n of the adding means or to shorten the delay time of the delay means. However, if the word length n is reduced, the output jitter increases. or,
If the delay means is digitally delayed by one clock by the latch circuit, in order to shorten the delay time,
Needed a very high clock.
課題を解決するための手段 上記課題を解決するために、本発明の周波数変調回路
は、入力値を積分するディジタル積分手段と、定周波数
のディジタル信号を発生する信号発生手段と、前記ディ
ジタル積分手段の出力と前記信号発生手段の出力を掛け
合わせるディジタルの乗算手段と、前記乗算手段の出力
から、所望の周波数成分を取り出すアナログの帯域通過
フィルタを具備して構成したものである。Means for Solving the Problems In order to solve the above problems, a frequency modulation circuit of the present invention includes a digital integrating means for integrating an input value, a signal generating means for generating a digital signal of a constant frequency, and the digital integrating means. And a digital multiplication means for multiplying the output of the signal generation means with the output of the signal generation means, and an analog bandpass filter for extracting a desired frequency component from the output of the multiplication means.
作用 本発明は、上記した構成によって、出力ジッタの少な
い、LSI化に適した周波数変調回路を提供することがで
きる。Effects The present invention can provide a frequency modulation circuit having a small output jitter and suitable for use in an LSI with the above configuration.
実施例 以下、本発明の一実施例の周波数変調回路について、
図面を参照しながら説明する。第１図は、本発明を適用
した周波数変調回路のブロック図である。１は信号発生
手段、２はディジタル積分手段、３は乗算手段、４は帯
域通過フィルタである。ディジタル積分手段２は、従来
例で説明したとおりで、積分値が桁あふれによって、入
力データに応じた周波数f2の鋸歯状波になる事を利用す
るものである。Example Hereinafter, regarding the frequency modulation circuit of one example of the present invention,
This will be described with reference to the drawings. FIG. 1 is a block diagram of a frequency modulation circuit to which the present invention is applied. Reference numeral 1 is a signal generating means, 2 is a digital integrating means, 3 is a multiplying means, and 4 is a band pass filter. As described in the conventional example, the digital integrator 2 utilizes the fact that the integrated value becomes a sawtooth wave having a frequency f2 according to the input data due to overflow.
信号発生手段１より出力された周波数f1のディジタル
信号と、ディジタル積分手段から出力された周波数f2の
ディジタル信号は、乗算手段３に入力された掛け合わさ
れた後、帯域通過フィルタ４に入力されてf1＋f2、また
はf1−f2の成分が取り出される。乗算手段の入力は、純
粋なSIN波ではないが、ここではその基本波を考え、出
力の周波数を動かすことができる事を説明する。信号発
生手段の出力の基本波をSIN（２＊π＊f1＊ｔ）、ディ
ジタル積分手段の出力の基本波をSIN（２＊π＊f2＊
ｔ）とすると乗算の結果、COS（２＊π＊（f1＋f2）＊
ｔ）の和の周波数の成分と、COS（２＊π＊（f1−f2）
＊ｔ）の差の周波数の成分が現れる。すなわち、低い周
波数f2で周波数をδｆずらすことにより、f1＋f2また
は、f1−f2の高い周波数領域で、周波数を同じδｆだけ
ずらすことができる事を示している。したがって、±δ
ｆの通過帯域幅の帯域通過フィルタで、どちらかの成分
のみをとりだせば、望みの周波数で周波数を容易に制御
する事ができる。なお、実際には、入力は、純粋なSIN
波でないので、乗算の後では、f2（一般には、２＊f2）
おきにスプリアス成分が存在する。そのうちどれを用い
てもかまわない。又、低い周波数領域で、ディジタル積
分手段を用いているので、加算語長を長くとる事がで
き、出力ジッタを、非常に小さくできる。そのため、デ
ィジタル積分手段の出力語長を短くする事ができる。SI
N変換手段がいらない等の利点がある。特に、積分手段
の出力語長を１ビットにすると、乗算手段３は単に排他
的論理和、論理積、論理和などのゲート回路でよい。The digital signal of the frequency f1 output from the signal generating means 1 and the digital signal of the frequency f2 output from the digital integrating means are input to the multiplying means 3 and, after being multiplied, are input to the band pass filter 4 to be f1 + f2. , Or f1-f2 components are taken out. The input of the multiplication means is not a pure SIN wave, but here we will consider its fundamental wave and explain that the frequency of the output can be moved. The fundamental wave output from the signal generating means is SIN (2 * π * f1 * t), and the fundamental wave output from the digital integrating means is SIN (2 * π * f2 *).
t), the result of the multiplication is COS (2 * π * (f1 + f2) *
t) sum frequency component and COS (2 * π * (f1-f2)
The frequency component of the difference of * t) appears. That is, it is shown that by shifting the frequency by δf at the low frequency f2, the frequency can be shifted by the same δf in the high frequency region of f1 + f2 or f1−f2. Therefore, ± δ
With a bandpass filter having a passband width of f, if only one of the components is taken out, the frequency can be easily controlled at a desired frequency. Note that in reality, the input is a pure SIN
Since it is not a wave, after multiplication, f2 (generally 2 * f2)
There are spurious components every second. It doesn't matter which one you use. Further, since the digital integrating means is used in the low frequency region, the added word length can be made long and the output jitter can be made extremely small. Therefore, the output word length of the digital integrating means can be shortened. SI
There are advantages such as not requiring N conversion means. In particular, when the output word length of the integrating means is 1 bit, the multiplying means 3 may simply be a gate circuit such as an exclusive OR, an AND, or an OR.
発明の効果 以上のように、本発明によれば、最小限のアナログ回
路で構成する事ができ、高いクロックも必要としないの
で、LSI化が非常に容易になり、ジッタの少ない、安定
な周波数変調回路を提供する事ができる。As described above, according to the present invention, since it can be configured with a minimum of analog circuits and does not require a high clock, it is very easy to make an LSI, and a stable frequency with little jitter is provided. A modulation circuit can be provided.
第１図は、本発明を適用した周波数変調回路のブロック
図、第２図は、従来の周波数変調回路のブロック図であ
る。 ２……ディジタル積分手段、３……乗算手段、４……帯
域通過フィルタ。FIG. 1 is a block diagram of a frequency modulation circuit to which the present invention is applied, and FIG. 2 is a block diagram of a conventional frequency modulation circuit. 2 ... Digital integration means, 3 ... Multiplication means, 4 ... Bandpass filter.
Claims (3)
定周波数のディジタル信号を発生する信号発生手段と、
前記ディジタル積分手段の出力と前記信号発生手段の出
力を掛け合わせるディジタルの乗算手段と、前記乗算手
段の出力から、所望の周波数成分を取り出すアナログの
帯域通過フィルタを具備した周波数変調回路。1. Digital integrating means for integrating an input value,
Signal generating means for generating a constant frequency digital signal,
A frequency modulation circuit comprising a digital multiplication means for multiplying the output of the digital integration means and the output of the signal generation means, and an analog bandpass filter for extracting a desired frequency component from the output of the multiplication means.
を加算する加算手段と、前記加算手段の出力を一定時間
遅らせる遅延手段を具備し、前記遅延手段の出力を帰還
値とし、前記ディジタル積分手段の出力を、前記加算手
段もしくは前記ラッチ手段の出力の、全部もしくは一部
とすることを特徴とする請求項（１）記載の周波数変調
回路。2. The digital integrating means comprises an adding means for adding a feedback value and an input value, and a delay means for delaying the output of the adding means by a fixed time, and the output of the delay means is used as a feedback value, and the digital value The frequency modulation circuit according to claim 1, wherein the output of the integrating means is the whole or a part of the output of the adding means or the latch means.
であり、乗算手段は、ひとつのゲート回路よりなること
を特徴とする請求項（１）記載の周波数変調回路。3. The frequency modulation circuit according to claim 1, wherein the output word length of the digital integrating means is 1 bit, and the multiplying means comprises one gate circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63210224A JP2532601B2 (en) | 1988-08-24 | 1988-08-24 | Frequency modulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63210224A JP2532601B2 (en) | 1988-08-24 | 1988-08-24 | Frequency modulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0258947A JPH0258947A (en) | 1990-02-28 |
| JP2532601B2 true JP2532601B2 (en) | 1996-09-11 |
Family
ID=16585844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63210224A Expired - Fee Related JP2532601B2 (en) | 1988-08-24 | 1988-08-24 | Frequency modulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2532601B2 (en) |
-
1988
- 1988-08-24 JP JP63210224A patent/JP2532601B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0258947A (en) | 1990-02-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |