JP2529993B2 - Dielectric isolation structure integrated circuit - Google Patents
Dielectric isolation structure integrated circuitInfo
- Publication number
- JP2529993B2 JP2529993B2 JP63062187A JP6218788A JP2529993B2 JP 2529993 B2 JP2529993 B2 JP 2529993B2 JP 63062187 A JP63062187 A JP 63062187A JP 6218788 A JP6218788 A JP 6218788A JP 2529993 B2 JP2529993 B2 JP 2529993B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- type
- polycrystalline silicon
- region
- dielectric isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Element Separation (AREA)
Description
【発明の詳細な説明】 〔概要〕 誘電体分離構造の集積回路に関し、 基板電位を製造上安定に固定することを目的とし、 基板に多結晶シリコンを用い該基板にＮ形及びＰ形の
不純物拡散領域をそれぞれ少なくとも１個所づつ設け、
該拡散領域に共通に接続する電極を形成して基板に電位
を与えるようにする。The present invention relates to an integrated circuit having a dielectric isolation structure, in which polycrystalline silicon is used as a substrate and N-type and P-type impurities are used as a substrate for the purpose of stably fixing the substrate potential during manufacturing. Provide at least one diffusion area each,
An electrode commonly connected to the diffusion region is formed to apply a potential to the substrate.
〔産業上の利用分野〕 本発明は、誘電体分離構造のIC、特に多結晶シリコン
基板電位を製造上安定に固定できる構造を有するICに関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC having a dielectric isolation structure, particularly to an IC having a structure capable of stably fixing the potential of a polycrystalline silicon substrate during manufacturing.
半導体ICに於いて、現在その各素子間の分離のため
に、通常PN接合分離方法が用いられているが、高集積化
に伴なって、誘電体絶縁分離方法も実施されている。In semiconductor ICs, the PN junction isolation method is usually used for the isolation between the respective elements, but the dielectric insulation isolation method is also implemented as the integration becomes higher.
この誘電体分離方法によるICの一例を第３図に示す。 An example of an IC using this dielectric isolation method is shown in FIG.
図に於いて、１は多結晶シリコン基板、２はダイオー
ド素子領域、３はトランジスタ素子領域、４は抵抗素子
領域、5,6は酸化膜、７〜14は拡散領域、15〜21は各電
極である。In the figure, 1 is a polycrystalline silicon substrate, 2 is a diode element region, 3 is a transistor element region, 4 is a resistance element region, 5 and 6 are oxide films, 7 to 14 are diffusion regions, and 15 to 21 are electrodes. Is.
このような構造のICを製造するためには、単結晶半導
体の裏面に各素子領域を分離するためのＶ溝を形成し、
Ｖ溝及び単結晶半導体裏面上に酸化膜５を介して多結晶
シリコン１を形成し、これを基板とする。表面はＶ溝の
先端迄エッチング除去し、酸化膜６を形成し、これに窓
開けをし、その部分から不純物を拡散して、拡散領域７
〜14を形成し電極15〜21を蒸着して各素子を形成する。
第４図はその一例としてダイオード，トランジスタ，抵
抗を示してある。In order to manufacture an IC having such a structure, a V groove for separating each element region is formed on the back surface of a single crystal semiconductor,
Polycrystalline silicon 1 is formed on the V-groove and the back surface of the single crystal semiconductor via an oxide film 5, and this is used as a substrate. The surface is removed by etching up to the tip of the V groove, an oxide film 6 is formed, a window is opened in this, and impurities are diffused from that portion to form a diffusion region 7.
14 to 14 and electrodes 15 to 21 are vapor-deposited to form each element.
FIG. 4 shows a diode, a transistor and a resistor as an example.
この誘電体分離方法での基板（通常は多結晶シリコ
ン）は通常電気的には全く浮遊させて使われているが、
このため基板上の各素子間には誘電体部５の静電容量に
よる結合があり、数MHz以上の高周波領域や、数十Ｖ以
上の大振幅信号の漏れが問題となる。この素子間の信号
漏れをなくすためには、基板に電極を設け、この電極を
接地又は定電位に固定する必要がある。The substrate (usually polycrystalline silicon) used in this dielectric isolation method is usually electrically suspended and used,
For this reason, there is a coupling between the respective elements on the substrate due to the electrostatic capacitance of the dielectric portion 5, which causes a problem of a high frequency region of several MHz or more and leakage of a large amplitude signal of several tens of V or more. In order to eliminate the signal leakage between the elements, it is necessary to provide an electrode on the substrate and fix this electrode to the ground or a constant potential.
従来の誘電体絶縁分離プロセスにおいては、その多結
晶シリコンを利用した支持基板を接地するために第４図
に示すように多結晶シリコン基板１の表面に高濃度の不
純物拡散領域25を設け、その領域に電極26を形成して接
地することにより誘電体絶縁層５を取囲む多結晶シリコ
ン基板１を接地し、各素子27間の静電結合を除くことが
提案されている〔特公昭56−35395参照〕。In the conventional dielectric isolation process, a high-concentration impurity diffusion region 25 is provided on the surface of the polycrystalline silicon substrate 1 as shown in FIG. 4 in order to ground the supporting substrate using the polycrystalline silicon. It has been proposed to ground the polycrystalline silicon substrate 1 surrounding the dielectric insulating layer 5 by forming an electrode 26 in the region and grounding it to eliminate the electrostatic coupling between the elements 27 [Japanese Patent Publication No. 35395].
ところが、支持基板となる多結晶シリコンは、特に不
純物をドープすることなく成長すると通常Ｎ形,P形のど
ちらとなるかが不安定となるため、高濃度拡散領域と同
一タイプの不純物を成長時に加えなければ接合ができて
しまい、基板を安定に接地することができないと云う問
題があった。However, since the polycrystalline silicon serving as the supporting substrate normally becomes N-type or P-type when grown without doping impurities, it becomes unstable. Therefore, impurities of the same type as the high-concentration diffusion region are grown at the time of growth. If it is not added, bonding is possible, and there is a problem that the substrate cannot be grounded stably.
本発明は、上記多結晶シリコン基板を形成・成長させ
る工程で、特に不純物を添加しなくても安定に基板電位
を固定できる方法を提供することを目的とする。An object of the present invention is to provide a method capable of stably fixing the substrate potential in the step of forming / growing the above-mentioned polycrystalline silicon substrate without adding any impurities.
本発明は上記課題を解決するために、基板に多結晶シ
リコンを用い該基板にＮ形及びＰ形の不純物拡散領域を
それぞれ少くとも１個所づつ設け、該拡散領域に共通に
接続する電極を形成して基板に電位を与えるようにした
ことを特徴とする。In order to solve the above-mentioned problems, the present invention uses polycrystalline silicon for a substrate, provides at least one N-type and P-type impurity diffusion region on each substrate, and forms an electrode commonly connected to the diffusion region. It is characterized in that a potential is applied to the substrate.
第１図及び第２図は本発明の原理及び実施例を説明す
る図であり、Ｎ形及びＰ形の高濃度不純物拡散領域31,3
2をそれぞれ設けそれらの拡散領域31,32に共通に電極26
を接続して、基板１に電位を与えるものである。1 and 2 are diagrams for explaining the principle and embodiment of the present invention, in which N-type and P-type high-concentration impurity diffusion regions 31, 3 are formed.
2 are provided respectively and the electrodes 26 are commonly used in the diffusion regions 31 and 32.
Is connected to give a potential to the substrate 1.
本発明では、第１図の如くＮ形,P形両方の高濃度不純
物拡散領域31,32を設けることにより、基板として形成
された多結晶シリコン１がＮ形,P形のいづれのタイプと
なっていても、高濃度不純物拡散領域31,32の一方とはP
N接合が形成されるが他の一方とは必らず安定な接続が
可能となるようにしている。In the present invention, by providing the N-type and P-type high-concentration impurity diffusion regions 31 and 32 as shown in FIG. 1, the polycrystalline silicon 1 formed as the substrate becomes either N-type or P-type. However, one of the high-concentration impurity diffusion regions 31 and 32 is P
Although an N-junction is formed, it is inevitably connected to the other one so that a stable connection is possible.
従って、多結晶シリコン基板の成長時に特に不純物を
添加する必要なく安定に基板の電位を固定することが可
能となる。Therefore, it becomes possible to stably fix the potential of the substrate without the need to add impurities during the growth of the polycrystalline silicon substrate.
以下第１図，第２図によって本発明の実施例を説明す
る。An embodiment of the present invention will be described below with reference to FIGS.
シリコン単結晶27に溝を形成する。これは単結晶27の
図示していない各素子領域分離用の溝形成と同時に行な
われる。溝形成に際しては結晶方位＜100＞の基板で素
子底部となる部分をマスクし、KOH溶液中についてエッ
チングする。次に酸化膜５を厚さ１〜５μｍに形成し、
1100℃〜1300℃でSiHCl3又はSiCl4等のガスによる気相
成長により多結晶シリコンを成長させて基板１とする。A groove is formed in the silicon single crystal 27. This is performed at the same time as the formation of trenches (not shown) for isolating each element region of the single crystal 27. At the time of forming the groove, a substrate having a crystal orientation of <100> is used as a mask for the portion to be the bottom of the device, and etching is performed in a KOH solution. Next, an oxide film 5 is formed to a thickness of 1 to 5 μm,
A substrate 1 is formed by growing polycrystalline silicon by vapor phase growth using a gas such as SiHCl 3 or SiCl 4 at 1100 ° C. to 1300 ° C.
次に単結晶27の表面をポリシングを行い、多結晶領域
１が表出する迄研削する。Next, the surface of the single crystal 27 is polished and ground until the polycrystalline region 1 is exposed.
次に酸化膜６を形成し、それに拡散窓を開け、Ｎ形不
純物及びＰ形不純物をそれぞれイオン注入或いは拡散法
により注入し、Ｎ形高濃度領域31,P形高濃度領域32を形
成する。Ｎ形不純物としてはリン等が使用でき、濃度は
1.0×1019〜1.0×1021/cm3程度とし、Ｐ形不純物として
はボロン等が使用でき、濃度は1.0×1018〜1.0×1020/c
m3程度とする。Next, an oxide film 6 is formed, a diffusion window is opened therein, and N-type impurities and P-type impurities are injected by ion implantation or diffusion, respectively, to form an N-type high concentration region 31 and a P-type high concentration region 32. Phosphorus can be used as the N-type impurity, and the concentration is
1.0 × 10 19 to 1.0 × 10 21 / cm 3 and boron can be used as a P-type impurity with a concentration of 1.0 × 10 18 to 1.0 × 10 20 / c
It is about m 3 .
最後にこれらＰ形及びＮ形不純物領域31,32に接続す
るようにアルミ電極26を形成する。なおＮ形不純物領域
31とＰ形不純物領域32は、第１図のように互いに接触し
ていても第２図のように分離していてもよい。Finally, the aluminum electrode 26 is formed so as to be connected to the P-type and N-type impurity regions 31 and 32. N-type impurity region
31 and the P-type impurity region 32 may be in contact with each other as shown in FIG. 1 or separated as shown in FIG.
表面の電極から与えられた電位は、Ｎ形,P形のどちら
の高濃度不純物拡散領域ともオーミックに接続され、さ
らに多結晶シリコン基板の不純物タイプがどちらの不純
物タイプとなっても、上記高濃度不純物拡散領域のどち
らかと同一タイプとなるため、安定に基板に電位を与え
ることができる。The potential applied from the electrode on the surface is ohmic-connected to both the N-type and P-type high-concentration impurity diffusion regions, and even if the impurity type of the polycrystalline silicon substrate is either of the above-mentioned high-concentration Since it is of the same type as either of the impurity diffusion regions, it is possible to stably apply a potential to the substrate.
第１図及び第２図は本発明の原理説明及び実施例の説明
用断面図、第３図及び第４図は従来例の説明用の断面図
である。 図に於いて、１は多結晶半導体基板、2,3,4は単結晶素
子領域、5,6は絶縁膜、７〜14は各素子用拡散領域、15
〜21は各素子用電極、25は拡散領域、26は電極、27は単
結晶素子領域、31はＮ形不純物拡散領域、32はＰ形不純
物拡散領域である。1 and 2 are sectional views for explaining the principle of the present invention and an embodiment of the present invention, and FIGS. 3 and 4 are sectional views for explaining a conventional example. In the figure, 1 is a polycrystalline semiconductor substrate, 2, 3 and 4 are single crystal element regions, 5 and 6 are insulating films, 7 to 14 are diffusion regions for each element, 15
Numeral 21 is an electrode for each element, 25 is a diffusion region, 26 is an electrode, 27 is a single crystal element region, 31 is an N-type impurity diffusion region, and 32 is a P-type impurity diffusion region.
Claims (1)
形及びＰ形の不純物拡散領域をそれぞれ少なくとも１個
所づつ設け、該拡散領域に共通に接続する電極を形成し
て基板に電位を与えるようにしたことを特徴とする誘電
体分離構造集積回路。1. A substrate is made of polycrystalline silicon, and N is used as the substrate.
And at least one impurity diffusion region of P-type and P-type impurity diffusion region respectively are provided, and an electrode commonly connected to the diffusion region is formed to apply a potential to the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63062187A JP2529993B2 (en) | 1988-03-16 | 1988-03-16 | Dielectric isolation structure integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63062187A JP2529993B2 (en) | 1988-03-16 | 1988-03-16 | Dielectric isolation structure integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01235346A JPH01235346A (en) | 1989-09-20 |
| JP2529993B2 true JP2529993B2 (en) | 1996-09-04 |
Family
ID=13192884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63062187A Expired - Fee Related JP2529993B2 (en) | 1988-03-16 | 1988-03-16 | Dielectric isolation structure integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2529993B2 (en) |
-
1988
- 1988-03-16 JP JP63062187A patent/JP2529993B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01235346A (en) | 1989-09-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |