JP2520957B2 - Semiconductor memory device testing method - Google Patents
Semiconductor memory device testing methodInfo
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- JP2520957B2 JP2520957B2 JP1054993A JP5499389A JP2520957B2 JP 2520957 B2 JP2520957 B2 JP 2520957B2 JP 1054993 A JP1054993 A JP 1054993A JP 5499389 A JP5499389 A JP 5499389A JP 2520957 B2 JP2520957 B2 JP 2520957B2
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- voltage
- power supply
- substrate
- memory cell
- supply voltage
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Description
【発明の詳細な説明】 〔概 要〕 スタティック型半導体記憶装置の記憶保持性能の試験
方法に関し、 不良のメモリセルを確実に検出することを目的とし、 データ書込み後、被試験スタティック型メモリセルを
非選択状態にするとともに電源電圧を通常印加される電
圧から一旦低下させ、次いで瞬間的に上昇させた後再度
低下させ、その後、当該メモリセルを選択状態に復帰さ
せるとともに該電源電圧を該通常印加される電圧に戻し
て、該書込まれたデータの読出しを行うように構成され
る。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method for testing the memory retention performance of a static semiconductor memory device, which aims to reliably detect a defective memory cell. In the non-selected state, the power supply voltage is once lowered from the normally applied voltage, then momentarily raised and then lowered again, and then the memory cell is returned to the selected state and the power supply voltage is normally applied. It is configured to return the written voltage to read the written data.
本発明はスタティック型半導体記憶装置の記憶保持性
能を試験する方法に関する。The present invention relates to a method of testing the memory retention performance of a static semiconductor memory device.
一般にスタティック型半導体記憶装置（例えばスタテ
ィック型MISメモリ）の場合、電源印加中は永久にデー
タを保持することが要求されており、したがってかかる
データ保持性能を有するか否かを短時間に試験する必要
がある。Generally, in the case of a static semiconductor memory device (for example, a static MIS memory), it is required to hold data permanently while applying power, and therefore it is necessary to test whether or not it has such data holding performance in a short time. There is.
従来のこの種試験方法においては、データ書込み後読
出しまでの間に電源電圧を下げて試験を行っている。し
かしこの方法はセルへの供給電流を減らす（後述する補
償電流を減らす）意味で効果があるが、また不充分であ
る。In the conventional test method of this type, the test is performed by lowering the power supply voltage between the writing of data and the reading. However, this method is effective in the sense of reducing the supply current to the cell (reducing the compensation current described later), but is also insufficient.
第１図はこの種の試験方法が適用されるスタティック
型メモリセルの構成例を示すもので、Q1,Q2は当該メモ
リセルが選択されたときにオンとなるトランスファゲー
トであり、非選択時はオフとされる。またトランジスタ
Q3,Q4によりフリップフロップが構成され、該フリップ
フロップが所定の状態に設定されることにより所定のデ
ータが保持される。更に、Q5,Q6はそれぞれビット線BL,
▲▼と電源VCC間に接続された負荷トランジスタで
あり、またR1,R2はそれぞれ該電源VCCと記憶ノードA,B
間に接続された抵抗である。更にILは該記憶ノードに存
在するリーク抵抗RLを通して流れるリーク電流であり、
Ifは該リーク電流ILを補償する補償電流であって該電源
VCCから該抵抗を通して該記憶ノード側に流れる。FIG. 1 shows an example of the structure of a static memory cell to which this type of test method is applied. Q 1 and Q 2 are transfer gates that are turned on when the memory cell is selected, and are not selected. Time is off. Also transistors
A flip-flop is formed by Q 3 and Q 4 , and predetermined data is held by setting the flip-flop to a predetermined state. Furthermore, Q 5 and Q 6 are bit lines BL and BL, respectively.
A load transistor connected between ▲ ▼ and the power supply V CC , and R 1 and R 2 are the power supply V CC and the storage nodes A and B, respectively.
It is a resistor connected in between. Further, I L is a leak current flowing through the leak resistance R L existing in the storage node,
I f is a compensation current for compensating the leak current I L
It flows from V CC through the resistor to the storage node side.
ここで当該メモリセルが良品である場合にはリーク電
流ILは極小であり、補償電流Ifの方が十分に大きいた
め、電源電圧が印加されている限り永久にデータ保持
（例えばノードＡの電位がハイレベル、ノードＢの電位
がロウレベル）が可能であるが、メモリセルにおける何
らかの異常によりこのリーク電流ILが増大し、補償電流
Ifを超えるようになると、該データ保持が不可能とな
る。ここで上述したデータ保持が可能な条件は、該電源
電圧VCCを上記ノードＡの電位がハイレベルを保持でき
る最低限のレベルとしたときに、上記補償電流Ifが上記
リーク電流ILより大であれば上記データ保持が可能であ
るが、逆に上記リーク電流ILが上記補償電流Ifより大と
なれば上記データ保持が不可能となり、上記ノードＡの
電位がロウレベルに反転することになる。Here, when the memory cell is a non-defective product, the leakage current I L is extremely small and the compensation current I f is sufficiently large. Therefore, data is retained permanently (for example, at the node A) as long as the power supply voltage is applied. The potential is high level and the potential of the node B is low level). However, the leakage current I L increases due to some abnormality in the memory cell, and the compensation current
When it exceeds I f , the data cannot be held. The above-mentioned condition that data can be held is that the compensation current If is lower than the leakage current I L when the power supply voltage V CC is set to the minimum level at which the potential of the node A can hold a high level. If it is large, the data can be held, but conversely, if the leak current I L becomes larger than the compensation current I f , the data cannot be held and the potential of the node A is inverted to a low level. become.
この点、上記従来技術である電源電圧VCCを下げる試
験方法によれば、上記補償電流Ifを低く抑えることによ
って、見掛け上If＜ILとなり易い状態とし、このように
該電源電圧VCCを所定値だけ下げても依然として上記デ
ータ保持（すなわちノードＡの電位をハイレベルに保
持）がされているか否かによって当該メモリセルの良・
不良が試験される。In this respect, according to the test method of lowering the power supply voltage V CC which is the above-mentioned conventional technique, by suppressing the compensation current I f to a low value, it is likely that I f <I L is apparently obtained. Even if CC is lowered by a predetermined value, whether the memory cell is good or not depends on whether or not the data is still held (that is, the potential of the node A is held at the high level).
Defects are tested.
しかしながら上記従来方法によると、該試験後におけ
る温度条件の変化や経年変化等によって上記リーク電流
ILが増加し、その結果、該試験時には良品セルと判定さ
れたものが、その試験後に不良セルとなる場合があり、
したがって不良セルを見出すに充分な試験方法であると
はいえないという問題点がある。However, according to the above-mentioned conventional method, the above-mentioned leakage current may change due to changes in temperature conditions after the test and changes over time.
I L increases, and as a result, what was determined to be a good cell at the time of the test may become a defective cell after the test,
Therefore, there is a problem that it cannot be said that the test method is sufficient for finding defective cells.
本発明はかかる課題を解決するためになされたもの
で、当該試験時に不良のメモリセルを確実に検出しうる
ようにしたものである。The present invention has been made in order to solve such a problem, and is intended to surely detect a defective memory cell during the test.
上記課題を解決するために本発明によれば、データ書
込み後、被試験スタティック型メモリセルを非選択状態
にするとともに、電源電圧を通常印加される電圧から一
旦低下させ、次いで瞬間的に上昇させた後再度低下さ
せ、その後、当該メモリセルを選択状態に復帰させると
ともに該電源電圧を該通常印加される電圧に戻して、該
書込まれたデータの読出しを行うように構成される。According to the present invention, in order to solve the above problems, after writing data, the static memory cell under test is brought into a non-selected state, and the power supply voltage is once lowered from the voltage normally applied, and then momentarily raised. After that, the voltage is lowered again, and then the memory cell is returned to the selected state and the power supply voltage is returned to the normally applied voltage to read the written data.
上記構成によれば、試験時に一旦低下させた電源電圧
を瞬間的に上昇させた後再度低下させることにより、基
板電圧を降下させて上記リーク電流を増大させ、その結
果異常なリーク電流を有する不良セルを見出し易いよう
にして、該不良セルのほとんどを確実に検出することが
できる。According to the above configuration, the power supply voltage once lowered during the test is momentarily raised and then lowered again to lower the substrate voltage and increase the leak current, and as a result, a defect having an abnormal leak current. By making it easy to find cells, most of the defective cells can be reliably detected.
第２図（ａ）乃至（ｃ）は、上記第１図に示されるよ
うなスタティック型メモリセルに本発明の試験方法が適
用される場合の電源電圧および基板電圧の変化を示すも
ので、第２図（ｂ）は当該メモリの基板に基板バイアス
回路がある場合、また第２図（ｃ）は当該メモリの基板
に基板バイアス回路がない場合の基板電圧の変化（すな
わち例えばアース電位が印加されたＰ形基板あるいはＰ
ウエルの電圧変化）を示す。FIGS. 2A to 2C show changes in the power supply voltage and the substrate voltage when the test method of the present invention is applied to the static memory cell as shown in FIG. 2 (b) shows a case where the substrate of the memory has a substrate bias circuit, and FIG. 2 (c) shows a case where the substrate of the memory does not have a substrate bias circuit (ie, a ground potential is applied, for example). P-type substrate or P
Changes in well voltage).
上述したように第１図に示されるメモリセルにおい
て、リーク電流ILが零または極小であれば、データ記憶
ノードＡの電位は充分にハイレベルに保持されて何等問
題ないが、該リーク電流ILが補償電流If近くの値になる
と、該ノードＡの電位を充分なハイレベルに保持するこ
とができなくなり、正常なメモリセルとして機能しなく
なる。As described above, in the memory cell shown in FIG. 1, if the leak current I L is zero or the minimum, the potential of the data storage node A is kept at a sufficiently high level and there is no problem. When L becomes a value near the compensation current If , the potential of the node A cannot be maintained at a sufficiently high level, and the memory cell does not function normally.
このような不良なメモリセルを検出するために、本発
明では第２図（ａ）に示すように、データ書込み後、先
ずトランスファゲートQ1,Q2をオフさせて電源電圧VCCを
下げる（第２図（ａ）のＬ参照）。これにより記憶ノー
ドＡのハイレベルは低下し補償電流Ifが少くなる。なお
該トランスファゲートをオフさせている期間をポーズ期
間と称することとする。In order to detect such a defective memory cell, according to the present invention, as shown in FIG. 2A, after writing data, the transfer gates Q 1 and Q 2 are first turned off to lower the power supply voltage V CC ( (See L in FIG. 2 (a)). As a result, the high level of the storage node A decreases and the compensation current If decreases. Note that a period in which the transfer gate is turned off is called a pause period.
上記電源電圧の低下により当該基板の電圧は先ず第２
図（ｂ）および（ｃ）のd1に示すように該基板内の容量
カップリングにより一旦低下し、次いで該基板に基板バ
イアス回路がある場合には第２図（ｂ）のａに示すよう
に該基板電圧VBBが上昇する。Due to the decrease in the power supply voltage, the voltage of the substrate is
As shown by d 1 in FIGS. 2 (b) and 2 (c), it is temporarily lowered by capacitive coupling in the substrate, and then, when a substrate bias circuit is provided on the substrate, as shown in a of FIG. 2 (b). Then, the substrate voltage V BB rises.
次いで本発明では第２図（ａ）に示すように、上記ポ
ーズ期間中に電源電圧VCCを一瞬高く上げ（第２図
（ａ）のＨ参照）、その後すぐにまた下げる。この電源
電圧上昇時、該メモリセル以外の回路（例えばビット線
など）はチャージアップされるが、該メモリセル中のノ
ードＡの電位は、抵抗R1の抵抗値が高いため充分なハイ
レベルまで回復しない。Next, in the present invention, as shown in FIG. 2 (a), the power supply voltage V CC is momentarily raised during the pause period (see H in FIG. 2 (a)), and then immediately lowered again. When this power supply voltage rises, circuits other than the memory cell (eg, bit line) are charged up, but the potential of the node A in the memory cell reaches a sufficiently high level because the resistance value of the resistor R 1 is high. Does not recover.
また上記電源電圧の上昇により当該基板の電圧は、先
ず第２図（ｂ）および（ｃ）のd2に示すように上記容量
カップリングにより一旦上昇する。次いで該基板に基板
バイアス回路がある場合には、第２図（ｂ）のｂに示す
ように該基板電圧VBBが深く降下する。更にその直後に
おける電源電圧の低下により当該基板の電圧は先ず第２
図（ｂ）および（ｃ）のd3に示すように上記容量カップ
リングにより一旦低下し、次いで該基板に基板バイアス
回路がある場合には、第２図（ｂ）のｃに示すように該
基板電圧VBBが再び上昇する。また該基板に基板バイア
ス回路がない場合でも、第２図（ｃ）に示される上記容
量カップリングによる電圧上昇（d2で示される）および
電圧低下（d3で示される）に応じて、第２図（ｃ）に示
されるような基板電圧降下領域ｂを生ずる。Further, the voltage of the substrate is first raised by the capacitive coupling as shown by d 2 in FIGS. 2B and 2C due to the rise of the power supply voltage. Next, when the substrate has a substrate bias circuit, the substrate voltage V BB deeply drops as shown in b of FIG. 2 (b). Further, immediately after that, the voltage of the substrate is changed to the second
As shown in d 3 of FIGS. 2 (b) and 2 (c), the capacitance coupling causes the voltage to drop once, and when the substrate has a substrate bias circuit, as shown in c of FIG. 2 (b), The substrate voltage V BB rises again. Even if the substrate does not have a substrate bias circuit, the voltage rise (shown as d 2 ) and the voltage drop (shown as d 3 ) due to the capacitive coupling shown in FIG. A substrate voltage drop region b as shown in FIG.
このような基板電圧降下領域ｂが生ずることにより、
上記リーク電流ILが該基板へのリーク電流であれば、そ
のリーク電流値が増大することになり、しかも上記電源
電圧VCCの低下によって補償電流Ifが抑えられているの
で、当該メモリセルに異常がある場合には、該リーク電
流ILと補償電流Ifとの差が大きくなり、ノードＡの電位
はハイレベルを維持できなくなって容易にロウレベルに
反転し、これにより不良なメモリセルの検出が行われ
る。Due to such a substrate voltage drop region b,
If the leak current I L is a leak current to the substrate, the leak current value will increase, and since the compensation current I f is suppressed by the decrease in the power supply voltage V CC , the memory cell Is abnormal, the difference between the leak current I L and the compensation current I f becomes large, and the potential of the node A cannot be maintained at a high level and easily inverts to a low level. Is detected.
次いでトランスファゲートQ1,Q2を再びオンとする
が、この時上記電源電圧VCCは第２図（ａ）に示すよう
に上記低下されたレベルＬから上昇させて一旦中間レベ
ルＭとされ、（この期間をディスターブ期間と称するこ
ととする）、その後通常の電源電圧レベルに戻して上記
試験結果のデータ読出しを行う。なおこの場合、上記基
板電圧は上記容量カップリングにより、第２図（ｂ）お
よび（ｃ）においてそれぞれd4およびd5に示すように変
化する。Next, the transfer gates Q 1 and Q 2 are turned on again. At this time, the power supply voltage V CC is raised from the lowered level L to the intermediate level M as shown in FIG. (This period is referred to as a disturb period.) After that, the power source voltage level is returned to the normal level and the data of the test result is read. In this case, the substrate voltage changes due to the capacitive coupling as shown by d 4 and d 5 in FIGS. 2B and 2C, respectively.
ここで本発明において上記ディスターブ期間を設けた
理由を説明する。上述したように基板へのリーク電流値
を増大させることにより、該基板へのリークが大きい不
良セルはほとんどデータ保持ができなくなる。この場合
上記ノードＡのハイレベル電位を維持することができな
くなり、該ノードＡの電位がハイレベルからロウレベル
に反転する。しかし仮にこの時、該ノードＡの電位が上
記反転にまで至らなかったとしても、該ノードＡのハイ
レベル電位は上記電源電圧の低下により充分に低下して
いるので、上記ディスターブ期間（すなわち通常のハイ
レベルより低い電源電圧レベルＭでトランスファゲート
Q1,Q2をオンとする期間）においては、該ノードＡの電
位（通常のハイレベル電位より低いハイレベル電位）が
そのゲートに印加されているトランジスタQ4は、その駆
動機能が低下して（すなわちその導通状態が低下し
て）、ビット線▲▼から十分な電流を駆動すること
ができなくなっており、それだけノードＢの電位がハイ
レベルになり易くなる。したがって当該メモリセルに異
常がある場合には、仮に上記基板電圧の降下によって該
ノードＡの電位が反転しなかったとしても、上記ディス
ターブ期間において該ノードＢの電位がハイレベルとな
り、これによりトランジスタQ3がオンとなり、該ノード
Ａの電位が上記ハイレベルからロウレベルに反転する。
したがってこのようなディスターブ期間を設けることに
より、上記基板以外へのリーク（例えば絶縁膜などを通
してのリーク）も含め、異常なリーク電流を有する不良
なメモリセルの検出を、より確実に行うことができる。Here, the reason why the disturb period is provided in the present invention will be described. By increasing the leak current value to the substrate as described above, the defective cell having a large leak to the substrate can hardly hold data. In this case, the high level potential of the node A cannot be maintained, and the potential of the node A is inverted from the high level to the low level. However, even if the potential of the node A does not reach the inversion at this time, the high-level potential of the node A is sufficiently reduced due to the decrease of the power supply voltage, so that the disturb period (that is, the normal period). Transfer gate at power supply voltage level M lower than high level
In the period during which Q 1 and Q 2 are turned on), the driving function of the transistor Q 4 whose potential of the node A (high level potential lower than the normal high level potential) is applied to the transistor Q 4 is deteriorated. Then (that is, the conduction state is lowered), it becomes impossible to drive a sufficient current from the bit line {circle around (3)}, and the potential of the node B is likely to become high level. Therefore, if the memory cell has an abnormality, the potential of the node B becomes high level during the disturb period even if the potential of the node A is not inverted due to the drop of the substrate voltage. 3 is turned on, and the potential of the node A is inverted from the high level to the low level.
Therefore, by providing such a disturb period, it is possible to more reliably detect a defective memory cell having an abnormal leak current, including a leak to a region other than the substrate (for example, a leak through an insulating film). .
本発明によれば、スタティック型メモリセルの不良
を、短時間の試験によって確実に検出することができ
る。According to the present invention, a defect in a static memory cell can be reliably detected by a short-time test.
第１図は本発明の試験方法が適用されるスタティック型
メモリセルの構成例を示す図、 第２図（ａ）乃至（ｃ）は、本発明の試験方法が適用さ
れる場合の電源電圧および基板電圧の変化を示す図であ
る。 （符号の説明） Q1〜Q6:トランジスタ、 R1,R2:抵抗、 RL:リーク抵抗、 If:補償電流、 IL:リーク電流。FIG. 1 is a diagram showing a configuration example of a static type memory cell to which the test method of the present invention is applied, and FIGS. 2 (a) to 2 (c) are power supply voltages when the test method of the present invention is applied and It is a figure which shows the change of substrate voltage. (Description of symbols) Q 1 ~Q 6: transistors, R 1, R 2: resistance, R L: leakage resistance, I f: compensation current, I L: leakage current.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 黒田 将 愛知県春日井市高蔵寺町２丁目1844番２ 富士通ヴィエルエスアイ株式会社内 (56)参考文献 特開 平１−166399（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaru Kuroda 2-1844, Kozoji-cho, Kasugai-shi, Aichi Fujitsu Viels-E Co., Ltd. (56) Reference JP-A-1-166399 (JP, A)
Claims (2)
モリセルを非選択状態にするとともに電源電圧を通常印
加される電圧から一旦低下させ、次いで瞬間的に上昇さ
せた後再度低下させ、その後、当該メモリセルを選択状
態に復帰させるとともに該電源電圧を該通常印加される
電圧に戻して、該書込まれたデータの読出しを行うこと
を特徴とする半導体記憶装置の試験方法。1. After data writing, the static memory cell under test is brought into a non-selected state, and the power supply voltage is once lowered from a voltage normally applied, then momentarily raised and then lowered again, and then A method for testing a semiconductor memory device, comprising: returning a memory cell to a selected state, returning the power supply voltage to the normally applied voltage, and reading the written data.
常時印加される電圧まで２段階で戻すようにした、請求
項１に記載の半導体記憶装置の試験方法。2. The method of testing a semiconductor memory device according to claim 1, wherein the power supply voltage is returned to the constantly applied voltage in two steps when returning to the selected state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1054993A JP2520957B2 (en) | 1989-03-09 | 1989-03-09 | Semiconductor memory device testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1054993A JP2520957B2 (en) | 1989-03-09 | 1989-03-09 | Semiconductor memory device testing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02235300A JPH02235300A (en) | 1990-09-18 |
| JP2520957B2 true JP2520957B2 (en) | 1996-07-31 |
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ID=12986176
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1054993A Expired - Lifetime JP2520957B2 (en) | 1989-03-09 | 1989-03-09 | Semiconductor memory device testing method |
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| Country | Link |
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| JP (1) | JP2520957B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7394708B1 (en) * | 2005-03-18 | 2008-07-01 | Xilinx, Inc. | Adjustable global tap voltage to improve memory cell yield |
| CN116705128A (en) * | 2022-02-24 | 2023-09-05 | 长鑫存储技术有限公司 | Method for enhancing electric leakage between adjacent memory cells and electric leakage detection method and device |
| CN114649050A (en) | 2022-02-24 | 2022-06-21 | 长鑫存储技术有限公司 | Memory detection method, detection device, computer storage medium and electronic equipment |
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1989
- 1989-03-09 JP JP1054993A patent/JP2520957B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02235300A (en) | 1990-09-18 |
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