JP2504838B2 - Input / output protection device for semiconductor integrated circuit - Google Patents
Input / output protection device for semiconductor integrated circuitInfo
- Publication number
- JP2504838B2 JP2504838B2 JP19552289A JP19552289A JP2504838B2 JP 2504838 B2 JP2504838 B2 JP 2504838B2 JP 19552289 A JP19552289 A JP 19552289A JP 19552289 A JP19552289 A JP 19552289A JP 2504838 B2 JP2504838 B2 JP 2504838B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- conductivity
- input
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路の入出力保護装置に関するも
のである。The present invention relates to an input / output protection device for a semiconductor integrated circuit.
従来例を、第１導電型がＮ型の場合を例として説明す
る。A conventional example will be described by taking the case where the first conductivity type is N type as an example.
従来、この種の入出力保護装置は第３図の半導体チッ
プの断面図、第４図の等価回路図に示す様に接地電位に
固定されたＰ型Si基板10上にＮ型の埋め込み量11を形成
し、Ｎ型埋込み層11とＮ型拡散層12a,…を介して電源電
圧に固定されたＮ型ウェル13を持つ。さらに隣接する素
子と分離された電気的に固定されていないＰ型ウェル６
内に入力端子が接続されるＮ型拡散抵抗層５が設けら
れ、Ｎ型埋め込み層11をコレクタ、Ｐ型ウェル６をベー
ス、Ｎ型拡散抵抗層５をエミッタとして寄生バイポーラ
トラインジスタ16を作っており、Ｎ型拡散抵抗層５を通
った後に保護回路としてnMOSトランジスタ９が構成され
ていた。Conventionally, this type of input / output protection device has an N-type buried amount 11 on a P-type Si substrate 10 fixed to the ground potential as shown in the sectional view of the semiconductor chip of FIG. 3 and the equivalent circuit diagram of FIG. And has an N-type well 13 fixed to the power supply voltage via the N-type buried layer 11 and the N-type diffusion layers 12a ,. Further, the P-type well 6 which is separated from the adjacent element and is not electrically fixed
An N-type diffusion resistance layer 5 to which an input terminal is connected is provided inside, and a parasitic bipolar transistor 16 is formed by using the N-type buried layer 11 as a collector, the P-type well 6 as a base, and the N-type diffusion resistance layer 5 as an emitter. Therefore, the nMOS transistor 9 is formed as a protection circuit after passing through the N-type diffusion resistance layer 5.
上述した従来の半導体集積回路入力保護装置では、入
力端子が接続されるＮ型拡散抵抗層を形成する為のＰ型
ウェルは、静電耐圧の強度を得る為に電気的に固定され
ていない。これにより入力端子がエミッタ、Ｎ型埋込層
がコレクタ、Ｐ型ウェルが開放されたベースという寄生
バイポーラトランジスタが形成されることとなる。In the conventional semiconductor integrated circuit input protection device described above, the P-type well for forming the N-type diffusion resistance layer to which the input terminal is connected is not electrically fixed in order to obtain the strength of electrostatic withstand voltage. As a result, a parasitic bipolar transistor in which the input terminal is the emitter, the N-type buried layer is the collector, and the P-type well is open is formed.
入力端子のレベル（以後Vin）が“H"レベルと感知さ
れるレベル（以後VIH）を電源電圧にして放置すると、
寄生バイポーラトランジスタのコレクタ−ベース間の接
合バイアスが小さくなり、Ｐ型ウェルに蓄積される電荷
量が非常に大きくなる。その後Vinを“L"レベルにする
とＰ型ウェルに蓄積された電荷はＮ型拡散抵抗の抵抗値
と蓄積された電荷量と寄生バイポーラトランジスタのh
feにより決まる時定数によりＮ型拡散抵抗を介して入力
端子へ向けて放電し“L"レベルに推移する事になる。こ
れにより例えばスピードの低下といった半導体集積回路
の性能を著しく劣化してしまうという欠点があった。If the level at which the input terminal level (hereafter V in ) is detected as “H” level (hereafter V IH ) is left as the power supply voltage,
The junction bias between the collector and the base of the parasitic bipolar transistor becomes small, and the amount of charge accumulated in the P-type well becomes very large. After that, when V in is set to the “L” level, the charge accumulated in the P-type well becomes the resistance value of the N-type diffusion resistance, the accumulated charge amount, and the h of the parasitic bipolar transistor.
Due to the time constant determined by fe, it discharges toward the input terminal through the N-type diffused resistor and changes to "L" level. As a result, there is a drawback that the performance of the semiconductor integrated circuit is significantly deteriorated, for example, the speed is reduced.
本発明の半導体集積回路の入出力保護装置は、電源電
位端に接続されている第１導電型ウェルと第１導電型埋
込層で囲まれ、第２導電型基板から電気的に分離された
領域内の第２導電型ウェル内に形成された外部端子に接
続される第１導電型拡散抵抗を持つ半導体集積回路の入
出力保護装置に於いて、前記第１導電型拡散層抵抗にゲ
ート端子を、第２導電型ウェル内の第２の導電型拡散層
にドレイン端子を、接地電位にソース端子をそれぞれ接
続したMOSトランジスタを有している。An input / output protection device for a semiconductor integrated circuit according to the present invention is surrounded by a first conductivity type well connected to a power supply potential end and a first conductivity type buried layer, and electrically isolated from a second conductivity type substrate. In an input / output protection device for a semiconductor integrated circuit having a first-conductivity-type diffused resistor connected to an external terminal formed in a second-conductivity-type well in a region, in the first-conductivity-type diffused layer resistor, a gate terminal is provided. And a MOS transistor having a drain terminal connected to the second conductivity type diffusion layer in the second conductivity type well and a source terminal connected to the ground potential.
次に本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す半導体チップの断面
図、第２図は等価回路図である。FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram.
従来例と相違する点は、nMOSトランジスタ１をＰ型拡
散層2aを介して接地レベルに固定されたＰ型ウェル14a
内に形成し、このnMOSトランジスタの一方のＮ型拡散層
3aは接地レベルに、もう一方のＮ型拡散層４はＮ型拡散
抵抗層５が形成されているＰ型ウェル６内のＰ型拡散層
７に接続され、ゲート８は入力保護用トランジスタ９の
ドレイン及び内部回路へ接続されている点である。The difference from the conventional example is that a P-type well 14a in which the nMOS transistor 1 is fixed to the ground level via a P-type diffusion layer 2a.
One N-type diffusion layer of this nMOS transistor
3a is connected to the ground level, the other N-type diffusion layer 4 is connected to the P-type diffusion layer 7 in the P-type well 6 in which the N-type diffusion resistance layer 5 is formed, and the gate 8 of the input protection transistor 9 is connected. That is, it is connected to the drain and the internal circuit.
次に、本実施例の動作について説明する。 Next, the operation of this embodiment will be described.
例えば入力レベルVinをVccレベルに保持した状態を考
える。この場合、入力レベルはＮ型拡散抵抗層５を通し
てnMOSトランジスタ１のゲート８を電源電圧レベルに固
定するのでnMOSトランジスタ１はONしておりＮ型拡散抵
抗層５が設けられているＰ型ウェル６の電荷を接地へ逃
がす働きをする。この為Ｐ型ウェル６に電荷が蓄積され
ることはない。従ってVinを瞬時に“L"レベルへ変化さ
せた時でも時定数による遅れは全くない。For example, consider a state in which the input level V in is held at V cc level. In this case, since the input level fixes the gate 8 of the nMOS transistor 1 to the power supply voltage level through the N-type diffused resistance layer 5, the nMOS transistor 1 is ON and the P-type well 6 in which the N-type diffused resistance layer 5 is provided. It works to release the electric charge of to the ground. Therefore, no charges are accumulated in the P-type well 6. Therefore, even when V in is instantly changed to the “L” level, there is no delay due to the time constant.
以上の説明において、導電型を逆にし、電源の極性を
変えたものにも本発明を適用しうることは明らかであ
る。In the above description, it is obvious that the present invention can be applied to the case where the conductivity type is reversed and the polarity of the power source is changed.
以上説明したように本発明は、入力端子が接続されて
いる第１導電型拡散抵抗層が設けられている第２導電型
ウェルと接地端子との間に、ゲートを第１導電型拡散抵
抗層の内部回路側端に接続した第１導電型MOSトランジ
スタを挿入することにより、入力端子の電位が電源電圧
レベルで固定された場合においても第２導電型ウェルに
電荷が蓄積されることがなく、十分時間がたった後に入
力端子の電位を“L"レベルに切り換えても半導体集積回
路の本来の性能を失うことなく動作させる事が可能とな
るという効果がある。As described above, according to the present invention, the gate is provided between the well of the second conductivity type having the first conductivity type diffusion resistance layer to which the input terminal is connected and the ground terminal, and the first conductivity type diffusion resistance layer. By inserting the first-conductivity-type MOS transistor connected to the end of the internal circuit, the electric charge is not accumulated in the second-conductivity-type well even when the potential of the input terminal is fixed at the power supply voltage level. Even if the potential of the input terminal is switched to the “L” level after a sufficient time has elapsed, it is possible to operate the semiconductor integrated circuit without losing its original performance.
第１図は本発明の半導体入出力保護装置の一実施例を示
す半導体チップの断面図、第２図はこの実施例の等価回
路図、第３図は従来例の半導体集積回路の入出力保護装
置を示す半導体チップの断面図、第４図は従来例の等価
回路図である。 １……nMOSトランジスタ、2a〜2e……Ｎ型拡散層、3,4
……Ｎ型拡散層、５……Ｎ型拡散抵抗層、６……Ｐ型ウ
ェル、７……Ｐ型拡散層、８……nMOSトランジスタゲー
ト、９……入力保護用トランジスタ、10……Ｐ型Si基
板、11……Ｎ型埋込み層、12a〜12d……Ｎ型拡散層、13
……Ｎ型ウェル、14a,14b……Ｐ型ウェル、15……外部
端子、16……寄生バイポーラトランジスタ、17……Ｎ型
エピタキシャル層。FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of a semiconductor input / output protection device of the present invention, FIG. 2 is an equivalent circuit diagram of this embodiment, and FIG. 3 is an input / output protection of a conventional semiconductor integrated circuit. FIG. 4 is a sectional view of a semiconductor chip showing the device, and FIG. 4 is an equivalent circuit diagram of a conventional example. 1 ... nMOS transistor, 2a-2e ... N-type diffusion layer, 3,4
... N-type diffusion layer, 5 ... N-type diffusion resistance layer, 6 ... P-type well, 7 ... P-type diffusion layer, 8 ... nMOS transistor gate, 9 ... Input protection transistor, 10 ... P -Type Si substrate, 11 ... N-type buried layer, 12a to 12d ... N-type diffusion layer, 13
...... N type well, 14a, 14b ...... P type well, 15 ...... external terminal, 16 ...... parasitic bipolar transistor, 17 ...... N type epitaxial layer.
Claims (1)
散層が形成されている第１導電型ウェルと第１導電型埋
込層で囲まれ、第２導電型基板から電気的に分離された
領域内の第２の導電型ウェル内に形成された外部端子に
接続される第１導電型拡散抵抗を持つ半導体集積回路の
入出力保護装置において、前記外部端子に接続される第
１導電型拡散層抵抗にゲート端子を、前記第２導電型ウ
ェル内に形成された第２の導電型拡散層にドレイン端子
を、接地電位にソース端子をそれぞれ接続したMOSトラ
ンジスタを挿入したことを特徴とする半導体集積回路の
入出力保護装置。1. A first-conductivity-type well in which a first-conductivity-type diffusion layer connected to a power supply potential end is formed and a first-conductivity-type buried layer, and is electrically connected from a second-conductivity-type substrate. In an input / output protection device of a semiconductor integrated circuit having a first conductivity type diffusion resistance connected to an external terminal formed in a second conductivity type well in a separated region, a first connection to the external terminal is provided. A MOS transistor having a gate terminal connected to the conductivity type diffusion layer resistor, a drain terminal connected to the second conductivity type diffusion layer formed in the second conductivity type well, and a source terminal connected to the ground potential is inserted. I / O protection device for semiconductor integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19552289A JP2504838B2 (en) | 1989-07-27 | 1989-07-27 | Input / output protection device for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19552289A JP2504838B2 (en) | 1989-07-27 | 1989-07-27 | Input / output protection device for semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0360066A JPH0360066A (en) | 1991-03-15 |
| JP2504838B2 true JP2504838B2 (en) | 1996-06-05 |
Family
ID=16342494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19552289A Expired - Lifetime JP2504838B2 (en) | 1989-07-27 | 1989-07-27 | Input / output protection device for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2504838B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05121670A (en) * | 1991-10-25 | 1993-05-18 | Nec Corp | Semiconductor input protective device |
| US5545909A (en) * | 1994-10-19 | 1996-08-13 | Siliconix Incorporated | Electrostatic discharge protection device for integrated circuit |
| CN1244152C (en) | 2001-11-16 | 2006-03-01 | 松下电器产业株式会社 | Semiconductor device |
-
1989
- 1989-07-27 JP JP19552289A patent/JP2504838B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0360066A (en) | 1991-03-15 |
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