JP2501568Y2 - Receiver - Google Patents

Receiver

Info

Publication number
JP2501568Y2
JP2501568Y2 JP1694290U JP1694290U JP2501568Y2 JP 2501568 Y2 JP2501568 Y2 JP 2501568Y2 JP 1694290 U JP1694290 U JP 1694290U JP 1694290 U JP1694290 U JP 1694290U JP 2501568 Y2 JP2501568 Y2 JP 2501568Y2
Authority
JP
Japan
Prior art keywords
video signal
transistor
emitter
reference voltage
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1694290U
Other languages
Japanese (ja)
Other versions
JPH03107882U (en
Inventor
茂 石黒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP1694290U priority Critical patent/JP2501568Y2/en
Publication of JPH03107882U publication Critical patent/JPH03107882U/ja
Application granted granted Critical
Publication of JP2501568Y2 publication Critical patent/JP2501568Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Landscapes

  • Video Image Reproduction Devices For Color Tv Systems (AREA)
  • Processing Of Color Television Signals (AREA)
  • Television Receiver Circuits (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 カラーテレビ受信機、カラーディスプレイ等の映像機
器の映像信号回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a video signal circuit of a video device such as a color television receiver and a color display.

〔従来技術〕[Prior art]

カラーテレビ受信機等において、CRTの明るさを上げ
るためにはCRTをドライブする電圧のレベルを大きくす
る必要がある。しかし、CRTを大振幅でドライブすると
中間レベルの輝度領域での効果は認められるが、高レベ
ルの輝度部ではCRTのアノード電流が流れ過ぎるため、C
RT画面上でブルーミング現象を発生しフォーカスの劣化
を招く。
In a color television receiver or the like, it is necessary to increase the level of the voltage driving the CRT in order to increase the brightness of the CRT. However, when the CRT is driven with a large amplitude, the effect in the intermediate brightness region is recognized, but the anode current of the CRT flows too much in the high brightness region, so C
Blooming phenomenon occurs on the RT screen, causing focus deterioration.

〔考案が解決しようとする課題〕[Problems to be solved by the device]

本考案は従来例に鑑みてなされたもので、高輝度部に
よるCRTのアノード電流を抑圧しフォーカスの劣化を防
止することで総合画質の向上を図ることを目的とする。
The present invention has been made in view of the conventional example, and it is an object of the present invention to improve the overall image quality by suppressing the anode current of the CRT due to the high brightness portion and preventing the deterioration of the focus.

〔課題を解決するための手段〕[Means for solving the problem]

本考案は、映像増幅回路のベース入力回路にダイオー
ド回路と抵抗分割の電圧をバイアスとする温度特性を考
慮したトランジスタによる基準電圧回路とを付加するこ
とで、映像信号の高輝度部のレベルを抑圧することに特
徴がある。
The present invention suppresses the level of the high-brightness part of the video signal by adding a diode circuit and a reference voltage circuit using a transistor that considers the temperature characteristic of biasing the voltage of resistance division to the base input circuit of the video amplifier circuit. There is a feature in doing it.

〔作用〕[Action]

第1図に示すように、入力抵抗1と映像増幅用のトラ
ンジスタ2とエミッタ負荷抵抗3からなるエミッタホロ
ワ回路と、基準電圧用のトランジスタ7とベースバイア
ス用の分割抵抗8,9とエミッタ負荷抵抗6からなるエミ
ッタを基準電圧VKとする基準電圧回路と、ダイオード
5と抵抗4からなる映像信号の高輝度部の抑圧回路との
回路構成からなり、第2図のように入力映像信号Vi
基準電圧Vkのレベル関係を設定すると映像信号の高輝
度部の電圧Dでダイオード5が導通し、映像増幅用のト
ランジスタ2のエミッタより高輝度部の抑圧した映像信
号Voを出力する。
As shown in FIG. 1, an emitter follower circuit including an input resistor 1, a video amplifying transistor 2 and an emitter load resistor 3, a reference voltage transistor 7, base bias dividing resistors 8 and 9 and an emitter load resistor 6 are provided. 2 is composed of a reference voltage circuit having an emitter made of a reference voltage V K as a reference voltage and a circuit for suppressing a high-luminance part of a video signal which is composed of a diode 5 and a resistor 4, and has an input video signal V i as shown in FIG. When the level relationship of the reference voltage V k is set, the diode 5 is turned on by the voltage D of the high brightness portion of the video signal, and the video signal V o suppressed by the high brightness portion is output from the emitter of the transistor 2 for video amplification.

〔実施例〕〔Example〕

第1図のように、入力映像信号Viを入力抵抗1を通
してエミッタホロワ回路トランジスタ2のベースに接続
し、電源電圧(+B)を抵抗8,9で分割した分割点を基
準電圧用コレクタ接地のトランジスタ7のベースに接続
し、同基準電圧用トランジスタ7のエミッタ負荷抵抗6
出力と前記トランジスタ2のベースとの間に、電流制限
抵抗4とダイオード5とを直列に同ダイオード5のアノ
ードを同トランジスタ7のエミッタ側とする方向に接続
し、同トランジスタ7のエミッタ電圧を基準電圧Vk
する。基準電圧Vkは電源電圧を抵抗8と9で分割した
電圧+トランジスタ7のVBEで設定する。トランジスタ
7と抵抗6,8,9とコンデンサ10とからなる基準電圧回路
は温度特性を考慮し基準電圧Vkの変動を補償してい
る。温度上昇によりトランジスタ7のVBEが小さくなる
とVKが下がり、同時にダイオード5の順方向電圧VDF
も減少しダイオード5の動作開始電圧Dの変動を抑え
る。基準電圧Vkと入力映像信号Viとのレベル関係を第
2図のように設定すると、入力映像信号Viの映像の高
輝度部の電圧Dでダイオード5を導通状態とし、入力抵
抗1と電流制限抵抗4の定数と同ダイオード5の特性に
より、高輝度部で緩やかな傾斜特性としてトランジスタ
2のエミッタ抵抗3より高輝度部のレベルを抑圧した映
像信号Voを出力する。尚、高輝度部の傾斜は入力抵抗
1に対して電流制限抵抗4の定数を小さくする程緩やか
な傾斜となり抑圧量が増加する。
As shown in FIG. 1, the input video signal V i is connected to the base of the emitter follower circuit transistor 2 through the input resistor 1, and the dividing point at which the power supply voltage (+ B) is divided by the resistors 8 and 9 is a collector grounded transistor for the reference voltage. 7 is connected to the base of the same reference voltage transistor 7 and the emitter load resistor 6
A current limiting resistor 4 and a diode 5 are connected in series between the output and the base of the transistor 2 in a direction in which the anode of the diode 5 is on the emitter side of the transistor 7, and the emitter voltage of the transistor 7 is used as a reference. The voltage is V k . The reference voltage V k is set by the voltage obtained by dividing the power supply voltage by the resistors 8 and 9 + V BE of the transistor 7. The reference voltage circuit composed of the transistor 7, the resistors 6, 8, 9 and the capacitor 10 compensates for the fluctuation of the reference voltage V k in consideration of the temperature characteristic. When V BE of the transistor 7 decreases due to the temperature rise, V K decreases, and at the same time, the forward voltage V DF of the diode 5 decreases.
Is also reduced to suppress the fluctuation of the operation start voltage D of the diode 5. When the level relationship between the reference voltage V k and the input video signal V i is set as shown in FIG. 2, the diode 5 is made conductive by the voltage D of the high brightness portion of the video of the input video signal V i and the input resistance 1 and Due to the constant of the current limiting resistor 4 and the characteristic of the diode 5, the video signal V o in which the level of the high luminance portion is suppressed is output from the emitter resistance 3 of the transistor 2 as a gentle slope characteristic in the high luminance portion. The slope of the high-luminance portion becomes gentler as the constant of the current limiting resistor 4 is smaller than that of the input resistor 1, and the suppression amount increases.

〔考案の効果〕[Effect of device]

以上のように本考案は、温度特性を考慮したトランジ
スタによる基準電圧回路とダイオード回路との信号抑圧
回路を付加し、映像信号の高輝度部のレベルを抑圧する
ことで、図に示していないが、CRTのブルーミングによ
るフォーカスの劣化を防止し総合画質の向上を図ること
ができる。
As described above, the present invention adds the signal suppression circuit of the reference voltage circuit and the diode circuit by the transistor in consideration of the temperature characteristic and suppresses the level of the high luminance part of the video signal, which is not shown in the figure. , It is possible to prevent deterioration of focus due to blooming of CRT and improve the overall image quality.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案の一実施例を示す映像信号の高輝度部を
抑圧する電気回路図、第2図は同第1図の動作波形図で
ある。 1は入力抵抗、4は電流制限抵抗、5は信号抑圧用ダイ
オード、7は基準電圧用トランジスタ、Viは入力映像
信号、Voは高輝度部を抑圧した出力信号、Vkは基準電
圧、Dはダイオード5の導通開始電圧である。
FIG. 1 is an electric circuit diagram for suppressing a high-luminance portion of a video signal showing an embodiment of the present invention, and FIG. 2 is an operation waveform diagram of FIG. 1 is an input resistor, 4 is a current limiting resistor, 5 is a signal suppressing diode, 7 is a reference voltage transistor, V i is an input video signal, V o is an output signal in which a high luminance part is suppressed, V k is a reference voltage, D is the conduction start voltage of the diode 5.

Claims (1)

(57)【実用新案登録請求の範囲】(57) [Scope of utility model registration request] 【請求項1】カラーテレビ受信機等の映像増幅回路にお
いて、映像信号を入力抵抗を通して低インピーダンスで
出力するエミッタホロワ回路のベースに接続し、一方、
電源電圧を抵抗分割した分割点をコレクタ接地の基準電
圧発生用のトランジスタのベースに接続し、同トランジ
スタのエミッタ負荷抵抗出力と前記エミッタホロワ回路
のベースとの間に、抵抗とダイオードを直列に同ダイオ
ードのアノードを同トランジスタのエミッタ側とする方
向に接続し、同エミッタホロワ回路のエミッタ負荷より
映像信号の高輝度部のレベルを抑圧した映像信号を出力
してなる受像機。
1. In a video amplifier circuit such as a color television receiver, a video signal is connected to a base of an emitter follower circuit for outputting a video signal with a low impedance through an input resistor.
The dividing point where the power supply voltage is divided by resistance is connected to the base of the transistor for generating the reference voltage of the grounded collector, and the resistor and the diode are connected in series between the emitter load resistance output of the transistor and the base of the emitter follower circuit. An image receiver in which the anode of is connected in the direction of the emitter side of the same transistor, and the video signal in which the level of the high-luminance part of the video signal is suppressed is output from the emitter load of the emitter follower circuit.
JP1694290U 1990-02-21 1990-02-21 Receiver Expired - Lifetime JP2501568Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1694290U JP2501568Y2 (en) 1990-02-21 1990-02-21 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1694290U JP2501568Y2 (en) 1990-02-21 1990-02-21 Receiver

Publications (2)

Publication Number Publication Date
JPH03107882U JPH03107882U (en) 1991-11-06
JP2501568Y2 true JP2501568Y2 (en) 1996-06-19

Family

ID=31520179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1694290U Expired - Lifetime JP2501568Y2 (en) 1990-02-21 1990-02-21 Receiver

Country Status (1)

Country Link
JP (1) JP2501568Y2 (en)

Also Published As

Publication number Publication date
JPH03107882U (en) 1991-11-06

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