JP2022105251A - Semiconductor heat dissipation package structure - Google Patents

Semiconductor heat dissipation package structure Download PDF

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JP2022105251A
JP2022105251A JP2021026656A JP2021026656A JP2022105251A JP 2022105251 A JP2022105251 A JP 2022105251A JP 2021026656 A JP2021026656 A JP 2021026656A JP 2021026656 A JP2021026656 A JP 2021026656A JP 2022105251 A JP2022105251 A JP 2022105251A
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substrate
heat dissipation
adhesive layer
package structure
heat sink
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JP7152544B2 (en
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東昇 李
Tosho Ri
規浩 ▲ほう▼
Kuei-Hao Pang
兆▲けい▼ 魏
Chao-Ching Wei
晉村 郭
Chin-Tsun Kuo
佩螢 季
Pei-Ying Li
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Chipbond Technology Corp
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Chipbond Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

To provide a semiconductor heat dissipation package structure.SOLUTION: A semiconductor heat dissipation package structure comprises a substrate 110, a chip 120, an adhesive layer 130, and a heat sink 140. The adhesive layer 130 is installed on the substrate 110, surrounding the chip 120. The heat sink 140 is installed on the substrate 110, a heat dissipation layer 142 of the heat sink 140 being in contact with the chip 120 installed on the substrate 110 and carrying out heat dissipation from the chip 120. The heat sink 140 having a carrier 141 and the heat dissipation layer 142 is attached to the adhesive layer 130 with an attachment part 140a to form a space S surrounding the adhesive layer 130 between the attachment part 140a and the substrate 110. The space S surrounds the adhesive layer 130 to accommodate the adhesive layer 130 compressed and overflowed, and thereby, prevents such an event that the adhesive layer 130 overflows or protrudes onto the heat sink 140.SELECTED DRAWING: Figure 5

Description

本発明は、半導体放熱パッケージ構造及びその製造方法に関し、特に、接着剤が溢れ出してパッケージ構造を汚染する事象を回避する半導体放熱パッケージ構造に関するものである。 The present invention relates to a semiconductor heat dissipation package structure and a method for manufacturing the same, and more particularly to a semiconductor heat dissipation package structure that avoids an event in which an adhesive overflows and contaminates the package structure.

電子製品の機能が向上するにつれ、チップが演算時に高熱を発するようになっている。チップの温度が高すぎるとチップが損壊してしまい、電子製品が使用できなくなる。
薄膜フリップチップパッケージ構造として、例えば、特許文献１に記載されたものが知られている。 As the functionality of electronic products improves, the chips generate high heat during computation. If the temperature of the chip is too high, the chip will be damaged and the electronic product cannot be used.
As a thin film flip chip package structure, for example, the one described in Patent Document 1 is known.

従来の技術では、第一放熱部材の接着層がチップ及び薄膜基板に取り付けられており、チップに対して放熱を行っている。接着層のエッジは基材、熱伝導層、及び金属層のエッジに平坦に揃えられている。このため、薄膜フリップチップパッケージ構造が圧搾された場合、接着層が外力により圧迫されることで基材、熱伝導層、及び金属層のエッジに溢れ出したり突出し、薄膜フリップチップパッケージ構造を汚染してしまう。 In the conventional technique, the adhesive layer of the first heat dissipation member is attached to the chip and the thin film substrate to dissipate heat to the chip. The edges of the adhesive layer are evenly aligned with the edges of the substrate, the heat conductive layer, and the metal layer. Therefore, when the thin film flip chip package structure is squeezed, the adhesive layer is pressed by an external force and overflows or protrudes to the edges of the base material, the heat conductive layer, and the metal layer, contaminating the thin film flip chip package structure. It ends up.

複数の薄膜フリップチップパッケージ構造を巻き取る場合、基材、熱伝導層、及び金属層のエッジに溢れ出したり突出する接着層が薄膜フリップチップパッケージ構造を相互に接着させてしまい、薄膜フリップチップパッケージ構造の品質及び歩留まりに影響を及ぼした。 When winding multiple thin film flip chip package structures, the adhesive layer that overflows or protrudes from the edges of the substrate, heat conductive layer, and metal layer causes the thin film flip chip package structure to adhere to each other, resulting in the thin film flip chip package. It affected the quality and yield of the structure.

台湾登録実用新案第Ｍ６０２７２５号公報Taiwan Registered Utility Model No. M602725 Gazette

基板とヒートシンクとの間に設置している接着層がヒートシンクに溢れ出したり突出するのを回避し、半導体放熱パッケージ構造を汚染しないようにする。また、複数の半導体放熱パッケージ構造を巻き取る際に、ヒートシンクに溢れ出したり突出する接着層がこれら半導体放熱パッケージ構造を相互に接着させる事象も回避する。
本発明は、上述に鑑みてなされたものであり、その目的は、半導体放熱パッケージ構造を提供することにある。 It prevents the adhesive layer installed between the substrate and the heat sink from overflowing or protruding into the heat sink, and does not contaminate the semiconductor heat dissipation package structure. Further, when the plurality of semiconductor heat dissipation package structures are wound up, the phenomenon that the adhesive layer overflowing or protruding from the heat sink adheres these semiconductor heat dissipation package structures to each other is avoided.
The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor heat dissipation package structure.

本発明の半導体放熱パッケージ構造は、回路層を有している基板と、前記回路層に電気的に接続しているチップと、前記基板に設置され、前記チップを包囲している接着層と、キャリア及び放熱層を有し、前記放熱層は前記キャリアに設置しているヒートシンクと、を備え、前記ヒートシンクは前記放熱層を介して前記チップの露出面に接触し、取付部により前記接着層に取り付け、前記取付部と前記基板との間に前記接着層を包囲している空間を形成している。 The semiconductor heat dissipation package structure of the present invention includes a substrate having a circuit layer, a chip electrically connected to the circuit layer, and an adhesive layer installed on the substrate and surrounding the chip. It has a carrier and a heat radiating layer, the heat radiating layer includes a heat sink installed on the carrier, and the heat sink comes into contact with the exposed surface of the chip via the heat radiating layer, and is attached to the adhesive layer by a mounting portion. It is attached, and a space surrounding the adhesive layer is formed between the attachment portion and the substrate.

本発明の半導体放熱パッケージ構造の製造方法は、チップは基板に結合し前記基板の回路層に電気的に接続している基板及びチップを提供する工程と、前記チップを包囲している接着層を前記基板に設置する工程と、ヒートシンクはキャリア及び放熱層を有し、前記放熱層は前記キャリアに設置し、前記ヒートシンクは前記放熱層を介して前記チップの露出面に接触し、前記ヒートシンクは取付部により前記接着層に取り付け、前記取付部と前記基板との間には前記接着層を包囲している空間を形成している前記ヒートシンクを前記基板に設置する工程と、を含む。 The method for manufacturing a semiconductor heat sink package structure of the present invention includes a step of providing a substrate and a chip in which the chip is bonded to the substrate and electrically connected to the circuit layer of the substrate, and an adhesive layer surrounding the chip. The step of installing on the substrate, the heat sink has a carrier and a heat sink, the heat sink is installed on the carrier, the heat sink contacts the exposed surface of the chip through the heat sink, and the heat sink is attached. A step of installing the heat sink, which is attached to the adhesive layer by a portion and forms a space surrounding the adhesive layer between the attachment portion and the substrate, is provided on the substrate.

本発明は、基板にヒートシンクを設置し、ヒートシンクの放熱層は基板に設置しているチップに接触し、チップに対する放熱を行う。 In the present invention, a heat sink is installed on the substrate, and the heat dissipation layer of the heat sink contacts the chip installed on the substrate to dissipate heat to the chip.

本発明は、取付部と基板との間に位置している空間が接着層を包囲し、圧搾されて溢れ出した接着層を収容し、接着層がヒートシンクに溢れ出したり突出する事象を回避している。また、複数の半導体放熱パッケージ構造を巻き取る際に、これら半導体放熱パッケージ構造が相互に接着する事象も回避し、製品の品質及び歩留まりに影響を及ぼさないようにしている。 In the present invention, the space located between the mounting portion and the substrate surrounds the adhesive layer, accommodates the adhesive layer that has been squeezed and overflowed, and avoids the phenomenon that the adhesive layer overflows or protrudes into the heat sink. ing. Further, when winding a plurality of semiconductor heat dissipation package structures, the phenomenon that these semiconductor heat dissipation package structures adhere to each other is avoided so as not to affect the quality and yield of the product.

本発明の第一実施形態に係る半導体放熱パッケージ構造の断面図である。It is sectional drawing of the semiconductor heat dissipation package structure which concerns on 1st Embodiment of this invention. 本発明の第一実施形態に係る半導体放熱パッケージ構造の平面図である。It is a top view of the semiconductor heat dissipation package structure which concerns on 1st Embodiment of this invention. 本発明の第一実施形態に係る半導体放熱パッケージ構造の断面図である。It is sectional drawing of the semiconductor heat dissipation package structure which concerns on 1st Embodiment of this invention. 本発明の第一実施形態に係る半導体放熱パッケージ構造の平面図である。It is a top view of the semiconductor heat dissipation package structure which concerns on 1st Embodiment of this invention. 本発明の第一実施形態に係る半導体放熱パッケージ構造の断面図である。It is sectional drawing of the semiconductor heat dissipation package structure which concerns on 1st Embodiment of this invention. 本発明の第一実施形態に係る半導体放熱パッケージ構造の平面図である。It is a top view of the semiconductor heat dissipation package structure which concerns on 1st Embodiment of this invention. 本発明のその他の実施形態に係る半導体放熱パッケージ構造の断面図である。It is sectional drawing of the semiconductor heat dissipation package structure which concerns on other embodiment of this invention.

以下、本発明による実施形態を図面に基づいて説明する。なお、複数の実施形態において実質的に同一の構成部位には同一の符号を付し、説明を省略する。 Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In the plurality of embodiments, substantially the same constituent parts are designated by the same reference numerals, and the description thereof will be omitted.

（第一実施形態）
本発明の第一実施形態について図１から図６に基づいて説明する。 (First Embodiment)
The first embodiment of the present invention will be described with reference to FIGS. 1 to 6.

図１から図６は本発明の第一実施形態に係る半導体放熱パッケージ構造１００の製造方法を示す概略図である。
図１及び図２に示すように、基板１１０及びチップ１２０を備える。チップ１２０は基板１１０に結合し、基板１１０の回路層１１１に電気的に接続している。
本実施形態では、回路層１１１は基板１１０の表面に設置し、保護層１１２により回路層１１１を被覆し、回路層１１１の複数のインナーピン１１１ａを露出させている。チップ１２０の複数のバンプ１２１は回路層１１１のこれらインナーピン１１１ａに結合している。充填剤１１３を基板１１０とチップ１２０との間に充填し、充填剤１１３によりこれらバンプ１２１を被覆している。 1 to 6 are schematic views showing a method of manufacturing the semiconductor heat dissipation package structure 100 according to the first embodiment of the present invention.
As shown in FIGS. 1 and 2, the substrate 110 and the chip 120 are provided. The chip 120 is coupled to the substrate 110 and electrically connected to the circuit layer 111 of the substrate 110.
In the present embodiment, the circuit layer 111 is installed on the surface of the substrate 110, the circuit layer 111 is covered with the protective layer 112, and the plurality of inner pins 111a of the circuit layer 111 are exposed. The plurality of bumps 121 of the chip 120 are coupled to these inner pins 111a of the circuit layer 111. The filler 113 is filled between the substrate 110 and the chip 120, and the bumps 121 are covered with the filler 113.

図３及び図４に示すように、接着層１３０は基板１１０に設置し、チップ１２０を包囲している。
本実施形態では、接着層１３０は基板１１０に設置しているだけではなく、充填剤１１３にも設置している。 As shown in FIGS. 3 and 4, the adhesive layer 130 is placed on the substrate 110 and surrounds the chip 120.
In this embodiment, the adhesive layer 130 is installed not only on the substrate 110 but also on the filler 113.

接着層１３０は塗布方式で基板１１０に設置している。 The adhesive layer 130 is installed on the substrate 110 by a coating method.

図５及び図６に示すように、ヒートシンク１４０を基板１１０に設置し、半導体放熱パッケージ構造１００を形成している。ヒートシンク１４０はキャリア１４１及び放熱層１４２を備え、放熱層１４２はキャリア１４１に設置し、ヒートシンク１４０は放熱層１４２の接触面１４２ａを介してチップ１２０の露出面１２２に接触している。接触面１４２ａの接触面積は露出面１２２の表面積未満ではない。このため、放熱層１４２がチップ１２０の露出面１２２を全面的に被覆し、放熱又は熱伝導面積を増加させ、放熱効果を高めている。 As shown in FIGS. 5 and 6, the heat sink 140 is installed on the substrate 110 to form the semiconductor heat dissipation package structure 100. The heat sink 140 includes a carrier 141 and a heat radiating layer 142, the heat radiating layer 142 is installed on the carrier 141, and the heat sink 140 is in contact with the exposed surface 122 of the chip 120 via the contact surface 142a of the heat radiating layer 142. The contact area of the contact surface 142a is not less than the surface area of the exposed surface 122. Therefore, the heat radiating layer 142 completely covers the exposed surface 122 of the chip 120 to increase heat dissipation or heat conduction area and enhance the heat dissipation effect.

図５及び図６に示すように、ヒートシンク１４０の取付部１４０ａはチップ１２０を包囲している接着層１３０に取り付け、取付部１４０ａはチップ１２０を包囲し、取付部１４０ａと基板１１０との間に接着層１３０を包囲している空間Ｓを形成している。
本実施形態では、ヒートシンク１４０は取付部１４０ａに位置している放熱層１４２により接着層１３０に取り付けている。 As shown in FIGS. 5 and 6, the mounting portion 140a of the heat sink 140 is mounted on the adhesive layer 130 surrounding the chip 120, and the mounting portion 140a surrounds the chip 120 and is between the mounting portion 140a and the substrate 110. It forms a space S surrounding the adhesive layer 130.
In the present embodiment, the heat sink 140 is attached to the adhesive layer 130 by the heat radiating layer 142 located at the attachment portion 140a.

図５及び図６に示すように、本実施形態では、取付部１４０ａのエッジ１４０ｂは基板１１０に垂直に投影し、基板１１０に空間Ｓの極度エッジＳ１を形成している。
空間Ｓの極度エッジＳ１と接着層１３０の外縁１３１との間には２０μｍ以上である間隔を有している。 As shown in FIGS. 5 and 6, in the present embodiment, the edge 140b of the mounting portion 140a is projected perpendicularly to the substrate 110, and the extreme edge S1 of the space S is formed on the substrate 110.
There is a distance of 20 μm or more between the extreme edge S1 of the space S and the outer edge 131 of the adhesive layer 130.

図５に示すように、取付部１４０ａと基板１１０との間に位置している空間Ｓは接着層１３０を包囲し、圧搾されて変形するか溢れ出した接着層１３０を収容するために用い、接着層１３０がヒートシンク１４０に溢れ出したり突出する事象を回避し、半導体放熱パッケージ構造１００が汚染されないようにしている。また、複数の半導体放熱パッケージ構造１００を巻き取る過程で相互に接着する事象も回避し、これら半導体放熱パッケージ構造１００の品質及び歩留まりに影響を及ぼさないようにしている。 As shown in FIG. 5, the space S located between the mounting portion 140a and the substrate 110 surrounds the adhesive layer 130 and is used to accommodate the adhesive layer 130 that has been squeezed and deformed or overflowed. The phenomenon that the adhesive layer 130 overflows or protrudes from the heat sink 140 is avoided, and the semiconductor heat dissipation package structure 100 is prevented from being contaminated. In addition, the phenomenon of mutual adhesion in the process of winding the plurality of semiconductor heat dissipation package structures 100 is avoided so as not to affect the quality and yield of these semiconductor heat dissipation package structures 100.

（その他の実施形態） (Other embodiments)

接着層は塗布方式で基板に設置している限りではなく、その他の実施形態では、予め環状接着層を形成し、環状接着層を基板１１０に取り付け、チップ１２０を包囲している。 The adhesive layer is not limited to being installed on the substrate by a coating method, and in other embodiments, an annular adhesive layer is formed in advance, the annular adhesive layer is attached to the substrate 110, and the chip 120 is surrounded.

図７に示すように、その他の実施形態では、ヒートシンク１４０は取付部１４０ａに位置しているキャリア１４１により接着層１３０に取り付けている。 As shown in FIG. 7, in other embodiments, the heat sink 140 is attached to the adhesive layer 130 by a carrier 141 located at the attachment portion 140a.

その他の実施形態の他の基本的構成は、第一実施形態と同様である。 Other basic configurations of the other embodiments are the same as those of the first embodiment.

以上、本発明は、上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲において種々の形態で実施可能である。 As described above, the present invention is not limited to the above embodiment, and can be implemented in various forms without departing from the gist thereof.

１００ 半導体放熱パッケージ構造、
１１０ 基板、
１１１ 回路層、
１１１ａ インナーピン、
１１２ 保護層、
１１３ 充填剤、
１２０ チップ、
１２１ バンプ、
１２２ 露出面、
１３０ 接着層、
１３１ 外縁、
１４０ ヒートシンク、
１４０ａ 取付部、
１４０ｂ エッジ、
１４１ キャリア、
１４２ 放熱層、
１４２ａ 接触面、
Ｓ 空間、
Ｓ１ 極度エッジ。 100 semiconductor heat dissipation package structure,
110 board,
111 circuit layer,
111a inner pin,
112 protective layer,
113 Filler,
120 chips,
121 bumps,
122 exposed surface,
130 adhesive layer,
131 outer edge,
140 heat sink,
140a mounting part,
140b edge,
141 carrier,
142 heat dissipation layer,
142a contact surface,
S space,
S1 Extreme edge.

Claims (12)

回路層を有している基板と、
前記回路層に電気的に接続しているチップと、
前記基板に設置され、前記チップを包囲している接着層と、
キャリア及び放熱層を有し、前記放熱層は前記キャリアに設置しているヒートシンクと、を備え、
前記ヒートシンクは前記放熱層を介して前記チップの露出面に接触し、取付部により前記接着層に取り付け、前記取付部と前記基板との間に前記接着層を包囲している空間を形成していることを特徴とする半導体放熱パッケージ構造。 A board with a circuit layer and
With a chip electrically connected to the circuit layer,
An adhesive layer installed on the substrate and surrounding the chip,
It has a carrier and a heat sink, and the heat sink includes a heat sink installed on the carrier.
The heat sink contacts the exposed surface of the chip via the heat dissipation layer, is attached to the adhesive layer by a mounting portion, and forms a space surrounding the adhesive layer between the mounting portion and the substrate. A semiconductor heat sink package structure characterized by the fact that it is present. 前記放熱層の接触面は前記露出面に接触し、前記接触面の接触面積は前記露出面の表面積未満ではないことを特徴とする請求項１に記載の半導体放熱パッケージ構造。 The semiconductor heat dissipation package structure according to claim 1, wherein the contact surface of the heat radiation layer is in contact with the exposed surface, and the contact area of the contact surface is not smaller than the surface area of the exposed surface. 前記取付部は前記チップを包囲し、前記取付部のエッジは前記基板に垂直に投影し、前記基板には前記空間の極度エッジを形成していることを特徴とする請求項１に記載の半導体放熱パッケージ構造。 The semiconductor according to claim 1, wherein the mounting portion surrounds the chip, the edge of the mounting portion is projected vertically onto the substrate, and the substrate forms an extreme edge of the space. Heat dissipation package structure. 前記空間の前記極度エッジと前記接着層の外縁との間には２０μｍ以上である間隔を有していることを特徴とする請求項３に記載の半導体放熱パッケージ構造。 The semiconductor heat dissipation package structure according to claim 3, wherein a distance of 20 μm or more is provided between the extreme edge of the space and the outer edge of the adhesive layer. 前記ヒートシンクは前記取付部に位置している前記放熱層により前記接着層に取り付けていることを特徴とする請求項１に記載の半導体放熱パッケージ構造。 The semiconductor heat dissipation package structure according to claim 1, wherein the heat sink is attached to the adhesive layer by the heat dissipation layer located at the attachment portion. 前記ヒートシンクは前記取付部に位置している前記キャリアにより前記接着層に取り付けていることを特徴とする請求項１に記載の半導体放熱パッケージ構造。 The semiconductor heat dissipation package structure according to claim 1, wherein the heat sink is attached to the adhesive layer by the carrier located in the attachment portion. チップは基板に結合し前記基板の回路層に電気的に接続している基板及びチップを提供する工程と、
前記チップを包囲している接着層を前記基板に設置する工程と、
ヒートシンクはキャリア及び放熱層を有し、前記放熱層は前記キャリアに設置し、前記ヒートシンクは前記放熱層を介して前記チップの露出面に接触し、前記ヒートシンクは取付部により前記接着層に取り付け、前記取付部と前記基板との間には前記接着層を包囲している空間を形成している前記ヒートシンクを前記基板に設置する工程と、を含むことを特徴とする半導体放熱パッケージ構造の製造方法。 The process of providing a substrate and a chip that are coupled to the substrate and electrically connected to the circuit layer of the substrate.
The process of installing the adhesive layer surrounding the chip on the substrate, and
The heat sink has a carrier and a heat radiating layer, the heat radiating layer is installed on the carrier, the heat sink contacts the exposed surface of the chip via the heat radiating layer, and the heat sink is attached to the adhesive layer by a mounting portion. A method for manufacturing a semiconductor heat dissipation package structure, which comprises a step of installing the heat sink forming a space surrounding the adhesive layer between the mounting portion and the substrate on the substrate. .. 前記放熱層の接触面は前記露出面に接触し、前記接触面の接触面積は前記露出面の表面積未満ではないことを特徴とする請求項７に記載の半導体放熱パッケージ構造の製造方法。 The method for manufacturing a semiconductor heat dissipation package structure according to claim 7, wherein the contact surface of the heat radiation layer is in contact with the exposed surface, and the contact area of the contact surface is not less than the surface area of the exposed surface. 前記取付部は前記チップを包囲し、前記取付部のエッジは前記基板に垂直に投影し、前記基板に前記空間の極度エッジを形成していることを特徴とする請求項７に記載の半導体放熱パッケージ構造の製造方法。 The semiconductor heat dissipation according to claim 7, wherein the mounting portion surrounds the chip, and the edge of the mounting portion is projected vertically onto the substrate to form an extreme edge of the space on the substrate. Manufacturing method of package structure. 前記空間の前記極度エッジと前記接着層の外縁との間には２０μｍ以上である間隔を有していることを特徴とする請求項９に記載の半導体放熱パッケージ構造の製造方法。 The method for manufacturing a semiconductor heat dissipation package structure according to claim 9, wherein a distance of 20 μm or more is provided between the extreme edge of the space and the outer edge of the adhesive layer. 前記ヒートシンクは前記取付部に位置している前記放熱層により前記接着層に取り付けていることを特徴とする請求項７に記載の半導体放熱パッケージ構造の製造方法。 The method for manufacturing a semiconductor heat dissipation package structure according to claim 7, wherein the heat sink is attached to the adhesive layer by the heat dissipation layer located at the attachment portion. 前記ヒートシンクは前記取付部に位置している前記キャリアにより前記接着層に取り付けていることを特徴とする請求項７に記載の半導体放熱パッケージ構造の製造方法。 The method for manufacturing a semiconductor heat dissipation package structure according to claim 7, wherein the heat sink is attached to the adhesive layer by the carrier located in the attachment portion.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6354485B1 (en) * 1996-10-24 2002-03-12 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies
JP2008028396A (en) * 2006-07-20 2008-02-07 Samsung Electronics Co Ltd Cof semiconductor package
CN101577263A (en) * 2008-05-06 2009-11-11 南茂科技股份有限公司 Chip packaging structure and chip packaging coiling tape
JP2010251357A (en) * 2009-04-10 2010-11-04 Panasonic Corp Semiconductor module device
KR20100135161A (en) * 2009-06-16 2010-12-24 주식회사 동부하이텍 Heat releasing semiconductor package, method for manufacturing the same and display apparatus including the same
JP2012164846A (en) * 2011-02-08 2012-08-30 Renesas Electronics Corp Semiconductor device, semiconductor device manufacturing method and display device
US20180342437A1 (en) * 2015-12-02 2018-11-29 Novatek Microelectronics Corp. Chip on film package and heat-dissipation structure for a chip package
TWM602725U (en) * 2020-07-31 2020-10-11 大陸商河南烯力新材料科技有限公司 Chip on film package structure and display device
TWM611792U (en) * 2020-12-31 2021-05-11 頎邦科技股份有限公司 Heat-dissipating semiconductor package
JP2022081373A (en) * 2020-11-19 2022-05-31 ▲き▼邦科技股▲分▼有限公司 Circuit board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3119649B2 (en) * 1999-03-30 2000-12-25 大衆電腦股▲ふん▼有限公司 Semiconductor device having heat dissipation structure on both sides and method of manufacturing the same
TWI618205B (en) * 2015-05-22 2018-03-11 南茂科技股份有限公司 Chip on film package and heat dissipation method thereof

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6354485B1 (en) * 1996-10-24 2002-03-12 Tessera, Inc. Thermally enhanced packaged semiconductor assemblies
JP2008028396A (en) * 2006-07-20 2008-02-07 Samsung Electronics Co Ltd Cof semiconductor package
CN101577263A (en) * 2008-05-06 2009-11-11 南茂科技股份有限公司 Chip packaging structure and chip packaging coiling tape
JP2010251357A (en) * 2009-04-10 2010-11-04 Panasonic Corp Semiconductor module device
KR20100135161A (en) * 2009-06-16 2010-12-24 주식회사 동부하이텍 Heat releasing semiconductor package, method for manufacturing the same and display apparatus including the same
JP2012164846A (en) * 2011-02-08 2012-08-30 Renesas Electronics Corp Semiconductor device, semiconductor device manufacturing method and display device
US20180342437A1 (en) * 2015-12-02 2018-11-29 Novatek Microelectronics Corp. Chip on film package and heat-dissipation structure for a chip package
TWM602725U (en) * 2020-07-31 2020-10-11 大陸商河南烯力新材料科技有限公司 Chip on film package structure and display device
JP2022081373A (en) * 2020-11-19 2022-05-31 ▲き▼邦科技股▲分▼有限公司 Circuit board
TWM611792U (en) * 2020-12-31 2021-05-11 頎邦科技股份有限公司 Heat-dissipating semiconductor package

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