JP2022092809A - Method for inspecting epitaxial wafer for defect - Google Patents

Method for inspecting epitaxial wafer for defect Download PDF

Info

Publication number
JP2022092809A
JP2022092809A JP2020205733A JP2020205733A JP2022092809A JP 2022092809 A JP2022092809 A JP 2022092809A JP 2020205733 A JP2020205733 A JP 2020205733A JP 2020205733 A JP2020205733 A JP 2020205733A JP 2022092809 A JP2022092809 A JP 2022092809A
Authority
JP
Japan
Prior art keywords
epitaxial wafer
wafer
defect
residual stress
dislocation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2020205733A
Other languages
Japanese (ja)
Inventor
翔太 木瀬
Shota Kise
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Priority to JP2020205733A priority Critical patent/JP2022092809A/en
Priority to CN202111507360.7A priority patent/CN114624251A/en
Publication of JP2022092809A publication Critical patent/JP2022092809A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84—Systems specially adapted for particular applications
    • G01N21/88—Investigating the presence of flaws or contamination
    • G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • G01N21/9501—Semiconductor wafers
    • G01N21/9505—Wafer internal defects, e.g. microcracks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/01—Arrangements or apparatus for facilitating the optical investigation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/01—Arrangements or apparatus for facilitating the optical investigation
    • G01N2021/0106—General arrangement of respective parts
    • G01N2021/0112—Apparatus in one mechanical, optical or electronic block

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

To provide a method for inspecting an epitaxial wafer for a defect that can identify a slip dislocation defect or a misfit dislocation defect.SOLUTION: If an epitaxial wafer WF has a dislocation defect DF including a slip dislocation defect or a misfit dislocation defect, the residual stress of the epitaxial wafer is determined by a wafer stress measurement. When the residual stress is at least a predetermined value S0, the presence of a slip dislocation defect is determined. When the residual stress is less than the predetermined value S0, the presence of a misfit dislocation defect is determined.SELECTED DRAWING: Figure 1

Description

本発明は、エピタキシャルウェーハの欠陥検査方法に関するものである。 The present invention relates to a defect inspection method for an epitaxial wafer.

レーザー光で半導体基板の表面を螺旋状に走査し、当該表面からの散乱光の特定方向における特定散乱光情報を取得し、この特定散乱光情報から、半導体基板の結晶すべり面に沿って発生する結晶欠陥の有無を検出する表面検査装置が知られている（たとえば、特許文献１）。また、偏光された平行光を半導体基板に照射し、当該半導体基板を透過または反射した光により得られた画像から、半導体基板の結晶品質を評価する方法が知られている（たとえば、特許文献２）。 The surface of the semiconductor substrate is spirally scanned with a laser beam to acquire specific scattered light information in a specific direction of scattered light from the surface, and the specific scattered light information is generated along the crystal slip surface of the semiconductor substrate. A surface inspection device for detecting the presence or absence of crystal defects is known (for example, Patent Document 1). Further, a method of irradiating a semiconductor substrate with polarized parallel light and evaluating the crystal quality of the semiconductor substrate from an image obtained by light transmitted or reflected through the semiconductor substrate is known (for example, Patent Document 2). ).

特開２００７－２１４４９１号公報JP-A-2007-214491 特表２０１７／０７８１２７号公報Japanese Patent Publication No. 2017/07827

ところで、シリコンエピタキシャルウェーハの結晶欠陥として、外部から加わる熱的又は物理的なストレスに起因するスリップ転位欠陥と、基板とエピタキシャル層界面での格子不整合に起因するミスフィット転位欠陥がある。しかしながら、上記特許文献１に記載された表面検査装置では、スリップ転位欠陥及びミスフィット転位欠陥の何れもが、同じような線状欠陥として観察されるので、これらを識別できないという問題がある。 By the way, as crystal defects of a silicon epitaxial wafer, there are slip dislocation defects caused by thermal or physical stress applied from the outside and misfit dislocation defects caused by lattice mismatch at the interface between the substrate and the epitaxial layer. However, in the surface inspection apparatus described in Patent Document 1, since both slip dislocation defects and misfit dislocation defects are observed as similar linear defects, there is a problem that they cannot be identified.

本発明が解決しようとする課題は、スリップ転位欠陥とミスフィット転位欠陥を識別できるエピタキシャルウェーハの検査方法を提供することである。 An object to be solved by the present invention is to provide an inspection method for an epitaxial wafer capable of discriminating between slip dislocation defects and misfit dislocation defects.

本発明は、エピタキシャルウェーハに、スリップ転位欠陥及びミスフィット転位欠陥を含む転位欠陥がある場合には、ウェーハストレス測定により前記エピタキシャルウェーハの残留応力を求め、
前記残留応力が所定値以上の場合は、前記スリップ転位欠陥であると判定し、前記残留応力が前記所定値未満である場合は、前記ミスフィット転位欠陥であると判定することによって上記課題を解決する。なお、ウェーハストレス測定は、ウェーハに赤外光を照射し、応力を受けた部分が、光弾性効果により生じた偏光状態変化を解析し、歪として測定する。 In the present invention, when the epitaxial wafer has dislocation defects including slip dislocation defects and misfit dislocation defects, the residual stress of the epitaxial wafer is obtained by wafer stress measurement.
When the residual stress is equal to or more than a predetermined value, it is determined to be the slip dislocation defect, and when the residual stress is less than the predetermined value, it is determined to be the misfit dislocation defect to solve the above problem. do. In the wafer stress measurement, the wafer is irradiated with infrared light, and the stressed portion analyzes the change in the polarization state caused by the photoelastic effect and measures it as strain.

上記発明において、前記エピタキシャルウェーハの検査面に検査光を照射し、その散乱光に基づいて、スリップ転位欠陥及びミスフィット転位欠陥を含む転位欠陥の有無を判定してもよい。 In the above invention, the inspection surface of the epitaxial wafer may be irradiated with inspection light, and the presence or absence of dislocation defects including slip dislocation defects and misfit dislocation defects may be determined based on the scattered light.

本発明によれば、エピタキシャルウェーハに、スリップ転位欠陥及びミスフィット転位欠陥を含む転位欠陥が発見されたら、ウェーハストレス測定により残留応力を測定し、残留応力が大きい場合にはスリップ転位欠陥であると判定するので、スリップ転位欠陥とミスフィット転位欠陥を識別することができる。 According to the present invention, if a dislocation defect including a slip dislocation defect and a misfit dislocation defect is found in an epitaxial wafer, the residual stress is measured by wafer stress measurement, and if the residual stress is large, it is a slip dislocation defect. Since the determination is made, slip dislocation defects and misfit dislocation defects can be distinguished.

本発明のエピタキシャルウェーハの検査方法の一実施の形態を示す工程図である。It is a process drawing which shows one Embodiment of the inspection method of the epitaxial wafer of this invention. 図１の表面検査工程で用いられる表面検査装置の一例を示す構成図である。It is a block diagram which shows an example of the surface inspection apparatus used in the surface inspection process of FIG. 図１の残留応力検査工程で用いられるウェーハストレス測定装置の一例を示す構成図である。It is a block diagram which shows an example of the wafer stress measuring apparatus used in the residual stress inspection process of FIG. エピタキシャルウェーハの転位欠陥の一例を示す図である。It is a figure which shows an example of the dislocation defect of an epitaxial wafer. 図３のウェーハストレス測定装置の出力波形を示す図である。It is a figure which shows the output waveform of the wafer stress measuring apparatus of FIG. 図５Ａの出力波形をフィルタリングした波形あとの波形を示す図である。It is a figure which shows the waveform after the waveform which filtered the output waveform of FIG. 5A. ＧＢＡ法を用いて、図５Ｂの波形から相対歪量を求める方法を示す図である。It is a figure which shows the method of obtaining the relative strain amount from the waveform of FIG. 5B using the GBA method.

本発明のエピタキシャルウェーハの欠陥検査方法の一実施の形態では、外部から加わる熱的又は物理的な応力に起因するスリップ転位欠陥と、基板とエピタキシャル層界面での格子不整合に起因するミスフィット転位欠陥とを検査対象とする。 In one embodiment of the epitaxial wafer defect inspection method of the present invention, slip dislocation defects due to external thermal or physical stress and misfit dislocations due to lattice mismatch at the interface between the substrate and the epitaxial layer Defects are to be inspected.

ここで、スリップ転位とは、ウェーハの半径方向に温度の不均一性がある場合などのように、円周方向に降伏値を超える応力が働くことで発生する線状の段差をいう。熱的要因による結晶領域の部分的な滑りであるため、エピタキシャルウェーハにあっては、エピタキシャル成長させる際の成長炉のヒータ温度条件を調整したりすることで、スリップ転位を抑制することができる。 Here, the slip dislocation refers to a linear step generated by a stress exceeding the yield value in the circumferential direction, such as when there is temperature non-uniformity in the radial direction of the wafer. Since it is a partial slip of the crystal region due to a thermal factor, in the case of an epitaxial wafer, slip dislocation can be suppressed by adjusting the heater temperature condition of the growth furnace at the time of epitaxial growth.

これに対して、不純物濃度が高いシリコン基板では、不純物原子の原子半径がシリコン原子の原子半径と異なるため、結晶格子定数が僅かに変化し、低不純物濃度のエピタキシャル層に膜歪が作用する。ミスフィット転位とは、当該膜中の歪が臨界値に達したときに発生する線状の段差をいう。エピタキシャル膜とシリコン基板との結晶格子定数の相違が原因で生じる転位であるため、エピタキシャル膜とシリコン基板の不純物濃度を調整したり、エピタキシャル膜とシリコン基板との間に中間濃度の緩衝層を設けたりすることで、ミスフィット転位を抑制することができる。 On the other hand, in a silicon substrate having a high impurity concentration, the atomic radius of the impurity atom is different from the atomic radius of the silicon atom, so that the crystal lattice constant changes slightly and film strain acts on the epitaxial layer having a low impurity concentration. The misfit dislocation is a linear step that occurs when the strain in the film reaches a critical value. Since the dislocation is caused by the difference in crystal lattice constant between the epitaxial film and the silicon substrate, the impurity concentration between the epitaxial film and the silicon substrate is adjusted, or a buffer layer with an intermediate concentration is provided between the epitaxial film and the silicon substrate. By doing so, the misfit dislocation can be suppressed.

このように、いずれの欠陥も線状の段差であり目視観察では判別できないが、上述したとおりその対策法が全く異なることから、これらの転位欠陥を識別することは、エピタキシャルウェーハの製造工程の稼働率や製品歩留まりを高めるためには重要なことである。勿論、これらスリップ転位欠陥とミスフィット転位欠陥は、エピタキシャルウェーハの断面をＸ線測定装置にて測定し、観察することで、識別することはできる。しかしながら、破壊検査は、製造工程においてリアルタイムで実施することはできないから、識別結果が得られるまでは、製造工程の稼働率や製品歩留まりは低下する。 As described above, all of the defects are linear steps and cannot be discriminated by visual observation. However, as described above, the countermeasures are completely different. Therefore, discriminating these dislocation defects is an operation of the epitaxial wafer manufacturing process. It is important to increase the rate and product yield. Of course, these slip dislocation defects and misfit dislocation defects can be identified by measuring and observing the cross section of the epitaxial wafer with an X-ray measuring device. However, since destructive inspection cannot be performed in real time in the manufacturing process, the operating rate and product yield of the manufacturing process will decrease until the identification result is obtained.

そこで、本実施形態の検査方法では、転位欠陥の原因の相違に着目し、識別不能なスリップ転位欠陥又はミスフィット転位欠陥が観察されたら、ウェーハストレス測定によりエピタキシャルウェーハの残留応力を求め、求められた残留応力が所定値以上の場合は、応力が原因で発生するスリップ転位欠陥であると判定し、残留応力が所定値未満である場合は、応力とは無関係の結晶格子定数の相違が原因で発生するミスフィット転位欠陥であると判定する。 Therefore, in the inspection method of the present embodiment, attention is paid to the difference in the causes of dislocation defects, and if indistinguishable slip dislocation defects or misfit dislocation defects are observed, the residual stress of the epitaxial wafer is obtained by measuring the wafer stress. If the residual stress is greater than or equal to the predetermined value, it is determined to be a slip dislocation defect caused by the stress, and if the residual stress is less than the predetermined value, it is due to the difference in crystal lattice constant unrelated to the stress. Judged as a misfit dislocation defect that occurs.

図１は、本発明のエピタキシャルウェーハの検査方法の一実施の形態を示す工程図である。本実施形態のエピタキシャルウェーハの検査方法では、ステップＳ１においてエピタキシャルウェーハの表面検査を行い、ステップＳ２においてエピタキシャルウェーハの表面に、スリップ転位欠陥及びミスフィット転位欠陥を含む転位欠陥があるか否かを判定する。スリップ転位欠陥及びミスフィット転位欠陥を含む転位欠陥ＤＦは、図４に示すように線状に延びる段差として観察されるので目視によっても検査することができるが、図２に示す表面検査装置１を用いて行うと、転位欠陥の検査をより正確に行うことができる。 FIG. 1 is a process diagram showing an embodiment of an inspection method for an epitaxial wafer of the present invention. In the epitaxial wafer inspection method of the present embodiment, the surface of the epitaxial wafer is inspected in step S1 and it is determined in step S2 whether or not the surface of the epitaxial wafer has dislocation defects including slip dislocation defects and misfit dislocation defects. do. The dislocation defect DF including the slip dislocation defect and the misfit dislocation defect is observed as a step extending linearly as shown in FIG. 4, and can be visually inspected. When used, the inspection of dislocation defects can be performed more accurately.

図２は、図１のステップＳ１の表面検査工程で用いられる表面検査装置１の一例を示す構成図である。検査対象であるエピタキシャルウェーハＷＦは、可動テーブル１１に載置され、可動テーブル１１がＸＹ平面上を動くことにより、エピタキシャルウェーハＷＦの表面全体にレーザー光が照射される。検査光であるレーザー光は、第１レーザー発振器１２と第２レーザー発振器１３にて生成され、第１レーザー発振器１２で生成されたレーザー光は、エピタキシャルウェーハＷＦの表面に垂直入射光として照射され、第２レーザー発振器１３で生成されたレーザー光は、エピタキシャルウェーハＷＦの表面に斜方入射光として照射される。特に限定はされないが、垂直入射光により、スクラッチ、エピタキシャル欠陥、フィルム内欠陥などを検査することが好ましく、斜方入射光は、高感度測定、ラフネスの高いウェーハ測定、ヘイズ（Ｈａｚｅ）などに用いることが好ましい。 FIG. 2 is a block diagram showing an example of the surface inspection apparatus 1 used in the surface inspection step of step S1 of FIG. The epitaxial wafer WF to be inspected is placed on the movable table 11, and the movable table 11 moves on the XY plane, so that the entire surface of the epitaxial wafer WF is irradiated with laser light. The laser light, which is the inspection light, is generated by the first laser oscillator 12 and the second laser oscillator 13, and the laser light generated by the first laser oscillator 12 is irradiated on the surface of the epitaxial wafer WF as vertically incident light. The laser light generated by the second laser oscillator 13 irradiates the surface of the epitaxial wafer WF as oblique incident light. Although not particularly limited, it is preferable to inspect scratches, epitaxial defects, in-film defects, etc. by vertically incident light, and oblique incident light is used for high-sensitivity measurement, high-roughness wafer measurement, haze, and the like. Is preferable.

エピタキシャルウェーハＷＦの表面に照射されたレーザー光の反射光は、楕円体形状とされた集光器１４を介して第１光電子増倍管１５で受光されると同時に、レンズ１６及びミラー１６ｂを介して第２光電子増倍管１６で受光される。特に限定はされないが、第１光電子増倍管１５で受光されるレーザー光は、微小なパーティクルやヘイズの測定に用いることが好ましく、第２光電子増倍管１６で受光されるレーザー光は、線状欠陥、スクラッチ、ＣＯＰ（ボイド欠陥）、エピタキシャル欠陥などに用いることが好ましい。 The reflected light of the laser beam radiated to the surface of the epitaxial wafer WF is received by the first photomultiplier tube 15 via the condenser 14 having an elliptical shape, and at the same time, through the lens 16 and the mirror 16b. The light is received by the second photomultiplier tube 16. Although not particularly limited, the laser light received by the first photomultiplier tube 15 is preferably used for measuring minute particles and haze, and the laser light received by the second photomultiplier tube 16 is a line. It is preferably used for shape defects, scratches, COP (void defects), epitaxial defects and the like.

本実施形態の表面検査装置１を用いてエピタキシャルウェーハＷＦの表面を走査した場合、鏡面状態の表面からの反射レーザー光はそのまま受光される一方、当該表面に異物の付着やピットなどの段差があるとレーザー光は散乱光となって第１光電子増倍管１５及び第２光電子増倍管１６に受光される。これにより、スリップ転位欠陥及びミスフィット転位欠陥を含む転位欠陥ＤＦがあるか否かを判定することができる。 When the surface of the epitaxial wafer WF is scanned using the surface inspection device 1 of the present embodiment, the reflected laser light from the mirrored surface is received as it is, but foreign matter adheres to the surface and steps such as pits are present on the surface. And the laser light becomes scattered light and is received by the first photomultiplier tube 15 and the second photomultiplier tube 16. This makes it possible to determine whether or not there is a dislocation defect DF including a slip dislocation defect and a misfit dislocation defect.

図１に戻り、ステップＳ１，Ｓ２の表面検査により線状欠陥がないと判定された場合には、ステップＳ５へ進み、スリップ転位欠陥及びミスフィット転移欠陥はないとする。これに対してステップＳ１，Ｓ２の表面検査により線状欠陥があると判定された場合には、ステップＳ３へ進み、ウェーハストレス測定によりエピタキシャルウェーハの残留応力を検査する。図３は、図１のステップＳ３の残留応力検査工程で用いられるウェーハストレス測定装置２の一例（ＳＩＲＤ（Ｓｃａｎｎｉｎｇ ＩｎｆＲｅｄ Ｄｅｐｏｌａｒｉｚａｔｉｏｎ）測定装置）を示す構成図である。 Returning to FIG. 1, if it is determined by the surface inspections of steps S1 and S2 that there are no linear defects, the process proceeds to step S5, and it is assumed that there are no slip dislocation defects or misfit dislocation defects. On the other hand, if it is determined by the surface inspection of steps S1 and S2 that there is a linear defect, the process proceeds to step S3, and the residual stress of the epitaxial wafer is inspected by the wafer stress measurement. FIG. 3 is a configuration diagram showing an example (SIRD (Scanning InfRed Depolarization) measuring device) of the wafer stress measuring device 2 used in the residual stress inspection step of step S3 of FIG.

本実施形態のウェーハストレス測定装置２は、赤外レーザー発振器２１を備え、当該赤外レーザー発振器２１から発信された赤外光は、レンズ２２を通過して偏光子２３に入射する。赤外光は、この偏光子２３において直線偏光されたのち、検査対象であるエピタキシャルウェーハＷＦに対して略垂直に入射する。エピタキシャルウェーハＷＦに入射した赤外光は、エピタキシャルウェーハＷに歪がある場合には、この歪に応じて円偏光されて減衰する。 The wafer stress measuring device 2 of the present embodiment includes an infrared laser oscillator 21, and the infrared light transmitted from the infrared laser oscillator 21 passes through the lens 22 and is incident on the splitter 23. The infrared light is linearly polarized by the polarizing element 23 and then incidents substantially perpendicular to the epitaxial wafer WF to be inspected. If the epitaxial wafer W has a strain, the infrared light incident on the epitaxial wafer WF is circularly polarized and attenuated according to the strain.

エピタキシャルウェーハＷＦを透過した赤外光は、対物レンズ２４を通過して、偏光分離素子２５に入射する。赤外光は、この偏光分離素子２５において、直線偏光されている成分と、エピタキシャルウェーハＷＦの歪箇所において円偏光された成分とに分離される。分離された赤外光の成分は、それぞれ別のフォトダイオード２６，２７に入射する。 The infrared light transmitted through the epitaxial wafer WF passes through the objective lens 24 and is incident on the polarization separating element 25. Infrared light is separated into a linearly polarized component and a circularly polarized component at the strained portion of the epitaxial wafer WF in the polarization separating element 25. The separated infrared light components are incident on different photodiodes 26 and 27, respectively.

各フォトダイオード２６，２７は、入射した赤外光の成分の強度を検出し、検出結果を処理部２８に出力する。処理部２８は、入力された強度に基づいて、直線偏光成分と、円偏光成分との差分を歪量として検出する。このような、歪量を検出する処理を、エピタキシャルウェーハＷＦを回転させ、また、赤外光の照射されるエピタキシャルウェーハＷＦの半径方向の位置を変更して行うことにより、エピタキシャルウェーハＷＦ上の表面の各位置における歪量を検出する。このような検出処理において、検出された歪量の波形（歪波形）は、図５Ａに示すような波形をしている。この歪波形には、エピタキシャルウェーハＷＦにおけるボロン、リン等のドーパント濃度に起因する歪成分や、エピタキシャルウェーハＷＦの全体的な反り等に起因する歪成分が含まれている。 Each of the photodiodes 26 and 27 detects the intensity of the component of the incident infrared light, and outputs the detection result to the processing unit 28. The processing unit 28 detects the difference between the linearly polarized light component and the circularly polarized light component as a strain amount based on the input intensity. Such a process for detecting the amount of strain is performed by rotating the epitaxial wafer WF and changing the position in the radial direction of the epitaxial wafer WF irradiated with infrared light, thereby performing the process on the surface on the epitaxial wafer WF. The amount of strain at each position of is detected. In such a detection process, the waveform of the detected strain amount (strain waveform) has a waveform as shown in FIG. 5A. This strain waveform includes a strain component caused by the concentration of dopants such as boron and phosphorus in the epitaxial wafer WF, and a strain component caused by the overall warpage of the epitaxial wafer WF.

そこで、処理部２８は、歪波形から局所的な歪成分を抽出するために、ドーパント濃度や、ウェーハの全体的な反りによる歪成分に相当する長波長の歪成分を歪波形から除外するフィルタリング処理、すなわち浮動平均差分処理を行う。図５Ａに示す歪波形に、浮動平均差分処理を行うと、図５Ｂに示すように長波長の成分が除外された歪波形が得られる。 Therefore, in order to extract a local strain component from the strain waveform, the processing unit 28 performs a filtering process for excluding the long wavelength strain component corresponding to the dopant concentration and the strain component due to the overall warp of the wafer from the strain waveform. That is, floating average difference processing is performed. When the distorted waveform shown in FIG. 5A is subjected to the floating average difference processing, a distorted waveform excluding the long wavelength component is obtained as shown in FIG. 5B.

次いで、処理部２８は、ＧＢＡ法を用いて、歪波形に基づいて、相対歪量を求める。すなわち、処理部２８は、ウェーハＷの全面に所定のグリッドの格子を当てがい、所定の領域における全てのセルの数に対する所定の閾値を超えた歪が発生しているセルの数の割合を示す相対歪量を検出する。図５Ｃには、歪波形におけるグリッド位置を示しており、グリッド間がセルの歪を示している。 Next, the processing unit 28 obtains a relative strain amount based on the strain waveform by using the GBA method. That is, the processing unit 28 applies a grid of a predetermined grid to the entire surface of the wafer W, and shows the ratio of the number of cells in which distortion exceeding a predetermined threshold value is generated to the number of all cells in a predetermined region. Detects the amount of relative strain. FIG. 5C shows the grid positions in the distortion waveform, and the spaces between the grids show the distortion of the cells.

ここで、グリッドとしては、直交座標系のグリッド（Ｘ－Ｙグリッド）や、極座標系のグリッド（Ｒ－Ｔグリッド）を用いることができる。本実施形態では、例えば、１ｍｍ×１ｍｍのセルを構成するグリッドを用い、ウェーハＷの最外周の例えば５ｍｍ幅の円環状の領域から最外周の０．５ｍｍ幅の円環状の領域を除いた領域を対象に相対歪量を検出している。 Here, as the grid, a grid of an orthogonal coordinate system (XY grid) or a grid of a polar coordinate system (RT grid) can be used. In the present embodiment, for example, a grid constituting a cell of 1 mm × 1 mm is used, and a region excluding an annular region having a width of 0.5 mm on the outermost circumference from an annular region having a width of, for example, 5 mm on the outermost circumference of the wafer W. The relative strain amount is detected for the target.

このようなウェーハストレス測定装置２により、エピタキシャルウェーハＷＦの残留応力を示す相対歪量を求めることができる。図１に戻り、ステップＳ４においては、求められた残留応力が、予め設定された残留応力の閾値Ｓ０以上か否かが判定される。この残留応力の閾値Ｓ０は、たとえば次のようにして予め求めることができる。すなわち、種々の製造条件で作製した転位欠陥を含むエピタキシャルウェーハを用い、これらの残留応力を測定したのち、Ｘ線測定装置にて断面を測定し、観察することで、それぞれの転位欠陥がスリップ転位欠陥であるか、ミスフィット転位欠陥であるかを識別し、この識別したエピタキシャルウェーハの識別境界となる残留応力値を閾値Ｓ０とする。 With such a wafer stress measuring device 2, it is possible to obtain a relative strain amount indicating the residual stress of the epitaxial wafer WF. Returning to FIG. 1 , in step S4, it is determined whether or not the obtained residual stress is equal to or higher than the preset residual stress threshold value S0. The threshold value S0 of this residual stress can be obtained in advance as follows, for example. That is, by using epitaxial wafers containing dislocation defects manufactured under various manufacturing conditions, measuring these residual stresses, and then measuring and observing the cross section with an X-ray measuring device, each dislocation defect is slipped. It is discriminated whether it is a defect or a misfit dislocation defect, and the residual stress value which is the identification boundary of the identified epitaxial dislocation wafer is set to the threshold value S0 .

上述したとおり、スリップ転位は、熱的又は物理的な応力が原因で発生するのに対し、ミスフィット転位は、応力とは無関係の結晶格子定数が原因で発生する。したがって、ステップＳ４にて、求められた残留応力が所定の閾値Ｓ０以上の場合は、応力が原因で発生するスリップ転位欠陥であると判定し（ステップＳ６）、残留応力が所定の閾値Ｓ０未満である場合は、応力とは無関係の結晶格子定数が原因で発生するスフィット転位欠陥であると判定する（ステップＳ７）。 As mentioned above, slip dislocations occur due to thermal or physical stress, whereas misfit dislocations occur due to the crystal lattice constant independent of stress. Therefore, if the obtained residual stress is equal to or higher than the predetermined threshold S 0 in step S4, it is determined that the slip dislocation defect is caused by the stress (step S6), and the residual stress is the predetermined threshold S 0 . If it is less than, it is determined that the dislocation defect is caused by a crystal lattice constant unrelated to stress (step S7).

以上のように、本実施形態のエピタキシャルウェーハの検査方法によれば、ウェーハの表面に転位欠陥と見られる線状の欠陥が観察された場合に、これがスリップ転位欠陥であるかミスフィット転位欠陥であるかを非破壊検査で識別することができるので、転位欠陥の発見からその対処までの時間を短縮することができる。その結果、エピタキシャルウェーハの製造工程の稼働率や製品歩留まりを高めることができる。 As described above, according to the epitaxial wafer inspection method of the present embodiment, when a linear defect that is considered to be a dislocation defect is observed on the surface of the wafer, it is a slip dislocation defect or a misfit dislocation defect. Since it can be identified by non-destructive inspection, it is possible to shorten the time from the discovery of dislocation defects to their countermeasures. As a result, the operating rate and product yield of the epitaxial wafer manufacturing process can be increased.

《ウェーハストレスと転位の識別》
エピタキシャル成長炉のヒータ加熱条件の水準が異なる条件１～４にてエピタキシャルウェーハを製造し、転位の有無を検査したところ何れも線状の転位欠陥が観察された。そのため、ウェーハストレス測定装置２を用いてそれぞれのエピタキシャルウェーハの残留応力を測定した。この結果を表１に示す。なお、残留応力は、条件１の残留応力値を１として正規化した値である。 << Identification of wafer stress and dislocation >>
When epitaxial wafers were manufactured under conditions 1 to 4 in which the level of heater heating conditions of the epitaxial growth furnace was different and the presence or absence of dislocations was inspected, linear dislocation defects were observed in all of them. Therefore, the residual stress of each epitaxial wafer was measured using the wafer stress measuring device 2. The results are shown in Table 1. The residual stress is a value normalized by setting the residual stress value of condition 1 to 1.

Figure 2022092809000002
Figure 2022092809000002

次に、不純物濃度を小さくしたシリコンウェーハを用い、上記条件１～４の各条件は変えずにエピタキシャルウェーハを製造した。これらエピタキシャルウェーハの転位の有無を観察するとともに、ウェーハストレス測定装置２を用いてそれぞれの残留応力を測定した。この結果を表２に示す。なお、残留応力は、条件１の残留応力値を１として正規化した値である。 Next, using a silicon wafer with a reduced impurity concentration, an epitaxial wafer was manufactured without changing each of the above conditions 1 to 4. The presence or absence of dislocations in these epitaxial wafers was observed, and the residual stress of each was measured using the wafer stress measuring device 2. The results are shown in Table 2. The residual stress is a value normalized by setting the residual stress value of condition 1 to 1.

Figure 2022092809000003
Figure 2022092809000003

これら表１及び表２の結果から、以下のことが理解される。まず、条件１及び条件２のエピタキシャルウェーハで観察された表１の転位欠陥は、表２に示すように不純物濃度を調整することで観察されなくなったことから、ミスフィット転位欠陥であると判定できる。また、条件３及び条件４のエピタキシャルウェーハで観察された表１の転位欠陥は、表２に示すように不純物濃度を調整しても観察されたことから、スリップ転位欠陥であると判定できる。 From the results in Tables 1 and 2, the following can be understood. First, the dislocation defects in Table 1 observed on the epitaxial wafers under Conditions 1 and 2 are no longer observed by adjusting the impurity concentration as shown in Table 2, and thus it can be determined that they are misfit dislocation defects. .. Further, since the dislocation defects in Table 1 observed in the epitaxial wafers under conditions 3 and 4 were observed even when the impurity concentration was adjusted as shown in Table 2, it can be determined that they are slip dislocation defects.

そして、表１及び表２の残留応力に示されるように、スリップ転位欠陥であるとされる条件３及び条件４のエピタキシャルウェーハの残留応力は、ミスフィット転位欠陥であるとされる条件１及び条件２のエピタキシャルウェーハの残留応力に対して有意に大きいことが理解できる。したがって、図１のステップＳ４にて、求められた残留応力が所定の閾値Ｓ０以上の場合は、応力が原因で発生するスリップ転位欠陥であると判定し（ステップＳ６）、残留応力が所定の閾値Ｓ０未満である場合は、応力とは無関係の結晶格子定数が原因で発生するミスフィット転位欠陥であると判定する（ステップＳ７）ことは適切である。 Then, as shown in the residual stresses in Tables 1 and 2, the residual stresses of the epitaxial wafers of the conditions 3 and 4 which are considered to be slip dislocation defects are the conditions 1 and conditions which are considered to be misfit dislocation defects. It can be understood that it is significantly larger than the residual stress of the epitaxial wafer of 2. Therefore, in step S4 of FIG. 1, when the obtained residual stress is equal to or higher than the predetermined threshold value S 0 , it is determined that the slip dislocation defect is caused by the stress (step S6), and the residual stress is predetermined. If it is less than the threshold S 0 , it is appropriate to determine that it is a misfit dislocation defect caused by a crystal lattice constant unrelated to stress (step S7).

１…表面検査装置
１１…可動テーブル
１２…第１レーザー発振器
１３…第２レーザー発振器
１４…集光器
１５…第１光電子増倍管
１６…第２光電子増倍管
１６ａ…レンズ
１６ｂ…ミラー
２…ウェーハストレス測定装置
２１…赤外レーザー発振器
２２…レンズ
２３…偏光子
２４…対物レンズ
２５…偏光分離素子
２６，２７…フォトダイオード
２８…処理部
ＷＦ…エピタキシャルウェーハ
ＤＦ…転位欠陥 1 ... Surface inspection device 11 ... Movable table 12 ... 1st laser oscillator 13 ... 2nd laser oscillator 14 ... Condenser 15 ... 1st photoelectron multiplying tube 16 ... 2nd photoelectron multiplying tube 16a ... Lens 16b ... Mirror 2 ... Wafer stress measuring device 21 ... Infrared laser oscillator 22 ... Lens 23 ... Polarizer 24 ... Objective lens 25 ... Polarization separation element 26, 27 ... Photo diode 28 ... Processing unit WF ... Epitential wafer DF ... Dislocation defect

Claims (2)

エピタキシャルウェーハに、スリップ転位欠陥及びミスフィット転位欠陥を含む転位欠陥がある場合に、ウェーハストレス測定により前記エピタキシャルウェーハの残留応力を求め、
前記残留応力が所定値以上の場合は、前記スリップ転位欠陥であると判定し、前記残留応力が前記所定値未満である場合は、前記ミスフィット転位欠陥であると判定するエピタキシャルウェーハの検査方法。 When the epitaxial wafer has dislocation defects including slip dislocation defects and misfit dislocation defects, the residual stress of the epitaxial wafer is obtained by wafer stress measurement.
An inspection method for an epitaxial wafer in which it is determined that the residual stress is a slip dislocation defect when the residual stress is equal to or more than a predetermined value, and it is determined to be a misfit dislocation defect when the residual stress is less than the predetermined value. 前記エピタキシャルウェーハの検査面に検査光を照射し、その散乱光に基づいて、スリップ転位欠陥及びミスフィット転位欠陥を含む転位欠陥の有無を判定する請求項１に記載のエピタキシャルウェーハの検査方法。 The method for inspecting an epitaxial wafer according to claim 1, wherein the inspection surface of the epitaxial wafer is irradiated with inspection light, and the presence or absence of dislocation defects including slip dislocation defects and misfit dislocation defects is determined based on the scattered light.
JP2020205733A 2020-12-11 2020-12-11 Method for inspecting epitaxial wafer for defect Pending JP2022092809A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2020205733A JP2022092809A (en) 2020-12-11 2020-12-11 Method for inspecting epitaxial wafer for defect
CN202111507360.7A CN114624251A (en) 2020-12-11 2021-12-10 Method for inspecting defect of epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020205733A JP2022092809A (en) 2020-12-11 2020-12-11 Method for inspecting epitaxial wafer for defect

Publications (1)

Publication Number Publication Date
JP2022092809A true JP2022092809A (en) 2022-06-23

Family

ID=81897649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020205733A Pending JP2022092809A (en) 2020-12-11 2020-12-11 Method for inspecting epitaxial wafer for defect

Country Status (2)

Country Link
JP (1) JP2022092809A (en)
CN (1) CN114624251A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214491A (en) * 2006-02-13 2007-08-23 Fujitsu Ltd Method and apparatus for detecting defect of semiconductor substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214491A (en) * 2006-02-13 2007-08-23 Fujitsu Ltd Method and apparatus for detecting defect of semiconductor substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
材料, vol. 第51巻 第9号, JPN7023003989, 15 September 2002 (2002-09-15), pages 966 - 970, ISSN: 0005179673 *

Also Published As

Publication number Publication date
CN114624251A (en) 2022-06-14

Similar Documents

Publication Publication Date Title
US6825487B2 (en) Method for isolation of wafer support-related crystal defects
TWI625806B (en) Metrology optimized inspection
US20200072762A1 (en) Method of inspecting back surface of epitaxial wafer, epitaxial wafer back surface inspection apparatus, method of managing lift pin of epitaxial growth apparatus, and method of producing epitaxial wafer
KR102385259B1 (en) Silicon Wafer Evaluation Method
WO2017078127A1 (en) Method comprising evaluating substrate by using polarized parallel light
JP6673122B2 (en) Silicon wafer evaluation method, silicon wafer manufacturing process evaluation method, and silicon wafer manufacturing method
TW462100B (en) Wafer surface inspection method
JP2022092809A (en) Method for inspecting epitaxial wafer for defect
EP2261644B1 (en) Method for judging whether a semiconductor wafer is a non-defective wafer by using a laser scattering method
JPH09167789A (en) Evaluation method for semiconductor device
JP7143828B2 (en) Slip detection method for silicon single crystal wafer
JP6634962B2 (en) Method for evaluating epitaxial layer of silicon epitaxial wafer and method for manufacturing silicon epitaxial wafer
TW201421016A (en) Semiconductor inspection device, and inspection method using charged particle beam
JP6809422B2 (en) Evaluation method for semiconductor wafers
JP2006040961A (en) Inspecting method, manufacturing method and managing method of semiconductor wafer
JP2017120202A (en) Defect inspection method, and defect inspection device
JP6593235B2 (en) Epitaxial wafer evaluation method and manufacturing method
JP2004193529A (en) Wafer evaluation method and apparatus
WO2021246101A1 (en) Evaluation method, evaluation system, and manufacturing method for silicon wafer
JP3338118B2 (en) Method for manufacturing semiconductor device
JP7363423B2 (en) Method for manufacturing silicon carbide single crystal
JP6520782B2 (en) Evaluation method and manufacturing method of epitaxial wafer
CN117368220A (en) Nondestructive testing method for stress defect of monocrystalline silicon
JP2007278918A (en) Method of inspecting optical substrate wafer
Dennis et al. Detection of a new surface killer defect on starting Si material using Nomarski principle of differential interference contrast

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20221215

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20230929

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20231024

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231201

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20240220