JP2021057531A - Display component and display device - Google Patents

Display component and display device Download PDF

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JP2021057531A
JP2021057531A JP2019181632A JP2019181632A JP2021057531A JP 2021057531 A JP2021057531 A JP 2021057531A JP 2019181632 A JP2019181632 A JP 2019181632A JP 2019181632 A JP2019181632 A JP 2019181632A JP 2021057531 A JP2021057531 A JP 2021057531A
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gate
source
output terminal
display
wiring
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守 石▲崎▼
Mamoru Ishizaki
守 石▲崎▼
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Toppan Inc
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Toppan Printing Co Ltd
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Priority to TW109133787A priority patent/TW202125638A/en
Priority to PCT/JP2020/036812 priority patent/WO2021065870A1/en
Publication of JP2021057531A publication Critical patent/JP2021057531A/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675—Constructional details
    • G02F1/1676—Electrodes
    • G02F1/16766—Electrodes for active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/37—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being movable elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Molecular Biology (AREA)
  • Computer Hardware Design (AREA)
  • Electrochemistry (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)

Abstract

To provide a display component and a display device that consume less power in rewriting.SOLUTION: A display component includes a rear plate, a display medium layer, and an opposite substrate that are stacked in order. The rear plate includes a first insulating substrate, a plurality of gate wires provided on the first insulating substrate and extending in a first direction, a plurality of source wires intersecting with the gate wire, a thin film transistor including a gate electrode connected to the gate wire, a source electrode connected to the source wire, and a drain electrode, and a pixel electrode connected to the drain electrode, electrically connected to the display medium layer, and provided on the first insulating substrate in matrix along the first direction and the second direction. The display medium layer includes electrophoretic particles. The opposite substrate includes a second insulating substrate, and a transparent electrode electrically connected to the display medium layer. In a plan view, at least a part of the source wire is included in a gap between the pixel electrodes arranged in the first direction.SELECTED DRAWING: Figure 2

Description

本発明は、表示部品及び表示装置に関する。 The present invention relates to display components and display devices.

半導体自体を基板としたトランジスタや集積回路技術を基礎として、ガラス基板上にアモルファスシリコン（ａ−Ｓｉ）やポリシリコン（ｐｏｌｙ−Ｓｉ）の薄膜トランジスタ（Ｔｈｉｎ Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ：ＴＦＴ）アレイが製造され、液晶ディスプレイなどに応用されている。ＴＦＴはスイッチの役割を果たしており、行配線（ゲート配線）に与えられた選択電圧によってＴＦＴをオンにした時に、列配線（ソース配線）に与えられた信号電圧をドレイン電極に接続された画素電極に書き込む。書き込まれた電圧は、ドレイン電極または画素電極と、キャパシタ電極との間に設けられた蓄積キャパシタに保持される。（ＴＦＴアレイの場合、ソースとドレインの働きは書き込む電圧の極性によって変わるため、動作で名称を決められない。そこで、便宜的に一方をソース、他方をドレインと、呼び方を統一しておく。本明細書では、配線に接続されている方をソース、画素電極に接続されている方をドレインと呼ぶ。） Amorphous silicon (a-Si) and polysilicon (poly-Si) thin film transistor (TFT) arrays are manufactured on a glass substrate based on transistors and integrated circuit technology using the semiconductor itself as a substrate, and a liquid crystal display. It is applied to such as. The TFT plays the role of a switch, and when the TFT is turned on by the selective voltage given to the row wiring (gate wiring), the signal voltage given to the column wiring (source wiring) is connected to the drain electrode. Write to. The written voltage is held in a storage capacitor provided between the drain electrode or the pixel electrode and the capacitor electrode. (In the case of a TFT array, the functions of the source and drain change depending on the polarity of the voltage to be written, so the name cannot be determined by the operation. Therefore, for convenience, one is called the source and the other is called the drain. In the present specification, the one connected to the wiring is referred to as a source, and the one connected to the pixel electrode is referred to as a drain.)

ＴＦＴアレイには、ゲート電位をオンからオフに切替える際に画素電位が変化するゲートフィードスルーという現象がある。画素電位は、ゲートフィードスルー電圧Ｖｇｆ＝ΔＶｇ・Ｃｇｄ／（Ｃｇｄ＋Ｃｓ＋Ｃｐ）だけ変化する。ΔＶｇはゲート電位変化量、Ｃｇｄはゲート・ドレイン間容量、Ｃｓは蓄積容量（画素電極・キャパシタ間容量）、Ｃｐは表示媒体の容量である。Ｃｐが大きければ蓄積容量Ｃｓを省略できる。Ｃｐが小さければＣｓが必要になり、ＣｐがＣｓに比べてずっと小さければＣｐを無視できる。従来は、ゲートフィードスルー電圧を小さくする目的で、Ｃｇｄを小さくする工夫がなされていた（特許文献１）。 The TFT array has a phenomenon called gate feedthrough in which the pixel potential changes when the gate potential is switched from on to off. The pixel potential changes by the gate feedthrough voltage Vgf = ΔVg · Cgd / (Cgd + Cs + Cp). ΔVg is the amount of change in gate potential, Cgd is the capacity between gate and drain, Cs is the storage capacity (capacity between pixel electrode and capacitor), and Cp is the capacity of the display medium. If Cp is large, the storage capacity Cs can be omitted. If Cp is small, Cs is required, and if Cp is much smaller than Cs, Cp can be ignored. Conventionally, in order to reduce the gate feedthrough voltage, a device for reducing Cgd has been made (Patent Document 1).

近年、ＴＦＴアレイと電気泳動媒体を組合せた電子ペーパー表示部品及び表示装置が開発され、液晶よりも低消費電力な表示部品及び表示装置として期待されている。一般的な液晶表示部品及び表示装置は駆動を行っている間しか表示できず、表示を保つためには駆動を続ける必要があるのに対し、電気泳動タイプの電子ペーパーは駆動終了後にも表示を保つので、駆動を続ける必要がない。 In recent years, electronic paper display components and display devices that combine a TFT array and an electrophoresis medium have been developed, and are expected as display components and display devices with lower power consumption than liquid crystals. While general liquid crystal display parts and display devices can display only while driving, and it is necessary to continue driving to maintain the display, electrophoresis-type electronic paper displays the display even after the driving is completed. It keeps, so you don't have to keep driving.

さらに、電子ペーパーを個体認識技術であるＲＦＩＤと組合せて、コンテナの表示部とする技術が開示されている（特許文献２）。電子ペーパーとＲＦＩＤとが組み合わされた表示部は、ＲＦＩＤに保存された内容物データを表示することで、目視でのデータの確認を可能とする。 Further, a technique of combining electronic paper with RFID, which is an individual recognition technique, to form a display unit of a container is disclosed (Patent Document 2). The display unit, which is a combination of electronic paper and RFID, enables visual confirmation of the data by displaying the content data stored in the RFID.

特開２０１４−１８７０９３号公報Japanese Unexamined Patent Publication No. 2014-187093 特開２００３−２３３７８６号公報Japanese Unexamined Patent Publication No. 2003-233786

このような表示装置には、内蔵する電池の電力を使って書替を行うタイプと、ＲＦＩＤの書替を行うリーダライタの電波を電力に変換し、その電力を用いて書替を行うタイプがある。いずれのタイプにおいても、書替時の消費電力量の低減が課題である。電池を内蔵する表示装置では、消費電力量が大きいと頻繁に電池交換を行う必要がある。ＲＦ電波の電力を用いる表示装置では、消費電力量が大きいと電波が強い近距離でしか書替を行うことができない。このため、書替時の消費電力量を抑制できる、ＴＦＴアレイが求められている。 Such display devices include a type that rewrites using the power of the built-in battery and a type that converts the radio wave of the reader / writer that rewrites RFID into electric power and rewrites using that electric power. is there. In any type, reducing the power consumption at the time of rewriting is an issue. In a display device with a built-in battery, it is necessary to replace the battery frequently when the power consumption is large. In a display device that uses the power of RF radio waves, if the power consumption is large, rewriting can be performed only at a short distance where the radio waves are strong. Therefore, there is a demand for a TFT array that can suppress the power consumption at the time of rewriting.

上記事情を踏まえ、本発明は、書替時の消費電力量が小さい表示部品及び表示装置を提供することを課題とする。 Based on the above circumstances, it is an object of the present invention to provide a display component and a display device having a small power consumption at the time of rewriting.

本発明の表示部品は、背面板と、前記背面板上に積層される表示媒体層と、前記表示媒体層上に積層される対向基板と、が順次積層され、前記背面板は、第１の絶縁基板と、第１の方向に延びて前記第１の絶縁基板上に設けられる複数のゲート配線と、前記第１の方向に交差する第２の方向に延びて前記第１の絶縁基板上に設けられる複数のソース配線と、前記ゲート配線に接続されるゲート電極と、前記ソース配線に接続されるソース電極と、ドレイン電極と、を有し前記第１の絶縁基板上に複数設けられる薄膜トランジスタと、各々の前記薄膜トランジスタに対応して設けられ、前記ドレイン電極と接続され、前記表示媒体層に電気的に接続し、前記ソース配線より前記表示媒体層側に、前記第１の方向及び前記第２の方向に沿ってマトリクス状に前記第１の絶縁基板上に設けられる画素電極と、を有し、前記表示媒体層は、電気泳動粒子を有し、前記対向基板は、第２の絶縁基板と、前記表示媒体層と電気的に接続する透明電極と、を有し、平面視で、前記第１の方向に並ぶ前記画素電極の間の隙間に前記ソース配線の少なくとも一部が含まれるように配置される。 In the display component of the present invention, a back plate, a display medium layer laminated on the back plate, and an opposing substrate laminated on the display medium layer are sequentially laminated, and the back plate is the first. An insulating substrate, a plurality of gate wiring extending in a first direction and provided on the first insulating substrate, and extending in a second direction intersecting the first direction on the first insulating substrate. A plurality of thin film transistors provided on the first insulating substrate having a plurality of source wirings provided, a gate electrode connected to the gate wiring, a source electrode connected to the source wiring, and a drain electrode. , Corresponding to each of the thin film transistors, connected to the drain electrode, electrically connected to the display medium layer, and from the source wiring to the display medium layer side, the first direction and the second direction. The display medium layer has the electrophoresis particles, and the opposing substrate has the second insulating substrate and the pixel electrodes provided on the first insulating substrate in a matrix along the direction of the above. A transparent electrode that is electrically connected to the display medium layer, so that at least a part of the source wiring is included in the gap between the pixel electrodes arranged in the first direction in a plan view. Be placed.

本発明の表示装置は、前記表示部品と、前記ゲート配線及び前記ソース配線に接続されるドライバＩＣと、を備え、前記ゲート配線は、前記第１の絶縁基板の第１の縁から第１の方向に延びる第１ゲート配線群と、前記第１の絶縁基板を挟んで前記第１の縁と向かい合う第２の縁から第１の方向に延びる第２ゲート配線群と、が前記第２の方向に並んで交互に配置され、前記ドライバＩＣは、前記第１ゲート配線群と接続される第１ゲート出力端子と、前記ソース配線と接続されるソース出力端子と、前記第２ゲート配線群と接続される第２ゲート出力端子と、を備え、前記第１ゲート出力端子、前記ソース出力端子、及び前記第２ゲート出力端子の順に並べて設けられる。 The display device of the present invention includes the display component, the gate wiring, and a driver IC connected to the source wiring, and the gate wiring is first from the first edge of the first insulating substrate. The first gate wiring group extending in the direction and the second gate wiring group extending in the first direction from the second edge facing the first edge across the first insulating substrate are in the second direction. The driver ICs are connected to the first gate output terminal connected to the first gate wiring group, the source output terminal connected to the source wiring, and the second gate wiring group. The second gate output terminal is provided, and the first gate output terminal, the source output terminal, and the second gate output terminal are provided side by side in this order.

本発明によれば、書替時の消費電力量が小さい表示部品及び表示装置を提供できる。 According to the present invention, it is possible to provide a display component and a display device having a small power consumption at the time of rewriting.

本発明の第一実施形態に係る表示部品の製造途中の平面図及び断面図である。It is a top view and a sectional view in the process of manufacturing the display component which concerns on 1st Embodiment of this invention. 同平面図及び断面図である。It is the same plan view and sectional view. 同完成品の平面図及び断面図である。It is a plan view and a sectional view of the finished product. 同表示部品のソース配線の寄生容量に起因する消費電力量を説明する図である。It is a figure explaining the power consumption caused by the parasitic capacitance of the source wiring of the display component. 同表示部品のゲート配線の寄生容量に起因する消費電力量を説明する図である。It is a figure explaining the power consumption caused by the parasitic capacitance of the gate wiring of the display component. 同表示部品の蓄積容量に起因する消費電力量を説明する図である。It is a figure explaining the power consumption due to the storage capacity of the display component. 同表示部品の電気的構造を説明する図である。It is a figure explaining the electrical structure of the display component. 同表示部品の仮想画素の電位変化を説明する図である。It is a figure explaining the potential change of the virtual pixel of the display component. 同表示部品の寸法を示す断面図である。It is sectional drawing which shows the dimension of the display component. 電極幅と電気力線の関係を説明する図である。It is a figure explaining the relationship between an electrode width and an electric line of force. 本発明の第二実施形態に係る表示部品の製造途中の平面図及び断面図である。It is a top view and a sectional view in the process of manufacturing the display component which concerns on 2nd Embodiment of this invention. 同平面図及び断面図である。It is the same plan view and sectional view. 同完成品の平面図及び断面図である。It is a plan view and a sectional view of the finished product. 同表示部品の寸法を示す断面図である。It is sectional drawing which shows the dimension of the display component. 本発明の第三実施形態に係る表示装置の概略を示す平面図である。It is a top view which shows the outline of the display device which concerns on 3rd Embodiment of this invention. 同変形例の概略を示す平面図である。It is a top view which shows the outline of the modification. 同変形例の概略を示す平面図である。It is a top view which shows the outline of the modification. 従来の表示部品の製造途中の平面図及び断面図である。It is a top view and a cross-sectional view in the process of manufacturing a conventional display component. 同平面図及び断面図である。It is the same plan view and sectional view. 同完成品の平面図及び断面図である。It is a plan view and a sectional view of the finished product.

本発明の第一実施形態に係る表示部品について、図１から図３を参照しながら説明する。図１から図３は本実施形態に係る表示部品１００の一部であり、表示部品１００は図３に記載された構成をマトリクス状に複数並べて接続した構成を有する。図１及び図２は表示部品１００の特徴をわかりやすく示すための製造途中の図であり、図１は基板上に薄膜トランジスタ等を形成した状態であって、図２はさらに画素電極等を形成した状態である。図３は完成図であり、表示媒体層等が積層された表示部品１００の断面図を示している。 The display component according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 3. 1 to 3 are a part of the display component 100 according to the present embodiment, and the display component 100 has a configuration in which a plurality of the configurations shown in FIG. 3 are arranged side by side in a matrix and connected. 1 and 2 are views in the middle of manufacturing for showing the features of the display component 100 in an easy-to-understand manner. FIG. 1 shows a state in which a thin film transistor or the like is formed on a substrate, and FIG. 2 shows a state in which a pixel electrode or the like is further formed. It is in a state. FIG. 3 is a completed view and shows a cross-sectional view of the display component 100 on which the display medium layer and the like are laminated.

図３に示すように、表示部品１００は、背面板１１０と、表示媒体層１２０と、対向基板１３０と、を有する。対向基板１３０、表示媒体層１２０、及び背面板１１０はこの順に積層されている。 As shown in FIG. 3, the display component 100 includes a back plate 110, a display medium layer 120, and an opposing substrate 130. The facing substrate 130, the display medium layer 120, and the back plate 110 are laminated in this order.

図１に示すように、背面板１１０は、絶縁基板１（第１の絶縁基板）上に、横方向（第１の方向）Ｄ１に延伸する複数のゲート配線２Ｗと、横方向Ｄ１に交差する縦方向（第２の方向）Ｄ２に延伸する複数のソース配線４Ｗ及びキャパシタ配線９Ｗと、を有する。本実施形態では、横方向Ｄ１と縦方向Ｄ２とは直交している。 As shown in FIG. 1, the back plate 110 intersects a plurality of gate wirings 2W extending in the lateral direction (first direction) D1 on the insulating substrate 1 (first insulating substrate) in the lateral direction D1. It has a plurality of source wirings 4W and capacitor wirings 9W extending in the vertical direction (second direction) D2. In this embodiment, the horizontal direction D1 and the vertical direction D2 are orthogonal to each other.

また、図２に示すように、背面板１１０は、ゲート配線２Ｗとソース配線４Ｗとが交差する位置に対応して設けられた複数の画素Ｐｘを有する。画素Ｐｘは、ＴＦＴ（薄膜トランジスタ）２０、キャパシタ電極９及び画素電極１０を有する。ＴＦＴ２０はゲート電極２、ソース電極４、ドレイン電極５、半導体パターン６及びドレイン副電極７を有する。 Further, as shown in FIG. 2, the back plate 110 has a plurality of pixels Px provided corresponding to the positions where the gate wiring 2W and the source wiring 4W intersect. The pixel Px has a TFT (thin film transistor) 20, a capacitor electrode 9, and a pixel electrode 10. The TFT 20 has a gate electrode 2, a source electrode 4, a drain electrode 5, a semiconductor pattern 6, and a drain sub-electrode 7.

ゲート電極２、ゲート配線２Ｗ及びドレイン副電極７は絶縁基板１上に積層され、これらの上にゲート絶縁膜３が積層される。 The gate electrode 2, the gate wiring 2W, and the drain sub-electrode 7 are laminated on the insulating substrate 1, and the gate insulating film 3 is laminated on these.

ソース電極４、ソース配線４Ｗ、ドレイン電極５、半導体パターン６、キャパシタ電極９及びキャパシタ配線９Ｗはゲート絶縁膜３上に積層され、これらの上に層間絶縁膜８が積層される。 The source electrode 4, the source wiring 4W, the drain electrode 5, the semiconductor pattern 6, the capacitor electrode 9 and the capacitor wiring 9W are laminated on the gate insulating film 3, and the interlayer insulating film 8 is laminated on these.

画素電極１０は層間絶縁膜８上に積層される。画素電極１０は表示媒体層１２０側を向いて配置される。 The pixel electrode 10 is laminated on the interlayer insulating film 8. The pixel electrode 10 is arranged so as to face the display medium layer 120 side.

ゲート電極２はゲート配線２Ｗに接続される。ソース電極４はソース配線４Ｗに接続される。ドレイン電極５はドレイン接続配線５Ｃ及びドレインビアホール接続５Ｖを介してドレイン副電極７に接続されている。画素電極１０は画素電極ビアホール接続１０Ｖを介してドレイン電極５に接続される。キャパシタ電極９はキャパシタ配線９Ｗに接続される。 The gate electrode 2 is connected to the gate wiring 2W. The source electrode 4 is connected to the source wiring 4W. The drain electrode 5 is connected to the drain sub-electrode 7 via the drain connection wiring 5C and the drain via hole connection 5V. The pixel electrode 10 is connected to the drain electrode 5 via a pixel electrode via hole connection 10V. The capacitor electrode 9 is connected to the capacitor wiring 9W.

ゲート電極２とソース電極４とは、平面視で重なる部分を有する。また、ゲート配線２Ｗとソース配線４Ｗとは、平面視で重なる部分を有する。ゲート配線２Ｗとキャパシタ配線９Ｗとは、平面視で重なる部分を有する。 The gate electrode 2 and the source electrode 4 have a portion that overlaps in a plan view. Further, the gate wiring 2W and the source wiring 4W have a portion that overlaps in a plan view. The gate wiring 2W and the capacitor wiring 9W have a portion that overlaps in a plan view.

キャパシタ電極９は、層間絶縁膜８を介して画素電極１０と重なり、ゲート絶縁膜３を介してドレイン副電極７と重なる。 The capacitor electrode 9 overlaps with the pixel electrode 10 via the interlayer insulating film 8 and overlaps with the drain sub-electrode 7 via the gate insulating film 3.

表示部品１００は、図２に示すように、平面視で、横方向Ｄ１に並ぶ画素電極１０の間の隙間に、ソース配線４Ｗの一部が含まれるように配置される。 As shown in FIG. 2, the display component 100 is arranged so that a part of the source wiring 4W is included in the gap between the pixel electrodes 10 arranged in the lateral direction D1 in a plan view.

この構造では、ソース配線４Ｗと画素電極１０とが重なる部分を減少させることにより、ソース配線４Ｗと画素電極１０との重なりによるソース・画素電極間容量Ｃｓｐを小さくすることができる。 In this structure, by reducing the portion where the source wiring 4W and the pixel electrode 10 overlap, the capacitance Csp between the source and the pixel electrode due to the overlap between the source wiring 4W and the pixel electrode 10 can be reduced.

表示媒体層１２０は、電気泳動粒子を用いた公知の構成であり、例えば白色粒子と、黒色粒子と、液体とを内包したカプセル又はセルが表示面の面内に複数並べられ、粒子が色毎に正負に帯電されている。表示媒体層１２０は、バインダや接着剤を含んでもよい。 The display medium layer 120 has a known configuration using electrophoretic particles. For example, a plurality of capsules or cells containing white particles, black particles, and a liquid are arranged in the plane of the display surface, and the particles are arranged for each color. Is positively and negatively charged. The display medium layer 120 may contain a binder or an adhesive.

対向基板１３０は、絶縁基板１１（第２の絶縁基板）と、表示媒体層１２０と電気的に接続する透明な透明電極１２と、を有する。 The facing substrate 130 has an insulating substrate 11 (second insulating substrate) and a transparent transparent electrode 12 that is electrically connected to the display medium layer 120.

表示部品１００による表示の原理は公知である。書き込み対象の画素Ｐｘに対応するＴＦＴ２０に対して、ゲート配線２Ｗ、ソース配線４Ｗを介してゲート電極２、ソース電極４に電位を生じさせてドレイン電極５を介して画素電極１０やドレイン副電極７に電荷を蓄積する。 The principle of display by the display component 100 is known. With respect to the TFT 20 corresponding to the pixel Px to be written, a potential is generated in the gate electrode 2 and the source electrode 4 via the gate wiring 2W and the source wiring 4W, and the pixel electrode 10 and the drain sub-electrode 7 are generated via the drain electrode 5. Accumulates charge in.

ドレイン副電極７に電荷が蓄積されることにより、ゲート配線２Ｗ、ソース配線４Ｗの電位を除いても、ドレイン副電極７・キャパシタ電極９間がコンデンサとなり画素電極１０の電荷が維持される。 Since the electric charge is accumulated in the drain sub-electrode 7, the charge between the drain sub-electrode 7 and the capacitor electrode 9 becomes a capacitor and the electric charge of the pixel electrode 10 is maintained even if the potentials of the gate wiring 2W and the source wiring 4W are removed.

画素電極１０と対向基板１３０の透明電極１２との間に電位差を生じさせ、表示媒体層１２０の中の白色粒子と黒色粒子とのどちらか一方を透明電極１２側に引きよせ、他方を画素電極１０側に引きよせて、透明電極１２側に引きよせた粒子の色を表示面に提示することにより、表示が行われる。 A potential difference is generated between the pixel electrode 10 and the transparent electrode 12 of the opposing substrate 130, and either one of the white particles and the black particles in the display medium layer 120 is attracted to the transparent electrode 12 side, and the other is the pixel electrode. Display is performed by presenting the color of the particles attracted to the 10 side and attracted to the transparent electrode 12 side on the display surface.

次に表示部品１００の使用時の消費電力について図４から図６を参照しながら説明する。図４は、１本のソース配線４Ｗで１フレーム中に消費される電力量の計算過程を示している。図５は、１本のゲート配線２Ｗで１フレーム中に消費される電力量の計算過程を示している。図６は、一つのＴＦＴ２０で１フレーム中に消費される電力量の計算過程を示している。 Next, the power consumption when the display component 100 is used will be described with reference to FIGS. 4 to 6. FIG. 4 shows the calculation process of the amount of electric power consumed in one frame by one source wiring 4W. FIG. 5 shows a calculation process of the amount of electric power consumed in one frame by one gate wiring 2W. FIG. 6 shows a calculation process of the amount of electric power consumed in one frame by one TFT 20.

まず、平面視でゲート電極２とソース電極４とが重なる部分の面積Ｓｇｓ、ソース配線４Ｗとゲート配線２Ｗとが重なる部分の面積Ｓｇｓｌ、ゲート絶縁膜３の誘電率εｇｉ及びゲート絶縁膜３の膜厚Ｄｇｉからゲート・ソース間容量Ｃｇｓ＝εｇｉ・（Ｓｇｓ＋Ｓｇｓｌ）／Ｄｇｉとなる。 First, in plan view, the area Sgs of the portion where the gate electrode 2 and the source electrode 4 overlap, the area Sgsl of the portion where the source wiring 4W and the gate wiring 2W overlap, the dielectric constant εgi of the gate insulating film 3 and the film of the gate insulating film 3 From the thickness Dgi, the gate-source capacitance Cgs = εgi · (Sgs + Sgsl) / Dgi.

本実施形態では平面視でソース電極４又はソース配線４Ｗとキャパシタ電極９又はキャパシタ配線９Ｗとが重なる部分がなく、ソース・キャパシタ間容量Ｃｓｃはほぼ０Ｆである。 In the present embodiment, there is no portion where the source electrode 4 or the source wiring 4W and the capacitor electrode 9 or the capacitor wiring 9W overlap in a plan view, and the capacitance Csc between the source and the capacitors is approximately 0F.

平面視でゲート配線２Ｗとキャパシタ配線９Ｗとが重なる部分の面積Ｓｇｃｌ、層間絶縁膜８の誘電率εｉｌ及び層間絶縁膜８の膜厚Ｄｉｌからゲート・キャパシタ間容量Ｃｇｃ＝εｉｌ・Ｓｇｃｌ／Ｄｉｌとなる。 From the area Sgcl of the portion where the gate wiring 2W and the capacitor wiring 9W overlap in a plan view, the dielectric constant εil of the interlayer insulating film 8 and the film thickness Dil of the interlayer insulating film 8, the gate-capacitor capacitance Cgt = εil · Sgcl / Dil. ..

平面視でゲート電極２とドレイン電極５とが重なる部分の面積Ｓｇｄ、ゲート絶縁膜３の誘電率εｇｉ及びゲート絶縁膜３の膜厚Ｄｇｉからゲート・ドレイン間容量Ｃｇｄ＝εｇｉ・Ｓｇｄ／Ｄｇｉとなる。 From the area Sgd of the portion where the gate electrode 2 and the drain electrode 5 overlap in a plan view, the dielectric constant εgi of the gate insulating film 3 and the film thickness Dgi of the gate insulating film 3, the gate-drain capacitance Cgd = εgi · Sgd / Dgi. ..

平面視でゲート電極２又はゲート配線２Ｗと画素電極１０とが重なる部分の面積Ｓｇｐ、ゲート絶縁膜３の誘電率εｇｉ及びゲート絶縁膜３の膜厚Ｄｇｉ、層間絶縁膜８の誘電率εｉｌ及び層間絶縁膜８の膜厚Ｄｉｌからゲート・画素間容量Ｃｇｐ＝εｇｉ・εｉｌ・Ｓｇｐ／（εｉｌ・Ｄｇｉ＋εｇｉ・Ｄｉｌ）となる。ただし、ドレイン電極５と画素電極１０は接続されているので、ＣｇｐはＣｇｄと並列関係にある。そこで、ＣｇｄにＣｇｐを加算したものを、改めてＣｇｄとする。 Area Sgp of the portion where the gate electrode 2 or the gate wiring 2W and the pixel electrode 10 overlap in a plan view, the dielectric constant εgi of the gate insulating film 3 and the thickness Dgi of the gate insulating film 3, the dielectric constant εil of the interlayer insulating film 8 and the interlayer From the film thickness of the insulating film 8 Di, the gate / interpixel capacitance Cgp = εgi / εil / Sgp / (εil / Dgi + εgi / Dil). However, since the drain electrode 5 and the pixel electrode 10 are connected, Cgp is in a parallel relationship with Cgd. Therefore, the sum of Cgd and Cgp is referred to as Cgd again.

平面視でソース電極４と画素電極１０が重なる部分の面積Ｓｓｐ、層間絶縁膜８の誘電率εｉｌ及び層間絶縁膜８の膜厚Ｄｉｌからソース・画素電極間容量Ｃｓｐ＝εｉｌ・Ｓｓｐ／Ｄｉｌとなる。 From the area Ssp of the portion where the source electrode 4 and the pixel electrode 10 overlap in a plan view, the dielectric constant εil of the interlayer insulating film 8 and the film thickness Dil of the interlayer insulating film 8, the capacitance between the source and the pixel electrodes Csp = εil · Ssp / Dil. ..

ソース配線４ＷがＭ本、ゲート配線２ＷがＮ本とする。ソース配線４Ｗに接続されている容量は、Ｃｇｓ、Ｃｓｃ、Ｃｓｐ／／Ｃｓである。ここで記号／／は、容量の直列回路を意味し、例えばＣｓｐ／／Ｃｓ＝１／（１／Ｃｓｐ＋１／Ｃｓ）である。ただしＣｓｐ＜＜Ｃｓであるから、Ｃｓｐ／／Ｃｓ≒Ｃｓｐである。１本のソース配線４Ｗに接続された画素ＰｘはＮ個であるから、静電容量はＣ＝Ｎ（Ｃｇｓ＋Ｃｓｃ＋Ｃｓｐ／／Ｃｓ）である。 The source wiring 4W is M, and the gate wiring 2W is N. The capacitances connected to the source wiring 4W are Cgs, Csc, and Csp // Cs. Here, the symbol // means a series circuit of capacitance, for example, Csp // Cs = 1 / (1 / Csp + 1 / Cs). However, since Csp << Cs, Csp // Cs≈Csp. Since the number of pixels Px connected to one source wiring 4W is N, the capacitance is C = N (Cgs + Csc + Csp // Cs).

ソース配線４Ｗは、各画素Ｐｘのデータに合わせて電圧を変更するので、最も多く充放電されるのは１行毎に逆極性を書込む場合である。１本のソース配線４Ｗで１フレーム中に消費される電力量は図４のように計算できる。ただし、白書込と黒書込の電圧が±Ｖｓ、ソース配線４Ｗの抵抗（厳密にはソース配線４Ｗの抵抗と直列抵抗（図示しないソースドライバの出力抵抗等）の和）がＲである。図４で、横軸は時間ｔである。ソースドライバの正電源の電圧がＶｐ、電流がＩｐ、負電源の電圧がＶｎ、電流がＩｎ、ＧＮＤ線の電圧がＶｏ＝０、電流がＩＯである。正電源の消費電力がＰｐ、負電源の消費電力がＰｎ、ＧＮＤ線の消費電力Ｐｏ＝０である。式を簡単にするために各充電波形の積分範囲をｔ＝０〜∞として表記しているが、時定数ＣＲより充分大きければよく、例えばｔ＝０〜３ＣＲでも電力量の９５％をカバーして近似的には同等である。１本のソース配線４Ｗで１フレームに消費される電力量は、（２Ｎ−１）Ｃ（Ｖｓ）＾２である。よって、Ｍ本のソース配線４Ｗで１フレーム中に消費される電力量は、Ｍ×（２Ｎ−１）×Ｎ（Ｃｇｓ＋Ｃｓｃ＋Ｃｓｐ／／Ｃｓ）×（Ｖｓ）＾２＝ＭＮ（２Ｎ−１）（Ｃｇｓ＋Ｃｓｃ＋Ｃｓｐ／／Ｃｓ）（Ｖｓ）＾２であり、Ｎが１より充分大きい場合には２Ｍ（Ｎ＾２）（Ｃｇｓ＋Ｃｓｃ＋Ｃｓｐ／／Ｃｓ）（Ｖｓ）＾２とみなせる。最も消費される電力量が小さいのはソース配線４Ｗの電圧を変えない場合であり、１フレーム中に消費される電力量は０Jである。 Since the source wiring 4W changes the voltage according to the data of each pixel Px, the most charged / discharged case is when the opposite polarity is written for each line. The amount of power consumed in one frame by one source wiring 4W can be calculated as shown in FIG. However, the voltage of white writing and black writing is ± Vs, and the resistance of the source wiring 4W (strictly speaking, the sum of the resistance of the source wiring 4W and the series resistance (output resistance of the source driver, etc. not shown)) is R. In FIG. 4, the horizontal axis is time t. The voltage of the positive power supply of the source driver is Vp, the current is Ip, the voltage of the negative power supply is Vn, the current is In, the voltage of the GND line is Vo = 0, and the current is IO . The power consumption of the positive power supply is Pp, the power consumption of the negative power supply is Pn, and the power consumption of the GND line is Po = 0. To simplify the equation, the integration range of each charge waveform is expressed as t = 0 to ∞, but it is sufficient if it is sufficiently larger than the time constant CR. For example, even t = 0 to 3CR covers 95% of the electric energy. Is approximately equivalent. The amount of electric power consumed in one frame by one source wiring 4W is (2N-1) C (Vs) ^ 2. Therefore, the amount of power consumed in one frame by M source wiring 4W is M × (2N-1) × N (Cgs + Csc + Csp // Cs) × (Vs) ^ 2 = MN (2N-1) (Cgs + Csc + Csp). // Cs) (Vs) ^ 2, and when N is sufficiently larger than 1, it can be regarded as 2M (N ^ 2) (Cgs + Csc + Csp // Cs) (Vs) ^ 2. The smallest amount of power consumed is when the voltage of the source wiring 4W is not changed, and the amount of power consumed in one frame is 0J.

ゲート配線２Ｗに接続されている容量はＣｇｓ、Ｃｇｃ、Ｃｇｄ／／Ｃｓである。１本のゲート配線２Ｗに接続された画素ＰｘはＭ個であるから、静電容量はＣ＝Ｍ（Ｃｇｓ＋Ｃｇｃ＋Ｃｇｄ／／Ｃｓ）である。ただしＣｇｄ＜＜Ｃｓであるから、Ｃｇｄ／／Ｃｓ≒Ｃｇｄである。１フレームでゲート電圧は、オフ→オンの１回と、オン→オフの１回の、計２回変化する。ゲート電圧変化量をΔＶｇとすると、１本のゲート配線２Ｗで１フレーム中に消費される電力量は図５のように計算できる。ただし、図５はＴＦＴ２０がｎチャネルの場合であり、ｐチャネルの場合は電圧の正負が逆になるが、消費電力量の式は同じである。ゲートの正電圧がＶｐ、負電圧がＶｎ、ゲート配線２Ｗの抵抗（厳密にはゲート配線２Ｗ抵抗と直列抵抗（ゲートドライバの出力抵抗等）の和）がＲである。図５で、横軸は時間ｔである。ゲートドライバの正電源の電圧がＶｐ、電流がＩｐ、負電源の電圧がＶｎ、電流がＩｎである。正電源の消費電力がＰｐ、負電源の消費電力がＰｎである。式を簡単にするために各充電波形の積分範囲をｔ＝０〜∞として表記しているが、時定数ＣＲより充分大きければよく、例えばｔ＝０〜３ＣＲでも電力量の９５％をカバーして近似的には同等である。１本のゲート配線２Ｗで１フレームに消費される電力量は、Ｃ（ΔＶｇ）＾２である。Ｎ本のゲート配線２Ｗで１フレーム中に消費される電力量は、Ｎ×Ｍ（Ｃｇｓ＋Ｃｇｃ＋Ｃｇｄ／／Ｃｓ）×（ΔＶｇ）＾２＝ＭＮ（Ｃｇｓ＋Ｃｇｃ＋Ｃｇｄ／／Ｃｓ）（ΔＶｇ）＾２である。 The capacitances connected to the gate wiring 2W are Cgs, Cgc, and Cgd // Cs. Since the number of pixels Px connected to one gate wiring 2W is M, the capacitance is C = M (Cgs + Cgc + Cgd // Cs). However, since Cgd << Cs, Cgd // Cs≈Cgd. In one frame, the gate voltage changes twice, once off → on and once on → off. Assuming that the amount of change in the gate voltage is ΔVg, the amount of power consumed in one frame by one gate wiring 2W can be calculated as shown in FIG. However, FIG. 5 shows a case where the TFT 20 has n channels, and in the case of p channels, the positive and negative of the voltage are opposite, but the formula of the electric energy is the same. The positive voltage of the gate is Vp, the negative voltage is Vn, and the resistance of the gate wiring 2W (strictly speaking, the sum of the gate wiring 2W resistance and the series resistance (the output resistance of the gate driver, etc.)) is R. In FIG. 5, the horizontal axis is time t. The voltage of the positive power supply of the gate driver is Vp, the current is Ip, the voltage of the negative power supply is Vn, and the current is In. The power consumption of the positive power supply is Pp, and the power consumption of the negative power supply is Pn. To simplify the equation, the integration range of each charge waveform is expressed as t = 0 to ∞, but it is sufficient if it is sufficiently larger than the time constant CR. For example, even t = 0 to 3CR covers 95% of the electric energy. Is approximately equivalent. The amount of electric power consumed in one frame by one gate wiring 2W is C (ΔVg) ^ 2. The amount of electric power consumed in one frame by N gate wirings 2W is N × M (Cgs + Cgt + Cgd // Cs) × (ΔVg) ^ 2 = MN (Cgs + Cgc + Cgd // Cs) (ΔVg) ^ 2.

ＴＦＴ２０に接続されているのはＣｓ、Ｃｐである。静電容量はＣ＝Ｃｓ＋Ｃｐである。１フレームで画素電圧は、画素Ｐｘが前回と異なる表示を行う場合に１回変化する。最も多く充電されるのは全画素Ｐｘの表示を変更する場合である。その場合、ソース配線４Ｗの電圧変化量をＶｓとすると、１フレーム中に消費される電力量は図６のように計算できる。ＴＦＴ２０の抵抗（厳密にはＴＦＴ２０の抵抗と直列抵抗（ソース配線４Ｗの抵抗等）の和）がＲである。図６で、横軸は時間ｔである。ドレイン電圧Ｖｄ＝Ｖｓを書込んだ時、電流がＩｔｆｔ、消費電力がＰｔｆｔである。式を簡単にするために充電波形の積分範囲をｔ＝０〜∞として表記しているが、時定数ＣＲより充分大きければよく、例えばｔ＝０〜３ＣＲでも電力量の９５％をカバーして近似的には同等である。１個のＴＦＴ２０で１フレームに消費される電力量は（Ｃｓ＋Ｃｐ）（Ｖｓ）＾２であり、ＭＮ個ではＭＮ（Ｃｓ＋Ｃｐ）（Ｖｓ）＾２である。Ｖｄ＝−Ｖｓの場合も同じ値である。最も消費電力量が小さいのは画素電位を変えない場合であり、１フレーム中に消費される電力量は０Jである。 Cs and Cp are connected to the TFT 20. The capacitance is C = Cs + Cp. In one frame, the pixel voltage changes once when the pixel Px displays a different display from the previous time. The most charged is when changing the display of all pixels Px. In that case, assuming that the amount of voltage change of the source wiring 4W is Vs, the amount of power consumed in one frame can be calculated as shown in FIG. The resistance of the TFT 20 (strictly speaking, the sum of the resistance of the TFT 20 and the series resistance (resistance of the source wiring 4W, etc.)) is R. In FIG. 6, the horizontal axis is time t. When the drain voltage Vd = Vs is written, the current is Itft and the power consumption is Ptft. To simplify the equation, the integration range of the charging waveform is expressed as t = 0 to ∞, but it is sufficient if it is sufficiently larger than the time constant CR. For example, even t = 0 to 3CR covers 95% of the electric energy. Approximately equivalent. The amount of electric power consumed in one frame by one TFT 20 is (Cs + Cp) (Vs) ^ 2, and that of MN is MN (Cs + Cp) (Vs) ^ 2. The same value is obtained when Vd = −Vs. The smallest power consumption is when the pixel potential is not changed, and the power consumption in one frame is 0J.

以上のように消費される電力量の係数は、ソース配線４Ｗで２ＭＮ＾２、ゲート配線２ＷでＭＮ、画素ＰｘでＭＮである。通常、ＭやＮは数十〜数百である。また一般的に、Ｃｇｓ、Ｃｓｃ、Ｃｓｐ、Ｃｇｃ、Ｃｇｄは、Ｃｓに比べて小さく、大まかに言って２桁程度小さい。したがって、ソース配線４Ｗで１フレーム中に消費される最大電力量は、画素Ｐｘで１フレームに消費される最大電力量と同等であり、ゲート配線２Ｗで１フレーム中に消費される電力量はそれらより２桁小さい。 The coefficients of the amount of power consumed as described above are 2MN ^ 2 for the source wiring 4W, MN for the gate wiring 2W, and MN for the pixel Px. Usually, M and N are tens to hundreds. In general, Cgs, Csc, Csp, Cgc, and Cgd are smaller than Cs, roughly about two orders of magnitude smaller. Therefore, the maximum amount of power consumed in one frame by the source wiring 4W is equivalent to the maximum amount of power consumed in one frame by the pixel Px, and the amount of power consumed in one frame by the gate wiring 2W is those. Two orders of magnitude smaller than.

また、電子ペーパーでは同画像を数フレーム（１０フレーム程度）に亘って描くことが多い。この場合、第１フレームでの書替に電力量を消費するが、第２〜１０フレームでは同電位なのでほとんど消費しない。すると、ソース配線４Ｗで約１０フレーム中に消費される最大電力量は大きく、画素Ｐｘで約１０フレーム中に消費される最大電力量はソース配線４Ｗで約１０フレーム中に消費される最大電力量より１桁小さく、ゲート配線２Ｗで約１０フレーム中に消費される電力量は画素Ｐｘで約１０フレーム中に消費される最大電力量よりさらに１桁小さい。したがって、ソース配線４Ｗに接続された容量（Ｃｇｓ、Ｃｓｃ、Ｃｓｐ）を小さくすることが、消費電力量を減らすために重要である。 Further, in electronic paper, the same image is often drawn over several frames (about 10 frames). In this case, the amount of electric power is consumed for rewriting in the first frame, but it is hardly consumed in the second to tenth frames because the potential is the same. Then, the maximum electric energy consumed in about 10 frames by the source wiring 4W is large, and the maximum electric energy consumed in about 10 frames by the pixel Px is the maximum electric energy consumed in about 10 frames by the source wiring 4W. The amount of power consumed in about 10 frames by the gate wiring 2W is one digit smaller than the maximum amount of power consumed in about 10 frames by the pixel Px. Therefore, it is important to reduce the capacitance (Cgs, Csc, Csp) connected to the source wiring 4W in order to reduce the power consumption.

以上のような構成をとり運用される本実施形態の表示部品１００は、ソース配線４Ｗと画素電極１０とが重なる部分を減少させることにより、ソース配線４Ｗと画素電極１０との重なりによるソース・画素電極間容量Ｃｓｐを小さくすることができるため、消費電力量を減らす効果がある。すなわち、上記のＴＦＴアレイを表示装置に用いることにより、表示装置の書替時の消費電力量を低減することができ、電池内蔵タイプの表示装置の電池交換頻度を減らすことができる。また、ＲＦ電波から電力変換するタイプの表示装置の場合は、書替可能距離を長くすることができる。 The display component 100 of the present embodiment, which is operated with the above configuration, has a source pixel due to the overlap of the source wiring 4W and the pixel electrode 10 by reducing the portion where the source wiring 4W and the pixel electrode 10 overlap. Since the capacitance Csp between electrodes can be reduced, there is an effect of reducing the amount of power consumption. That is, by using the above-mentioned TFT array for the display device, it is possible to reduce the power consumption at the time of rewriting the display device, and it is possible to reduce the frequency of battery replacement of the display device having a built-in battery. Further, in the case of a display device of a type that converts power from RF radio waves, the rewritable distance can be lengthened.

次に、表示部品１００において横方向Ｄ１に並ぶ画素電極１０の間の隙間にソース配線４Ｗの一部が含まれることによる表示への影響について説明する。 Next, the influence on the display due to the inclusion of a part of the source wiring 4W in the gap between the pixel electrodes 10 arranged in the horizontal direction D1 in the display component 100 will be described.

平面視で、横方向Ｄ１に並ぶ画素電極１０の間の隙間に含まれるソース配線４Ｗの部分と重なる部分について、図７に示すように、仮想画素電極１０Ｘを考える。透明電極１２の電位が０Ｖ、時間ｔ＝０で印加するソース配線４Ｗの電位をＶｓとする。表示媒体層１２０の抵抗をＲｐ、容量をＣｐ、層間絶縁膜８の抵抗をＲｉｎｓ、容量をＣｉｎｓとする。 As shown in FIG. 7, a virtual pixel electrode 10X is considered for a portion that overlaps with the portion of the source wiring 4W included in the gap between the pixel electrodes 10 arranged in the lateral direction D1 in a plan view. Let Vs be the potential of the source wiring 4W applied when the potential of the transparent electrode 12 is 0V and the time t = 0. The resistance of the display medium layer 120 is Rp, the capacitance is Cp, the resistance of the interlayer insulating film 8 is Rins, and the capacitance is Cins.

表示媒体層１２０の抵抗Ｒｐは小さく、容量Ｃｐは小さい（インピーダンスの容量成分が大きい）。層間絶縁膜８の抵抗Ｒｉｎｓは大きく、容量Ｃｉｎｓは大きい（インピーダンスの容量成分が小さい）。よって、表示媒体層１２０の容量Ｃｐと層間絶縁膜８の抵抗Ｒｉｎｓを無視でき、図７のように表示媒体層１２０の抵抗Ｒｐと層間絶縁膜８の容量Ｃｐのみを考える。 The resistance Rp of the display medium layer 120 is small, and the capacitance Cp is small (the capacitance component of impedance is large). The resistance Rins of the interlayer insulating film 8 is large, and the capacitance Cins is large (the capacitance component of impedance is small). Therefore, the capacitance Cp of the display medium layer 120 and the resistance Rins of the interlayer insulating film 8 can be ignored, and only the resistance Rp of the display medium layer 120 and the capacitance Cp of the interlayer insulating film 8 are considered as shown in FIG.

すると、ソース配線４Ｗを入力電圧とする時、仮想電極１０Ｘの電位は、図８のような微分波形で与えられる。即ち、ソース配線４Ｗの電位が０ＶからＶｓに変化する瞬間には電圧がかかるが、長くは続かない。 Then, when the source wiring 4W is used as the input voltage, the potential of the virtual electrode 10X is given by the differential waveform as shown in FIG. That is, a voltage is applied at the moment when the potential of the source wiring 4W changes from 0V to Vs, but it does not last for a long time.

図９に示すように、平面視で、横方向Ｄ１に並ぶ画素電極１０の間の隙間に含まれるソース配線４Ｗの横方向Ｄ１の寸法をＷｓｌｏとする。Ｗｓｌｏが、画素電極１０と透明電極１２の距離Ｄより充分に大きければ、図１０（ａ）のように電気力線はほぼ平行になり、透明電極１２近傍での電界は瞬間的にＶｓ／Ｄになってから図８のように減衰する。 As shown in FIG. 9, in a plan view, the dimension of the source wiring 4W included in the gap between the pixel electrodes 10 arranged in the lateral direction D1 in the lateral direction D1 is defined as Wslo. If Wslo is sufficiently larger than the distance D between the pixel electrode 10 and the transparent electrode 12, the lines of electric force become almost parallel as shown in FIG. 10A, and the electric field near the transparent electrode 12 momentarily Vs / D. After that, it attenuates as shown in FIG.

しかし、寸法Ｗｓｌｏが画素電極１０と透明電極１２の距離Ｄより小さければ、電気力線が透明電極１２側で広がり、透明電極近傍での電界は弱くなる。計算機シミュレーションによれば、Ｗｓｌｏ＝Ｄの場合（図１０（ｂ））、透明電極１２近傍の電界は図１０（ａ）の約０．６６倍であり、Ｗｓｌｏ＝Ｄ／１０の場合（図１０（ｃ））、透明電極１２近傍の電界は図１０（ａ）の約０．１０倍になる。電界が弱く、かつ、すぐに減衰するため、図１０（ｂ）や図１０（ｃ）では粒子の移動が起きず、色変化しない。 However, if the dimension Wslo is smaller than the distance D between the pixel electrode 10 and the transparent electrode 12, the electric lines of force spread on the transparent electrode 12 side, and the electric field in the vicinity of the transparent electrode becomes weak. According to the computer simulation, when Wslo = D (FIG. 10 (b)), the electric field near the transparent electrode 12 is about 0.66 times that of FIG. 10 (a), and when Wslo = D / 10 (FIG. 10). (C)), The electric field in the vicinity of the transparent electrode 12 is about 0.10 times that in FIG. 10 (a). Since the electric field is weak and attenuates immediately, the particles do not move and the color does not change in FIGS. 10 (b) and 10 (c).

次に、本発明の第二実施形態に係る表示部品について、図１１から図１３を参照しながら説明する。図１１から図１３は本実施形態に係る表示部品２００の一部であり、表示部品２００は図に記載された構成をマトリクス状に複数並べて接続した構成を有する。図１１及び図１２は表示部品２００の特徴をわかりやすく示すための製造途中の図であり、図１１は基板上にＴＦＴ等を形成した状態であって、図１２はさらに画素電極等を形成した状態である。図１３は完成図であり、表示媒体層等が積層された表示部品２００の断面図を示している。 Next, the display component according to the second embodiment of the present invention will be described with reference to FIGS. 11 to 13. 11 to 13 are a part of the display component 200 according to the present embodiment, and the display component 200 has a configuration in which a plurality of the configurations shown in the drawings are arranged and connected in a matrix. 11 and 12 are views in the middle of manufacturing for showing the features of the display component 200 in an easy-to-understand manner. FIG. 11 shows a state in which a TFT or the like is formed on a substrate, and FIG. 12 shows a state in which a pixel electrode or the like is further formed. It is in a state. FIG. 13 is a completed view and shows a cross-sectional view of the display component 200 on which the display medium layer and the like are laminated.

表示部品２００は、図１２に示すように、平面視で、横方向Ｄ１に並ぶ画素電極１０の間の隙間に、ソース配線４Ｗの全部が含まれるように配置される。その他は表示部品１００と同等の構成である。 As shown in FIG. 12, the display component 200 is arranged so that the entire source wiring 4W is included in the gap between the pixel electrodes 10 arranged in the lateral direction D1 in a plan view. Others have the same configuration as the display component 100.

表示部品２００は、ソース配線４Ｗと画素電極１０とが重なる部分をなくすことにより、ソース配線４Ｗと画素電極１０との重なりによるソース・画素電極間容量Ｃｓｐを０Ｆ近くとすることができるため、表示部品１００より消費電力量を減らす効果がある。 By eliminating the portion where the source wiring 4W and the pixel electrode 10 overlap, the display component 200 can set the capacitance Csp between the source and the pixel electrodes due to the overlap between the source wiring 4W and the pixel electrode 10 to be close to 0F. It has the effect of reducing the amount of power consumption compared to the component 100.

表示部品２００では、図１４に示すように、平面視で、横方向Ｄ１に並ぶ画素電極１０の間の隙間に含まれるソース配線４Ｗの横方向Ｄ１の寸法Ｗｓｌｏが、ソース配線４Ｗの横方向Ｄ１の寸法となる。 In the display component 200, as shown in FIG. 14, in a plan view, the dimension Wslo of the source wiring 4W in the lateral direction D1 included in the gap between the pixel electrodes 10 arranged in the lateral direction D1 is the lateral direction D1 of the source wiring 4W. It becomes the dimension of.

寸法Ｗｓｌｏが画素電極１０と透明電極１２の距離Ｄより小さければ、透明電極１２近傍の電界が小さくなり、粒子の移動が起きなくなり、色変化しない。 If the dimension Wslo is smaller than the distance D between the pixel electrode 10 and the transparent electrode 12, the electric field in the vicinity of the transparent electrode 12 becomes small, particles do not move, and the color does not change.

以上のような構成をとり運用される本実施形態の表示部品２００は、ソース配線４Ｗと画素電極１０とが重なる部分をなくすことにより、ソース配線４Ｗと画素電極１０との重なりによるソース・画素電極間容量Ｃｓｐを０Ｆ近くとすることができるため、消費電力量を減らす効果がある。すなわち、上記のＴＦＴアレイを表示装置に用いることにより、表示装置の書替時の消費電力量を低減することができ、電池内蔵タイプの表示装置の電池交換頻度を減らすことができる。また、ＲＦ電波から電力変換するタイプの表示装置の場合は、書替可能距離を長くすることができる。 The display component 200 of the present embodiment, which is operated with the above configuration, has a source / pixel electrode due to the overlap of the source wiring 4W and the pixel electrode 10 by eliminating the portion where the source wiring 4W and the pixel electrode 10 overlap. Since the inter-capacity Csp can be set to near 0F, there is an effect of reducing the amount of power consumption. That is, by using the above-mentioned TFT array for the display device, it is possible to reduce the power consumption at the time of rewriting the display device, and it is possible to reduce the frequency of battery replacement of the display device having a built-in battery. Further, in the case of a display device of a type that converts power from RF radio waves, the rewritable distance can be lengthened.

次に、本発明の第三実施形態に係る表示装置について、図１５及び図１６を参照しながら説明する。図１５は、本実施形態に係る表示装置３００の概略を示す平面図である。図１６は、本実施形態の変形例に係る表示装置３２０の概略を示す平面図である。 Next, the display device according to the third embodiment of the present invention will be described with reference to FIGS. 15 and 16. FIG. 15 is a plan view showing an outline of the display device 300 according to the present embodiment. FIG. 16 is a plan view showing an outline of the display device 320 according to the modified example of the present embodiment.

図１５に示すように、本実施形態に係る表示装置３００は、第一実施形態又は第二実施形態の構成に加え、ドライバＩＣ３１０を有する。 As shown in FIG. 15, the display device 300 according to the present embodiment has a driver IC 310 in addition to the configuration of the first embodiment or the second embodiment.

ドライバＩＣ３１０は、第１ゲート出力端子２Ｐ１と、第２ゲート出力端子２Ｐ２と、ソース出力端子４Ｐと、を有する。第１ゲート出力端子２Ｐ１、ソース出力端子４Ｐ及び第２ゲート出力端子２Ｐ２は、この順に並べてドライバＩＣ３１０に設けられる。ただしドライバＩＣ３１０は１チップである必要はなく、２チップまたは３チップで構成されてもよい。例えば図１７のように、第１ゲート出力端子２Ｐ１とソース出力端子４Ｐの一部が１つのチップ上にあり、ソース出力端子４Ｐの残りと第２ゲート出力端子２Ｐ２が別チップでもよい。 The driver IC 310 has a first gate output terminal 2P1, a second gate output terminal 2P2, and a source output terminal 4P. The first gate output terminal 2P1, the source output terminal 4P, and the second gate output terminal 2P2 are provided in the driver IC 310 in this order. However, the driver IC 310 does not have to be one chip, and may be composed of two chips or three chips. For example, as shown in FIG. 17, a part of the first gate output terminal 2P1 and the source output terminal 4P may be on one chip, and the rest of the source output terminal 4P and the second gate output terminal 2P2 may be separate chips.

表示装置３００では、ゲート配線２Ｗは、絶縁基板１の第１の縁から延びる第１ゲート配線群２Ｗ１と、絶縁基板１を挟んで第１の縁と向かい合う第２の縁から延びる第２ゲート配線群２Ｗ２と、を有する。第１ゲート配線群２Ｗ１と第２ゲート配線群２Ｗ２とが縦方向Ｄ２に並んで交互に配置される。 In the display device 300, the gate wiring 2W is the first gate wiring group 2W1 extending from the first edge of the insulating substrate 1 and the second gate wiring extending from the second edge facing the first edge with the insulating substrate 1 in between. It has a group 2W2 and. The first gate wiring group 2W1 and the second gate wiring group 2W2 are arranged alternately in the vertical direction D2.

第１ゲート出力端子２Ｐ１は第１ゲート配線群２Ｗ１と接続され、第２ゲート出力端子２Ｐ２は第２ゲート配線群２Ｗ２と接続され、ソース出力端子４Ｐはソース配線４Ｗと接続される。 The first gate output terminal 2P1 is connected to the first gate wiring group 2W1, the second gate output terminal 2P2 is connected to the second gate wiring group 2W2, and the source output terminal 4P is connected to the source wiring 4W.

以上のような構成をとり運用される本実施形態の表示装置３００は、表示部品１００又は表示部品２００を用いているため、消費電力を小さくでき、表示への影響はない。 Since the display device 300 of the present embodiment, which is operated with the above configuration, uses the display component 100 or the display component 200, the power consumption can be reduced and the display is not affected.

本実施形態における変形例を図１６に示す。
本実施形態に係る表示装置３２０は、第一実施形態又は第二実施形態の構成に加え、ドライバＩＣ３３０を有する。 A modified example of this embodiment is shown in FIG.
The display device 320 according to the present embodiment has a driver IC 330 in addition to the configuration of the first embodiment or the second embodiment.

ドライバＩＣ３３０は、ゲート出力端子２Ｐと、第１ソース出力端子４Ｐ１と、第２ソース出力端子４Ｐ２と、を有する。第１ソース出力端子４Ｐ１、ゲート出力端子２Ｐ及び第２ソース出力端子４Ｐ２は、この順に並べてドライバＩＣ３３０に設けられる。ただしドライバＩＣ３３０は１チップである必要はなく、２チップまたは３チップで構成されてもよい。例えば、第１ソース出力端子４Ｐ１とゲート出力端子２Ｐの一部が１つのチップ上にあり、ゲート出力端子２Ｐの残りと第２ソース出力端子４Ｐ２が別チップでもよい。 The driver IC 330 has a gate output terminal 2P, a first source output terminal 4P1, and a second source output terminal 4P2. The first source output terminal 4P1, the gate output terminal 2P, and the second source output terminal 4P2 are provided in the driver IC 330 side by side in this order. However, the driver IC 330 does not have to be one chip, and may be composed of two chips or three chips. For example, a part of the first source output terminal 4P1 and the gate output terminal 2P may be on one chip, and the rest of the gate output terminal 2P and the second source output terminal 4P2 may be separate chips.

表示装置３２０では、ソース配線４Ｗは、絶縁基板１の第１の縁から延びる第１ソース配線群４Ｗ１と、絶縁基板１を挟んで第１の縁と向かい合う第２の縁から延びる第２ソース配線群４Ｗ２と、を有する。第１ソース配線群４Ｗ１と第２ソース配線群４Ｗ２とが横方向Ｄ１に並んで交互に配置される。 In the display device 320, the source wiring 4W is the first source wiring group 4W1 extending from the first edge of the insulating substrate 1 and the second source wiring extending from the second edge facing the first edge with the insulating substrate 1 in between. It has a group of 4W2 and. The first source wiring group 4W1 and the second source wiring group 4W2 are arranged alternately in the horizontal direction D1.

第１ソース出力端子４Ｐ１は第１ソース配線群４Ｗ１と接続され、第２ソース出力端子４Ｐ２は第２ソース配線群４Ｗ２と接続され、ゲート出力端子２Ｐはゲート配線２Ｗと接続される。 The first source output terminal 4P1 is connected to the first source wiring group 4W1, the second source output terminal 4P2 is connected to the second source wiring group 4W2, and the gate output terminal 2P is connected to the gate wiring 2W.

以上のような構成をとり運用される本実施形態の表示装置３２０は、表示部品１００又は表示部品２００を用いているため、消費電力を小さくでき、表示への影響はない。 Since the display device 320 of the present embodiment, which is operated with the above configuration, uses the display component 100 or the display component 200, the power consumption can be reduced and the display is not affected.

以上、本発明の各実施形態について説明したが、本発明の技術範囲は上記実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において構成要素の組み合わせを変えたり、各構成要素に種々の変更を加えたり、削除したりすることが可能である。 Although each embodiment of the present invention has been described above, the technical scope of the present invention is not limited to the above-described embodiment, and the combination of components may be changed or each component may be changed without departing from the spirit of the present invention. Can be modified or deleted.

次に、本発明の表示部品及び表示装置について、実施例および比較例を用いてさらに説明する。ただし、本発明は以下の実施例に限定されるものではない。 Next, the display component and the display device of the present invention will be further described with reference to Examples and Comparative Examples. However, the present invention is not limited to the following examples.

（実施例１）
図１１〜図１３の製造工程によって図１３の表示部品２００を作製した。絶縁基板１としてガラス基板を用いた。ゲート電極２、ゲート配線２Ｗ、及びドレイン副電極７はＭｏ系金属膜で形成した。ゲート絶縁膜３はＳｉＮで形成した。半導体パターン６はＳｉで形成した。ソース電極４、ソース配線４Ｗ、ドレイン電極５、ドレイン接続配線５Ｃ、及びドレインビアホール接続５ＶはＭｏ系金属で形成した。層間絶縁膜８はＳｉＮと有機膜とを積層して形成した。画素電極１０及び画素電極ビアホール接続１０ＶはＩＴＯで形成した。上記のように背面板１１０を形成した。ただし、背面板１１０には、ゲート接続配線２ＣＷ、ソース接続配線４ＣＷ、及びキャパシタ接続配線９ＣＷを形成した。なお、ゲート線数Ｎ＝２９６、ソース線数Ｍ＝１２８であり、画素Ｐｘを並べて形成される画面のサイズは対角２．９インチである。 (Example 1)
The display component 200 of FIG. 13 was manufactured by the manufacturing process of FIGS. 11 to 13. A glass substrate was used as the insulating substrate 1. The gate electrode 2, the gate wiring 2W, and the drain sub-electrode 7 were formed of a Mo-based metal film. The gate insulating film 3 was formed of SiN. The semiconductor pattern 6 is made of Si. The source electrode 4, the source wiring 4W, the drain electrode 5, the drain connection wiring 5C, and the drain via hole connection 5V were made of Mo-based metal. The interlayer insulating film 8 was formed by laminating SiN and an organic film. The pixel electrode 10 and the pixel electrode via hole connection 10V were formed of ITO. The back plate 110 was formed as described above. However, the gate connection wiring 2CW, the source connection wiring 4CW, and the capacitor connection wiring 9CW are formed on the back plate 110. The number of gate lines N = 296, the number of source lines M = 128, and the size of the screen formed by arranging the pixels Px is 2.9 inches diagonally.

次に、対向基板１３０上に透明電極１２を形成し、表示媒体層１２０を形成した部材を背面板１１０上にラミネートして、表示部品２００とした。 Next, the transparent electrode 12 was formed on the opposed substrate 130, and the member on which the display medium layer 120 was formed was laminated on the back plate 110 to form the display component 200.

さらに、図１５に示す表示装置３００を作製した。即ち、ドライバＩＣ３１０を背面板１１０上に実装した。その結果、ゲート出力端子２Ｐ１が第１ゲート配線群２Ｗ１に、ソース出力端子４Ｐがソース配線４Ｗに、ゲート出力端子２Ｐ２が第２ゲート配線群２Ｗ２に、対向電圧出力端子がキャパシタ配線９Ｗおよび対向電極１２に接続された。 Further, the display device 300 shown in FIG. 15 was manufactured. That is, the driver IC 310 was mounted on the back plate 110. As a result, the gate output terminal 2P1 is in the first gate wiring group 2W1, the source output terminal 4P is in the source wiring 4W, the gate output terminal 2P2 is in the second gate wiring group 2W2, and the opposite voltage output terminal is in the capacitor wiring 9W and the opposite electrode. Connected to 12.

ドライバＩＣ３１０の入力端子（図示せず）に所定の駆動装置を接続し、１行毎に白と黒が交互に並ぶ「１行毎ストライプ画像」を表示させたところ、書替に必要な消費電力量は７．８ｍＪであった。ただし、Ｗｓｌｏ＝３．５μｍ、Ｄ＝３０μｍ、Ｗｐｘ＝２２０．５μｍ、Ｖｓ＝５Ｖ、ΔＶｇ＝２０Ｖ、フレーム周波数＝５０Ｈｚである。また、ソース配線４Ｗに起因する表示媒体層１２０の色変化は見られなかった。 When a predetermined drive device was connected to the input terminal (not shown) of the driver IC 310 and a "striped image for each line" in which white and black were alternately arranged for each line was displayed, the power consumption required for rewriting was displayed. The amount was 7.8 mJ. However, Wslo = 3.5 μm, D = 30 μm, Wpx = 220.5 μm, Vs = 5 V, ΔVg = 20 V, and frame frequency = 50 Hz. Further, no color change of the display medium layer 120 due to the source wiring 4W was observed.

（比較例１）
実施例１と同じ製造工程によって図１８、図１９を経て図２０の表示部品１００Ａを作製し、図１５と似た表示装置を得た。「１行毎ストライプ画像」を表示させたところ、書替に必要な消費電力量は８．６ｍＪであった。ただし、Ｗｓｌｏ＝０μｍ、Ｄ＝３０μｍ、Ｗｐｘ＝２２０．５μｍ、Ｖｓ＝５Ｖ、ΔＶｇ＝２０Ｖ、フレーム周波数＝５０Ｈｚである。 (Comparative Example 1)
The display component 100A of FIG. 20 was manufactured by the same manufacturing process as in Example 1 through FIGS. 18 and 19, and a display device similar to that of FIG. When the "striped image for each line" was displayed, the power consumption required for rewriting was 8.6 mJ. However, Wslo = 0 μm, D = 30 μm, Wpx = 220.5 μm, Vs = 5 V, ΔVg = 20 V, and frame frequency = 50 Hz.

（実施例２）
実施例１と同じ製造工程によって図１、図２を経て図３の表示部品１００を作製した。図１０のように、絶縁膜８の下の寸法Ｗｓｌｏを変えて、ソース配線４Ｗ・透明電極１２間に電圧を印加し、表示媒体層１２０の色が変わるかどうかを調べた。印加電圧は±５Ｖの矩形波、周波数は０．２Ｈｚ、表示媒体層１２０の厚さＤ＝３０μｍである。Ｗｓｌｏ＝１１０μｍの場合、２．５秒毎に色が変化した。Ｗｓｌｏ＝２５μｍの場合と、Ｗｓｌｏ＝９μｍの場合、色は変化しなかった。なお、絶縁膜８は積層膜であり、ＳｉＮの厚さは０．３μｍ又は０．７μｍ、有機膜の厚さは２μｍである。 (Example 2)
The display component 100 of FIG. 3 was manufactured through FIGS. 1 and 2 by the same manufacturing process as in Example 1. As shown in FIG. 10, the dimension Wslo under the insulating film 8 was changed, a voltage was applied between the source wiring 4W and the transparent electrode 12, and it was examined whether or not the color of the display medium layer 120 changed. The applied voltage is a rectangular wave of ± 5 V, the frequency is 0.2 Hz, and the thickness D of the display medium layer 120 is 30 μm. When Wslo = 110 μm, the color changed every 2.5 seconds. The color did not change when Wslo = 25 μm and when Wslo = 9 μm. The insulating film 8 is a laminated film, and the thickness of SiN is 0.3 μm or 0.7 μm, and the thickness of the organic film is 2 μm.

１ 絶縁基板（第１の絶縁基板）
１００、１００Ａ、２００ 表示部品
１１０ 背面板
１２０ 表示媒体層
１３０ 対向基板
２ ゲート電極
２Ｐ ゲート出力端子
２Ｐ１ 第１ゲート出力端子
２Ｐ２ 第２ゲート出力端子
２Ｗ ゲート配線
２Ｗ１ 第１ゲート配線群
２Ｗ２ 第２ゲート配線群
２０ ＴＦＴ（薄膜トランジスタ）
３ ゲート絶縁膜
３００、３２０ 表示装置
３１０、３３０ ドライバＩＣ
４ ソース電極
４Ｐ ソース出力端子
４Ｐ１ 第１ソース出力端子
４Ｐ２ 第２ソース出力端子
４Ｗ ソース配線
４Ｗ１ 第１ソース配線群
４Ｗ２ 第２ソース配線群
５ ドレイン電極
６ 半導体パターン
７ ドレイン副電極
１０ 画素電極
１１ 絶縁基板（第２の絶縁基板）
１２ 透明電極
Ｄ１ 横方向（第１の方向）
Ｄ２ 縦方向（第２の方向）
Ｐｘ 画素 1 Insulated substrate (first insulated substrate)
100, 100A, 200 Display component 110 Back plate 120 Display medium layer 130 Opposing board 2 Gate electrode 2P Gate output terminal 2P1 1st gate output terminal 2P2 2nd gate output terminal 2W Gate wiring 2W1 1st gate wiring group 2W2 2nd gate wiring Group 20 TFT (thin film transistor)
3 Gate insulating film 300, 320 Display device 310, 330 Driver IC
4 Source electrode 4P Source output terminal 4P1 1st source output terminal 4P2 2nd source output terminal 4W Source wiring 4W1 1st source wiring group 4W2 2nd source wiring group 5 Drain electrode 6 Semiconductor pattern 7 Drain sub-electrode 10 Pixel electrode 11 Insulated substrate (Second insulating substrate)
12 Transparent electrode D1 Lateral direction (first direction)
D2 vertical direction (second direction)
Px pixel

Claims (5)

背面板と、
前記背面板上に積層される表示媒体層と、
前記表示媒体層上に積層される対向基板と、が順次積層され、
前記背面板は、
第１の絶縁基板と、
第１の方向に延びて前記第１の絶縁基板上に設けられる複数のゲート配線と、
前記第１の方向に交差する第２の方向に延びて前記第１の絶縁基板上に設けられる複数のソース配線と、
前記ゲート配線に接続されるゲート電極と、前記ソース配線に接続されるソース電極と、ドレイン電極と、を有し前記第１の絶縁基板上に複数設けられる薄膜トランジスタと、
各々の前記薄膜トランジスタに対応して設けられ、前記ドレイン電極と接続され、前記表示媒体層に電気的に接続し、前記ソース配線より前記表示媒体層側に、前記第１の方向及び前記第２の方向に沿ってマトリクス状に前記第１の絶縁基板上に設けられる画素電極と、を有し、
前記表示媒体層は、電気泳動粒子を有し、
前記対向基板は、第２の絶縁基板と、前記表示媒体層と電気的に接続する透明電極と、を有し、
平面視で、前記第１の方向に並ぶ前記画素電極の間の隙間に前記ソース配線の少なくとも一部が含まれるように配置される、
表示部品。 Back plate and
The display medium layer laminated on the back plate and
The facing substrate to be laminated on the display medium layer is sequentially laminated,
The back plate is
The first insulating substrate and
A plurality of gate wirings extending in the first direction and provided on the first insulating substrate,
A plurality of source wirings extending in a second direction intersecting the first direction and provided on the first insulating substrate, and a plurality of source wirings.
A thin film transistor having a gate electrode connected to the gate wiring, a source electrode connected to the source wiring, and a drain electrode, and a plurality of thin film transistors provided on the first insulating substrate.
Provided corresponding to each of the thin film transistors, connected to the drain electrode, electrically connected to the display medium layer, and from the source wiring to the display medium layer side, the first direction and the second direction. It has pixel electrodes provided on the first insulating substrate in a matrix along the direction.
The display medium layer has electrophoretic particles and has
The facing substrate has a second insulating substrate and a transparent electrode that is electrically connected to the display medium layer.
Arranged so that at least a part of the source wiring is included in the gap between the pixel electrodes arranged in the first direction in a plan view.
Display parts. 平面視で、前記第１の方向に並ぶ前記画素電極の間の前記隙間に前記ソース配線の全部が露出するように配置される、
請求項１に記載の表示部品。 In a plan view, the source wiring is arranged so as to be entirely exposed in the gap between the pixel electrodes arranged in the first direction.
The display component according to claim 1. 平面視で、前記第１の方向に並ぶ前記画素電極の間の前記隙間に露出する前記ソース配線の部分の前記第１の方向の寸法が、前記画素電極と前記透明電極との距離より小さい請求項１又は請求項２に記載の表示部品。 Claim that the dimension of the source wiring portion exposed in the gap between the pixel electrodes arranged in the first direction is smaller than the distance between the pixel electrode and the transparent electrode in a plan view. The display component according to claim 1 or 2. 請求項１から請求項３のいずれか１項に記載の前記表示部品と、
前記ゲート配線及び前記ソース配線に接続されるドライバＩＣと、を備え、
前記ゲート配線は、前記第１の絶縁基板の第１の縁から第１の方向に延びる第１ゲート配線群と、前記第１の絶縁基板を挟んで前記第１の縁と向かい合う第２の縁から第１の方向に延びる第２ゲート配線群と、が前記第２の方向に並んで交互に配置され、
前記ドライバＩＣは、前記第１ゲート配線群と接続される第１ゲート出力端子と、前記ソース配線と接続されるソース出力端子と、前記第２ゲート配線群と接続される第２ゲート出力端子と、を備え、前記第１ゲート出力端子、前記ソース出力端子、及び前記第２ゲート出力端子の順に並べて設けられる、
表示装置。 The display component according to any one of claims 1 to 3, and the display component.
The gate wiring and the driver IC connected to the source wiring are provided.
The gate wiring includes a first gate wiring group extending in a first direction from the first edge of the first insulating substrate, and a second edge facing the first edge with the first insulating substrate interposed therebetween. The second gate wiring group extending from the first direction is arranged side by side in the second direction and alternately arranged.
The driver IC includes a first gate output terminal connected to the first gate wiring group, a source output terminal connected to the source wiring, and a second gate output terminal connected to the second gate wiring group. , The first gate output terminal, the source output terminal, and the second gate output terminal are provided in this order.
Display device. 請求項１から請求項３のいずれか１項に記載の前記表示部品と、
前記ゲート配線及び前記ソース配線に接続されるドライバＩＣと、を備え、
前記ソース配線は、前記第１の絶縁基板の第１の縁から第２の方向に延びる第１ソース配線群と、前記第１の絶縁基板を挟んで前記第１の縁と向かい合う第２の縁から第２の方向に延びる第２ソース配線群と、が前記第１の方向に並んで交互に配置され、
前記ドライバＩＣは、前記第１ソース配線群と接続される第１ソース出力端子と、前記ゲート配線と接続されるゲート出力端子と、前記第２ソース配線群と接続される第２ソース出力端子と、を備え、前記第１ソース出力端子、前記ゲート出力端子、及び前記第２ソース出力端子の順に並べて設けられる、
表示装置。 The display component according to any one of claims 1 to 3, and the display component.
The gate wiring and the driver IC connected to the source wiring are provided.
The source wiring includes a first source wiring group extending in a second direction from the first edge of the first insulating substrate, and a second edge facing the first edge with the first insulating substrate interposed therebetween. The second source wiring group extending in the second direction from the second source wiring group and the second source wiring group are arranged side by side in the first direction and alternately arranged.
The driver IC includes a first source output terminal connected to the first source wiring group, a gate output terminal connected to the gate wiring, and a second source output terminal connected to the second source wiring group. , The first source output terminal, the gate output terminal, and the second source output terminal are provided in this order.
Display device.
JP2019181632A 2019-10-01 2019-10-01 Display component and display device Pending JP2021057531A (en)

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