JP2021047721A - メモリシステムおよび方法 - Google Patents
メモリシステムおよび方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 12
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M13/353—Adaptation to the channel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1515—Reed-Solomon codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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- Microelectronics & Electronic Packaging (AREA)
- Probability & Statistics with Applications (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
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Abstract
Description
Claims (7)
- 複数のブロックを有する不揮発性の半導体メモリと、
前記ブロックごとに、ビットエラーレートの経時的変化のトレンドを求め、前記トレンドに基づいて、リフレッシュ処理のタイミングを決定するメモリコントローラと、
を備えるメモリシステム。 - 前記メモリコントローラは、
前記トレンドに基づいて、データに対して割り当てる可変長符号の符号化率を設定する、
請求項1に記載のメモリシステム。 - 前記メモリコントローラは、
前記トレンドを示す指標として、データを保存可能な予測期間が短いほど値が大きい所定の指標値を管理し、前記指標値に基づいて時間経過と前記指標値の変化に関する回帰式を算出し、前記回帰式に基づいて電源オフ中の前記指標値を推定する、
請求項1または請求項2に記載のメモリシステム。 - 前記メモリコントローラは、
前記半導体メモリの温度、および、書込/消去回数に応じて、前記指標値に対する加算値を記憶する加算値テーブルを記憶しており、
前記ブロックにおける所定の記憶領域ごとに、前記指標値を管理し、所定の周期で、前記半導体メモリの温度、および、書込/消去回数を取得し、前記加算値テーブルに基づいて、前記指標値に、該当する前記加算値を加算する、
請求項3に記載のメモリシステム。 - 前記メモリコントローラは、
前記ビットエラーレートを算出する場合に、前記半導体メモリのメモリセルの電位分布における谷の位置を検索するトラッキング処理によって決定したリード電圧によるデータのリード結果と、データをエラー訂正した結果と、に基づいて、前記ビットエラーレートを算出する、
請求項1から請求項4のいずれか一項に記載のメモリシステム。 - 前記メモリコントローラは、
前記リフレッシュ処理を行った場合、前記リフレッシュ処理を行った前記ブロックに対応する前記指標値を0にリセットする、
請求項3または請求項4に記載のメモリシステム。 - 複数のブロックを有する不揮発性の半導体メモリを備えるメモリシステムの制御方法であって、
前記ブロックごとに、ビットエラーレートの経時的変化のトレンドを求め、
前記トレンドに基づいて、リフレッシュ処理のタイミングを決定する、
方法。
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JP2019170738A JP7353889B2 (ja) | 2019-09-19 | 2019-09-19 | メモリシステムおよび方法 |
US16/799,326 US11138070B2 (en) | 2019-09-19 | 2020-02-24 | Memory system and method performed thereby |
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Families Citing this family (4)
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CN115729767A (zh) * | 2021-08-30 | 2023-03-03 | 华为技术有限公司 | 一种存储器的温度检测方法及装置 |
US11853607B2 (en) | 2021-12-22 | 2023-12-26 | Western Digital Technologies, Inc. | Optimizing flash memory utilization for NVMe KV pair storage |
US11817883B2 (en) * | 2021-12-27 | 2023-11-14 | Western Digital Technologies, Inc. | Variable length ECC code according to value length in NVMe key value pair devices |
US11733876B2 (en) | 2022-01-05 | 2023-08-22 | Western Digital Technologies, Inc. | Content aware decoding in KV devices |
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US11138070B2 (en) | 2021-10-05 |
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US20210089391A1 (en) | 2021-03-25 |
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