JP2021028935A - Semiconductor manufacturing apparatus - Google Patents

Semiconductor manufacturing apparatus Download PDF

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JP2021028935A
JP2021028935A JP2019147474A JP2019147474A JP2021028935A JP 2021028935 A JP2021028935 A JP 2021028935A JP 2019147474 A JP2019147474 A JP 2019147474A JP 2019147474 A JP2019147474 A JP 2019147474A JP 2021028935 A JP2021028935 A JP 2021028935A
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wafer
stage
fork
accommodating groove
semiconductor manufacturing
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JP7192707B2 (en
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勝也 久保田
Katsuya Kubota
勝也 久保田
照宏 村本
Teruhiro Muramoto
照宏 村本
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

To obtain a semiconductor manufacturing apparatus that can improve the positional accuracy of a wafer placed on a stage while preventing in-plane temperature variation of the wafer.SOLUTION: A fork 5 lifts and transports a wafer 4. The wafer 4 is placed on an upper surface of a stage 7. On the upper surface of the stage 7, a fork housing groove 11, into which the fork 5 enters, and a gas venting groove 12, which is provided at a different position from the fork housing groove 11 and communicates with the fork housing groove 11, are provided.SELECTED DRAWING: Figure 4

Description

本発明は、半導体製造装置に関するものであり、特に、処理するウエハが置かれるステージがウエハを固定保持する機構を持たない半導体製造装置に関する。 The present invention relates to a semiconductor manufacturing apparatus, and more particularly to a semiconductor manufacturing apparatus which does not have a mechanism in which a stage on which a wafer to be processed is placed fixes and holds a wafer.

半導体製造装置において、ウエハの裏面にフォークを入れてウエハを搬送して処理装置内のステージの上面に置く。製品によってウエハの裏面の状態と重量が異なる。ウエハの裏面の摩擦抵抗が少なく重量が軽いと、ステージ上でウエハの位置ずれ又は横滑りが生じる。これを防ぐために、ステージの上面に複数の溝を設け、溝内にステージを貫通する複数の通気孔を設けた半導体製造装置が知られている（例えば、特許文献１参照）。 In a semiconductor manufacturing apparatus, a fork is inserted into the back surface of the wafer to convey the wafer and place it on the upper surface of a stage in the processing apparatus. The condition and weight of the back surface of the wafer differ depending on the product. If the frictional resistance on the back surface of the wafer is low and the weight is light, the wafer may be misaligned or skid on the stage. In order to prevent this, a semiconductor manufacturing apparatus is known in which a plurality of grooves are provided on the upper surface of the stage and a plurality of vents are provided in the grooves to penetrate the stage (see, for example, Patent Document 1).

特開２００２−５７２０９号公報JP-A-2002-57209

従来の半導体製造装置では、ウエハの下面とステージの上面との間に存在するガスを逃がすためにステージの上面全面に多くの溝を形成している。溝の部分ではウエハとステージが接触しないため、温度調整性能が低下してウエハの面内温度分布がばらつく。これによりウエハに形成した薄膜の膜質異常などの問題が生じていた。 In a conventional semiconductor manufacturing apparatus, many grooves are formed on the entire upper surface of the stage in order to allow gas existing between the lower surface of the wafer and the upper surface of the stage to escape. Since the wafer and the stage do not come into contact with each other in the groove portion, the temperature adjustment performance deteriorates and the in-plane temperature distribution of the wafer varies. This causes problems such as abnormal film quality of the thin film formed on the wafer.

本発明は、上述のような課題を解決するためになされたもので、その目的はウエハの面内温度ばらつきを防ぎつつ、ステージに置くウエハの位置精度を向上させることができる半導体製造装置を得るものである。 The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor manufacturing apparatus capable of improving the position accuracy of a wafer placed on a stage while preventing in-plane temperature variation of the wafer. It is a thing.

本発明に係る半導体製造装置は、ウエハを持ち上げて搬送するフォークと、上面に前記ウエハが置かれるステージとを備え、前記ステージの前記上面に、前記フォークが入るフォーク収容溝と、前記フォーク収容溝とは異なる位置に設けられ前記フォーク収容溝に連通したガス抜き溝とが設けられていることを特徴とする。 The semiconductor manufacturing apparatus according to the present invention includes a fork for lifting and transporting a wafer and a stage on which the wafer is placed, and on the upper surface of the stage, a fork accommodating groove into which the fork is inserted and the fork accommodating groove are provided. It is characterized in that it is provided with a gas vent groove which is provided at a position different from the above and communicates with the fork accommodating groove.

本発明では、ウエハをステージに置く際にウエハの下面とステージの上面との間に存在するガスをガス抜き溝とフォーク収容溝を介して逃がすことができる。これにより、ウエハの位置ずれ及び横滑りを抑制することができるため、ステージに置くウエハの位置精度を向上させることができる。また、ウエハをステージに置くために元々設けられているフォーク収容溝とそれに連通したガス抜き溝をガスの排出に用いることで、従来のようにステージの上面に多くの溝を形成しなくてもよい。従って、温度調整性能があまり低下しないため、ウエハの面内温度ばらつきを防ぐことができる。 In the present invention, when the wafer is placed on the stage, the gas existing between the lower surface of the wafer and the upper surface of the stage can be released through the degassing groove and the fork accommodating groove. As a result, the displacement and sideslip of the wafer can be suppressed, so that the positioning accuracy of the wafer placed on the stage can be improved. Further, by using the fork accommodating groove originally provided for placing the wafer on the stage and the degassing groove communicating with the fork accommodating groove for discharging gas, it is not necessary to form many grooves on the upper surface of the stage as in the conventional case. Good. Therefore, since the temperature adjustment performance does not deteriorate so much, it is possible to prevent the in-plane temperature variation of the wafer.

実施の形態１に係る半導体製造装置を示す上面図である。It is a top view which shows the semiconductor manufacturing apparatus which concerns on Embodiment 1. FIG. ウエハがステージに正しく置かれた状態でデポを行う様子を示す断面図である。It is sectional drawing which shows the state that the depot is performed with the wafer correctly placed on the stage. ウエハの位置がずれた状態でデポを行う様子を示す断面図である。It is sectional drawing which shows the state which depot is performed in the state that the position of a wafer is deviated. 実施の形態１に係る半導体製造装置のステージを示す上面図である。It is a top view which shows the stage of the semiconductor manufacturing apparatus which concerns on Embodiment 1. FIG. 図４のＩ−ＩＩに沿った斜視断面図である。It is a perspective sectional view along I-II of FIG. 実施の形態２に係る半導体製造装置のステージを示す上面図である。It is a top view which shows the stage of the semiconductor manufacturing apparatus which concerns on Embodiment 2. 図６のＩＩＩ−ＩＶに沿った断面図である。FIG. 6 is a cross-sectional view taken along the line III-IV of FIG. 実施の形態２の変形例に係る半導体製造装置のステージを示す上面図である。It is a top view which shows the stage of the semiconductor manufacturing apparatus which concerns on the modification of Embodiment 2. 図８のＶ−ＶＩに沿った断面図である。FIG. 5 is a cross-sectional view taken along the line V-VI of FIG.

実施の形態に係る半導体製造装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。 The semiconductor manufacturing apparatus according to the embodiment will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted.

実施の形態１．
図１は、実施の形態１に係る半導体製造装置を示す上面図である。この半導体製造装置１００は、ウエハ上に薄膜を形成するＣＶＤ（Chemical Vapor Deposition）装置である。そして、半導体製造装置１００は、アーム構造を有する搬送ロボット１、ロードロックチャンバー２、ロードロックチャンバー２内に設けられたローダー３、回転軸に取り付けられた複数のフォーク５、処理室を構成するチャンバ６、チャンバ６内にあって複数のウエハ４を搭載可能なステージ７などを備えている。これに限らず、半導体製造装置１００はウエハを自重で位置決めする半導体製造装置であればよい。半導体製造装置１００は、研究室、実験室、又は量産工場のものを含む。 Embodiment 1.
FIG. 1 is a top view showing a semiconductor manufacturing apparatus according to the first embodiment. The semiconductor manufacturing apparatus 100 is a CVD (Chemical Vapor Deposition) apparatus that forms a thin film on a wafer. The semiconductor manufacturing apparatus 100 includes a transfer robot 1 having an arm structure, a load lock chamber 2, a loader 3 provided in the load lock chamber 2, a plurality of forks 5 attached to a rotating shaft, and a chamber constituting a processing chamber. 6. A stage 7 or the like in the chamber 6 on which a plurality of wafers 4 can be mounted is provided. Not limited to this, the semiconductor manufacturing apparatus 100 may be any semiconductor manufacturing apparatus that positions the wafer by its own weight. The semiconductor manufacturing apparatus 100 includes those in a laboratory, a laboratory, or a mass production factory.

搬送ロボット１がロードロックチャンバー２内のローダー３からウエハ４を取り出す。次に搬送ロボット１はウエハ４をチャンバ６内のフォーク５の上方に運ぶ。その後、フォーク５を上昇させることでウエハ４を持ち上げ、その状態でチャンバ６内のステージ７の処理領域８上まで回転移動し、フォーク５を降下させることでウエハ４をステージ７上に置く。円形の大きなステージ７の外周に沿って複数の処理領域８が設けられている。ステージ７は、真空吸着する吸着穴、位置決めピン、座操などのウエハ４を固定保持する機能を持たない。 The transfer robot 1 takes out the wafer 4 from the loader 3 in the load lock chamber 2. Next, the transfer robot 1 transports the wafer 4 above the fork 5 in the chamber 6. After that, the wafer 4 is lifted by raising the fork 5, and in that state, the wafer 4 is rotationally moved to the processing area 8 of the stage 7 in the chamber 6, and the wafer 4 is placed on the stage 7 by lowering the fork 5. A plurality of processing regions 8 are provided along the outer circumference of the large circular stage 7. The stage 7 does not have a function of fixing and holding the wafer 4 such as a suction hole for vacuum suction, a positioning pin, and a counterbore.

図２は、ウエハがステージに正しく置かれた状態でデポを行う様子を示す断面図である。ステージ７と上部電極９の間に電圧が印加されて、チャンバ６内で両者の間にプラズマ１０が発生する。ウエハ４がチャンバ６内で上部電極９の真下の処理領域８に配置されることで、ウエハ４の表面に均一に成膜することができる。図３は、ウエハの位置がずれた状態でデポを行う様子を示す断面図である。ウエハ４が上部電極９の真下の処理領域８からずれていると、デポ異常が発生する。 FIG. 2 is a cross-sectional view showing how the wafer is depoted while being correctly placed on the stage. A voltage is applied between the stage 7 and the upper electrode 9, and plasma 10 is generated between the two in the chamber 6. By arranging the wafer 4 in the processing region 8 directly below the upper electrode 9 in the chamber 6, a uniform film can be formed on the surface of the wafer 4. FIG. 3 is a cross-sectional view showing how the depot is performed with the wafers displaced. If the wafer 4 deviates from the processing region 8 directly below the upper electrode 9, a depot abnormality occurs.

図４は、実施の形態１に係る半導体製造装置のステージを示す上面図である。図５は図４のＩ−ＩＩに沿った斜視断面図である。ステージ７は例えばアルミからなる。ステージ７の上面に、フォーク５が入る２本のフォーク収容溝１１と、フォーク収容溝１１とは異なる位置に設けられフォーク収容溝１１に連通した２本のガス抜き溝１２とが設けられている。２本のフォーク収容溝１１は、処理領域８の外側から中央部に向かって延び、互いに平行に配置されている。ガス抜き溝１２は、この例では２本のフォーク収容溝１１の間においてフォーク収容溝１１に直交して互いに平行に配置されている。ガス抜き溝１２は、断面が三角形の凹部と、凹部に隣接して設けられステージ７の平坦面よりも突出した凸部とからなる凸凹構造を有する。ガス抜き溝１２はフォーク収容溝１１よりも幅が細く、深さは凸凹構造の高低差として３０〜５０μｍと浅い。 FIG. 4 is a top view showing a stage of the semiconductor manufacturing apparatus according to the first embodiment. FIG. 5 is a perspective sectional view taken along the line I-II of FIG. The stage 7 is made of, for example, aluminum. On the upper surface of the stage 7, two fork accommodating grooves 11 into which the fork 5 is inserted and two degassing grooves 12 provided at positions different from the fork accommodating groove 11 and communicating with the fork accommodating groove 11 are provided. .. The two fork accommodating grooves 11 extend from the outside of the processing region 8 toward the center and are arranged parallel to each other. In this example, the degassing groove 12 is arranged between the two fork accommodating grooves 11 orthogonal to the fork accommodating groove 11 and parallel to each other. The degassing groove 12 has an uneven structure including a concave portion having a triangular cross section and a convex portion provided adjacent to the concave portion and protruding from the flat surface of the stage 7. The degassing groove 12 is narrower than the fork accommodating groove 11 and has a shallow depth of 30 to 50 μm as a height difference of the uneven structure.

ウエハ４をステージ７に置く際にウエハ４の下面とステージ７の上面との間に存在するガス１３をガス抜き溝１２を介してフォーク収容溝１１内に逃がすことができる。加えて、ガス抜き溝１２が凸凹構造を有することで摩擦力も増す。これにより、ウエハ４の横滑りを抑制することができるため、ウエハ４の裏面の状態、重量、ステージの状態の良し悪しに左右されることなく、ステージ７に置くウエハ４の位置精度を向上させることができる。 When the wafer 4 is placed on the stage 7, the gas 13 existing between the lower surface of the wafer 4 and the upper surface of the stage 7 can be released into the fork accommodating groove 11 through the gas vent groove 12. In addition, the frictional force is increased because the degassing groove 12 has an uneven structure. As a result, the side slip of the wafer 4 can be suppressed, so that the positioning accuracy of the wafer 4 placed on the stage 7 can be improved regardless of the condition, weight, and the condition of the stage on the back surface of the wafer 4. Can be done.

また、ウエハ４をステージ７に置くために元々設けられているフォーク収容溝１１とそれに連通したガス抜き溝１２をガス１３の排出に用いることで、従来のようにステージ７の上面に多くの溝を形成しなくてもよい。従って、温度調整性能があまり低下しないため、ウエハ４の面内温度ばらつきを防ぐことができる。この結果、ウエハ４への成膜の面内均一性が安定する。 Further, by using the fork accommodating groove 11 originally provided for placing the wafer 4 on the stage 7 and the gas vent groove 12 communicating with the fork accommodating groove 11 for discharging the gas 13, many grooves are formed on the upper surface of the stage 7 as in the conventional case. Does not have to be formed. Therefore, since the temperature adjustment performance does not deteriorate so much, it is possible to prevent the in-plane temperature variation of the wafer 4. As a result, the in-plane uniformity of the film formation on the wafer 4 is stable.

また、ガス抜き溝１２をフォーク収容溝１１とは異なる位置に設けることで、フォーク収容溝１１以外の領域でもガス抜きを行うことができる。従って、ウエハ４の面内のガス抜きを瞬時に行ってウエハ４の横滑りを抑制することができる。そして、温度調整性能の低下を防ぐために、ガス抜き溝１２の幅をフォーク収容溝１１の幅よりも細くすることが好ましい。なお、ガス抜き溝１２の配置に関しては、フォーク収容溝１１に直交して配置させる必要は無く、ウエハ４の横滑り方向に応じて摩擦力が増える角度、形状、及び配置とすればよい。また、ガス抜き溝１２の両端をフォーク収容溝１１に繋げる必要は無く、少なくともその一端がフォーク収容溝１１と繋がっていればよい。 Further, by providing the degassing groove 12 at a position different from that of the fork accommodating groove 11, degassing can be performed in a region other than the fork accommodating groove 11. Therefore, the in-plane degassing of the wafer 4 can be instantaneously performed to suppress the side slip of the wafer 4. Then, in order to prevent deterioration of the temperature adjustment performance, it is preferable that the width of the degassing groove 12 is narrower than the width of the fork accommodating groove 11. Regarding the arrangement of the gas vent groove 12, it is not necessary to arrange the gas vent groove 12 orthogonally to the fork accommodating groove 11, and the angle, shape, and arrangement may be such that the frictional force increases according to the side slip direction of the wafer 4. Further, it is not necessary to connect both ends of the gas vent groove 12 to the fork accommodating groove 11, and at least one end thereof may be connected to the fork accommodating groove 11.

実施の形態２．
図６は、実施の形態２に係る半導体製造装置のステージを示す上面図である。図７は図６のＩＩＩ−ＩＶに沿った断面図である。ステージ７の上面に複数のガス抜き穴１４が設けられている。ガス抜き穴１４は、フォーク収容溝１１とは異なる位置に設けられ、フォーク収容溝１１に連通している。ここでは、ガス抜き穴１４はフォーク収容溝１１の延長線上に設けられている。 Embodiment 2.
FIG. 6 is a top view showing a stage of the semiconductor manufacturing apparatus according to the second embodiment. FIG. 7 is a cross-sectional view taken along the line III-IV of FIG. A plurality of degassing holes 14 are provided on the upper surface of the stage 7. The degassing hole 14 is provided at a position different from that of the fork accommodating groove 11 and communicates with the fork accommodating groove 11. Here, the gas vent hole 14 is provided on an extension line of the fork accommodating groove 11.

ウエハ４をステージ７に置く際にウエハ４の下面とステージ７の上面との間に存在するガス１３をガス抜き穴１４とフォーク収容溝１１を介して逃がすことができる。これにより、ウエハ４の横滑りを抑制することができるため、ウエハ４の裏面の状態、重量、ステージの状態の良し悪しに左右されることなく、ステージ７に置くウエハ４の位置精度を向上させることができる。 When the wafer 4 is placed on the stage 7, the gas 13 existing between the lower surface of the wafer 4 and the upper surface of the stage 7 can be released through the gas vent hole 14 and the fork accommodating groove 11. As a result, the side slip of the wafer 4 can be suppressed, so that the positioning accuracy of the wafer 4 placed on the stage 7 can be improved regardless of the condition, weight, and the condition of the stage on the back surface of the wafer 4. Can be done.

また、ウエハ４をステージ７に置くために元々設けられているフォーク収容溝１１とそれに連通したガス抜き穴１４をガス１３の排出に用いることで、従来のようにステージ７の上面に多くの溝を形成しなくてもよい。従って、温度調整性能があまり低下しないため、ウエハ４の面内温度ばらつきを防ぐことができる。この結果、ウエハ４への成膜の面内均一性が安定する。 Further, by using the fork accommodating groove 11 originally provided for placing the wafer 4 on the stage 7 and the gas vent hole 14 communicating with the fork accommodating groove 11 for discharging the gas 13, many grooves are formed on the upper surface of the stage 7 as in the conventional case. Does not have to be formed. Therefore, since the temperature adjustment performance does not deteriorate so much, it is possible to prevent the in-plane temperature variation of the wafer 4. As a result, the in-plane uniformity of the film formation on the wafer 4 is stable.

また、ステージ７の上面においてフォーク収容溝１１の周辺に、粗仕上げにより粗面構造領域１５が設けられている。これにより、鏡面仕上げの場合に比べて摩擦抵抗が大きくなるため、ウエハ４がステージ７上で横滑りし難くなる。粗面構造領域１５の具体的な表面粗さとしては、ガス抜き効果、横滑り防止、面内温度分布のばらつきとの関係を鑑みて、最大高さＲｍａｘを５０ａとすることが好ましい。 Further, on the upper surface of the stage 7, a rough surface structural region 15 is provided around the fork accommodating groove 11 by rough finishing. As a result, the frictional resistance becomes larger than in the case of mirror finishing, so that the wafer 4 is less likely to skid on the stage 7. As a specific surface roughness of the rough surface structure region 15, it is preferable to set the maximum height Rmax to 50a in consideration of the relationship between the degassing effect, the prevention of skidding, and the variation in the in-plane temperature distribution.

図８は、実施の形態２の変形例に係る半導体製造装置のステージを示す上面図である。図９は図８のＶ−ＶＩに沿った断面図である。ガス抜き穴１４と粗面構造領域１５がフォーク収容溝１１の周辺に設けられている。このようにガス抜き穴１４は加工が可能であればウエハ４の上面のどこに設けてもよい。また、ガス抜き穴１４をフォーク収容溝１１とは異なる位置に設けることで、フォーク収容溝１１以外の領域でもガス抜きを行うことができる。従って、ウエハ４の面内のガス抜きを瞬時に行ってウエハ４の横滑りを抑制することができる。 FIG. 8 is a top view showing a stage of the semiconductor manufacturing apparatus according to the modified example of the second embodiment. FIG. 9 is a cross-sectional view taken along the line V-VI of FIG. A degassing hole 14 and a rough surface structure region 15 are provided around the fork accommodating groove 11. As described above, the degassing hole 14 may be provided anywhere on the upper surface of the wafer 4 as long as it can be processed. Further, by providing the degassing hole 14 at a position different from that of the fork accommodating groove 11, degassing can be performed in a region other than the fork accommodating groove 11. Therefore, the in-plane degassing of the wafer 4 can be instantaneously performed to suppress the side slip of the wafer 4.

４ ウエハ、５ フォーク、７ ステージ、１１ フォーク収容溝、１２ ガス抜き溝、１４ ガス抜き穴、１５ 粗面構造領域 4 wafers, 5 forks, 7 stages, 11 fork accommodation grooves, 12 degassing grooves, 14 degassing holes, 15 rough surface structural areas

Claims (4)

ウエハを持ち上げて搬送するフォークと、
上面に前記ウエハが置かれるステージとを備え、
前記ステージの前記上面に、前記フォークが入るフォーク収容溝と、前記フォーク収容溝とは異なる位置に設けられ前記フォーク収容溝に連通したガス抜き溝とが設けられていることを特徴とする半導体製造装置。 A fork that lifts and conveys the wafer,
A stage on which the wafer is placed is provided on the upper surface.
A semiconductor manufacturing machine characterized in that a fork accommodating groove into which the fork is inserted and a degassing groove provided at a position different from the fork accommodating groove and communicating with the fork accommodating groove are provided on the upper surface of the stage. apparatus. 前記ガス抜き溝の幅は前記フォーク収容溝の幅より狭いことを特徴とする請求項１に記載の半導体製造装置。 The semiconductor manufacturing apparatus according to claim 1, wherein the width of the degassing groove is narrower than the width of the fork accommodating groove. ウエハを持ち上げて搬送するフォークと、
上面に前記ウエハが置かれるステージとを備え、
前記ステージの前記上面に、前記フォークが入るフォーク収容溝と、前記フォーク収容溝とは異なる位置に設けられ前記フォーク収容溝に連通した複数のガス抜き穴とが設けられていることを特徴とする半導体製造装置。 A fork that lifts and conveys the wafer,
A stage on which the wafer is placed is provided on the upper surface.
The upper surface of the stage is provided with a fork accommodating groove into which the fork enters and a plurality of degassing holes provided at positions different from the fork accommodating groove and communicating with the fork accommodating groove. Semiconductor manufacturing equipment. 前記ステージの前記上面に粗面構造領域が設けられていることを特徴とする請求項１〜３の何れか１項に記載の半導体製造装置。 The semiconductor manufacturing apparatus according to any one of claims 1 to 3, wherein a rough surface structural region is provided on the upper surface of the stage.
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JP2015088573A (en) * 2013-10-30 2015-05-07 株式会社日立ハイテクノロジーズ Plasma processing apparatus
JP2016201528A (en) * 2015-04-07 2016-12-01 株式会社Sumco Susceptor, vapor deposition apparatus, vapor deposition method and epitaxial silicon wafer
JP2018182289A (en) * 2017-04-18 2018-11-15 日新イオン機器株式会社 Electrostatic chuck

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5940524A (en) * 1982-08-31 1984-03-06 Toshiba Corp Cvd apparatus
JPH06260431A (en) * 1993-03-08 1994-09-16 Sony Corp Vacuum wafer treatment device
JPH116069A (en) * 1997-06-11 1999-01-12 Tokyo Electron Ltd Treating device and stage device
JP2002057209A (en) * 2000-06-01 2002-02-22 Tokyo Electron Ltd Single-wafer processing apparatus and single-wafer processing method
JP2015088573A (en) * 2013-10-30 2015-05-07 株式会社日立ハイテクノロジーズ Plasma processing apparatus
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