JP2020178096A - Inductor built-in substrate - Google Patents

Inductor built-in substrate Download PDF

Info

Publication number
JP2020178096A
JP2020178096A JP2019081007A JP2019081007A JP2020178096A JP 2020178096 A JP2020178096 A JP 2020178096A JP 2019081007 A JP2019081007 A JP 2019081007A JP 2019081007 A JP2019081007 A JP 2019081007A JP 2020178096 A JP2020178096 A JP 2020178096A
Authority
JP
Japan
Prior art keywords
hole
layer
conductor
resin
plating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019081007A
Other languages
Japanese (ja)
Other versions
JP7368693B2 (en
Inventor
児玉 博明
Hiroaki Kodama
博明 児玉
千朗 西脇
Senro Nishiwaki
千朗 西脇
和彦 倉信
Kazuhiko Kuranobu
和彦 倉信
浩彰 宇野
Hiroaki Uno
浩彰 宇野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP2019081007A priority Critical patent/JP7368693B2/en
Publication of JP2020178096A publication Critical patent/JP2020178096A/en
Application granted granted Critical
Publication of JP7368693B2 publication Critical patent/JP7368693B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

To provide a highly reliable inductor built-in substrate for a through-hole conductor.SOLUTION: In a first through-hole conductor 36B, a resin residue layer 19 on the surface of a first through hole 18b has an average thickness of 1 μm or less. Since the resin residue layer 19 has an average thickness of 1 μm or less, there is a break in the resin residue layer 19. An iron oxide filler 17 exposed from the surface of the first through hole 18b at the cut of the resin residue layer 19 comes into contact with a metal film forming the first through-hole conductor 36B.SELECTED DRAWING: Figure 6

Description

本発明は、インダクタを内蔵するインダクタ内蔵基板に関する。 The present invention relates to an inductor built-in substrate having an inductor built-in.

特許文献1は、配線基板に内蔵されるインダクタ部品の製造方法を開示している。特許文献1では、樹脂層内に磁性体を収容し、樹脂層内にスルーホール導体を設け、スルーホール導体と磁性体とが接触しないようにしている。 Patent Document 1 discloses a method for manufacturing an inductor component incorporated in a wiring board. In Patent Document 1, a magnetic material is housed in the resin layer, and a through-hole conductor is provided in the resin layer to prevent the through-hole conductor and the magnetic material from coming into contact with each other.

特開2016−197624JP 2016-197624

特許文献1では、樹脂層にスルーホール導体を配置するため、インダクタ部品の大きさに対して磁性体の割合が低くなり、インダクタンスを大きくすることが難しいと考えられる。一方、スルーホール導体と磁性体とを接触させた場合、スルーホール導体の信頼性が低下すると考えられる。 In Patent Document 1, since the through-hole conductor is arranged in the resin layer, the ratio of the magnetic material to the size of the inductor component is low, and it is considered difficult to increase the inductance. On the other hand, when the through-hole conductor is brought into contact with the magnetic material, the reliability of the through-hole conductor is considered to decrease.

本発明の目的は、スルーホール導体の信頼性の高いインダクタ内蔵基板を提供することである。 An object of the present invention is to provide a highly reliable inductor-embedded substrate for a through-hole conductor.

本発明に係るインダクタ内蔵基板は、開口が形成されたコア基板と、前記開口内に充填され、第1貫通孔を有する磁性体樹脂と、前記第1貫通孔に形成された金属膜から成る第1スルーホール導体と、を有する。前記磁性体樹脂は60重量%以上の酸化鉄フィラーを含有し、前記第1貫通孔の表面に平均厚みが0.01μm以上、1μm以下の樹脂残渣層が形成される。 The inductor-embedded substrate according to the present invention comprises a core substrate having an opening, a magnetic resin filled in the opening and having a first through hole, and a metal film formed in the first through hole. It has one through-hole conductor. The magnetic resin contains 60% by weight or more of an iron oxide filler, and a resin residue layer having an average thickness of 0.01 μm or more and 1 μm or less is formed on the surface of the first through hole.

本発明のインダクタ内蔵基板は、磁性体樹脂の第1貫通孔に直接金属膜からなる第1スルーホール導体を形成するため、インダクタ部品の磁性体樹脂の体積を大きくし、インダクタンスを大きくすることができる。磁性体樹脂は60重量%以上の酸化鉄フィラーを含有するため、伝熱性が高く、インダクタ内蔵基板の放熱性が高まる。第1貫通孔の表面の樹脂残渣層は、平均厚みが0.01μm以上、1μm以下であるため、第1貫通孔の表面から露出する酸化鉄フィラーが第1スルーホール導体を形成する金属膜と接し、第1スルーホール導体の信頼性が高くなる。 Since the inductor-embedded substrate of the present invention forms the first through-hole conductor made of a metal film directly in the first through hole of the magnetic resin, the volume of the magnetic resin of the inductor component can be increased and the inductance can be increased. it can. Since the magnetic resin contains 60% by weight or more of the iron oxide filler, the heat transfer property is high and the heat dissipation property of the inductor built-in substrate is enhanced. Since the resin residue layer on the surface of the first through hole has an average thickness of 0.01 μm or more and 1 μm or less, the iron oxide filler exposed from the surface of the first through hole forms a metal film forming the first through hole conductor. In contact with each other, the reliability of the first through-hole conductor is increased.

図1(A)は実施形態のインダクタ内蔵基板の断面図であり、図1(B)はスルーホールランドの平面図であり、図1(C)はインダクタ内蔵基板のコア基板の拡大図である。FIG. 1 (A) is a cross-sectional view of the inductor-embedded substrate of the embodiment, FIG. 1 (B) is a plan view of a through-hole land, and FIG. .. 実施形態に係るインダクタ内蔵基板の製造方法を示す工程図。The process chart which shows the manufacturing method of the inductor built-in substrate which concerns on embodiment. 実施形態に係るインダクタ内蔵基板の製造方法を示す工程図。The process chart which shows the manufacturing method of the inductor built-in substrate which concerns on embodiment. 実施形態に係るインダクタ内蔵基板の製造方法を示す工程図。The process chart which shows the manufacturing method of the inductor built-in substrate which concerns on embodiment. 実施形態に係るインダクタ内蔵基板の第1スルーホール導体の断面顕微鏡写真。A cross-sectional micrograph of the first through-hole conductor of the inductor-embedded substrate according to the embodiment. 実施形態に係るインダクタ内蔵基板の第1スルーホール導体の中央部の断面顕微鏡写真。A cross-sectional micrograph of the central portion of the first through-hole conductor of the inductor-embedded substrate according to the embodiment. 参考例に係るインダクタ内蔵基板の第1スルーホール導体の断面顕微鏡写真。A cross-sectional photomicrograph of the first through-hole conductor of the inductor-embedded substrate according to the reference example. 参考例に係るインダクタ内蔵基板の第1スルーホール導体の中央部の断面顕微鏡写真。A cross-sectional photomicrograph of the central portion of the first through-hole conductor of the inductor-built substrate according to the reference example.

図1(A)は、実施形態のインダクタを内蔵するインダクタ内蔵基板10の断面図を示す。インダクタ内蔵基板10は、第1面Fと第1面Fと反対側の第2面Sを有する絶縁性基材20と、絶縁性基材20の第1面F上の第1導体層(導体回路)58Fと、絶縁性基材20の第2面S上の第2導体層58Sと、第1導体層58Fと第2導体層58Sを接続しているスルーホール導体36とで形成されているコア基板30を有する。コア基板30は第1面Fと第1面Fと反対側の第2面Sを有する。コア基板30の第1面Fと絶縁性基材20の第1面Fは同じ面であり、コア基板30の第2面Sと絶縁性基材20の第2面Sは同じ面である。絶縁性基材20は、エポキシなどの樹脂と補強用のガラスクロス等の芯材14で形成されている。絶縁性基材20は、さらに、シリカ等の無機粒子を有しても良い。 FIG. 1A shows a cross-sectional view of an inductor built-in substrate 10 having an inductor of the embodiment built-in. The inductor-embedded substrate 10 includes an insulating base material 20 having a first surface F and a second surface S opposite to the first surface F, and a first conductor layer (conductor) on the first surface F of the insulating base material 20. Circuit) 58F, a second conductor layer 58S on the second surface S of the insulating base material 20, and a through-hole conductor 36 connecting the first conductor layer 58F and the second conductor layer 58S. It has a core substrate 30. The core substrate 30 has a first surface F and a second surface S opposite to the first surface F. The first surface F of the core substrate 30 and the first surface F of the insulating base material 20 are the same surface, and the second surface S of the core substrate 30 and the second surface S of the insulating base material 20 are the same surface. The insulating base material 20 is formed of a resin such as epoxy and a core material 14 such as a glass cloth for reinforcement. The insulating base material 20 may further have inorganic particles such as silica.

インダクタ内蔵基板10は、さらに、コア基板30の第1面F上に上側のビルドアップ層450Fを有する。上側のビルドアップ層450Fはコア基板30の第1面F上に形成されている絶縁層450Aと絶縁層450A上の導体層458Aと絶縁層450Aを貫通し第1導体層58Fと導体層458Aを接続しているビア導体460Aとを有する。上側のビルドアップ層450Fはさらに絶縁層450Aと導体層458A上の絶縁層450Cと絶縁層450C上の導体層458Cと絶縁層450Cを貫通し導体層458Aやビア導体460Aと導体層458Cとを接続するビア導体460Cを有する。 The inductor-embedded substrate 10 further has an upper build-up layer 450F on the first surface F of the core substrate 30. The upper build-up layer 450F penetrates the insulating layer 450A formed on the first surface F of the core substrate 30, the conductor layer 458A on the insulating layer 450A, and the insulating layer 450A, and passes through the first conductor layer 58F and the conductor layer 458A. It has a via conductor 460A connected to it. The upper build-up layer 450F further penetrates the insulating layer 450A, the insulating layer 450C on the conductor layer 458A, the conductor layer 458C on the insulating layer 450C, and the insulating layer 450C, and connects the conductor layer 458A, the via conductor 460A, and the conductor layer 458C. It has a via conductor 460C.

インダクタ内蔵基板10は、さらに、コア基板30の第2面S上に下側のビルドアップ層450Sを有する。下側のビルドアップ層450Sはコア基板30の第2面S上に形成されている絶縁層450Bと絶縁層450B上の導体層458Bと絶縁層450Bを貫通し第2導体層58Sと導体層458Bを接続しているビア導体460Bとを有する。下側のビルドアップ層450Sはさらに絶縁層450Bと導体層458B上の絶縁層450Dと絶縁層450D上の導体層458Dと絶縁層450Dを貫通し導体層458Bやビア導体460Bと導体層458Dとを接続するビア導体460Dを有する。 The inductor-embedded substrate 10 further has a lower build-up layer 450S on the second surface S of the core substrate 30. The lower build-up layer 450S penetrates the insulating layer 450B formed on the second surface S of the core substrate 30, the conductor layer 458B on the insulating layer 450B, and the insulating layer 450B, and the second conductor layer 58S and the conductor layer 458B. Has a via conductor 460B connecting the above. The lower build-up layer 450S further penetrates the insulating layer 450B, the insulating layer 450D on the conductor layer 458B, the conductor layer 458D on the insulating layer 450D, and the insulating layer 450D, and the conductor layer 458B, the via conductor 460B, and the conductor layer 458D. It has a via conductor 460D to connect.

実施形態のインダクタ内蔵基板は、さらに、上側のビルドアップ層450F上に開口471Fを有するソルダーレジスト層470Fと下側のビルドアップ層450S上に開口471Sを有するソルダーレジスト層470Sを有する。 The inductor-embedded substrate of the embodiment further has a solder resist layer 470F having an opening 471F on the upper build-up layer 450F and a solder resist layer 470S having an opening 471S on the lower build-up layer 450S.

ソルダーレジスト層470F、470Sの開口471F、471Sにより露出している導体層458C、458Dやビア導体460C、460Dの上面はパッドとして機能する。パッド上に、Ni/AuやNi/Pd/Au、Pd/Au、OSPから成る保護膜472が形成されている。その保護膜上に半田バンプ476F、476Sが形成されている。上側のビルドアップ層450F上に形成されている半田バンプ476Fを介して図示しないICチップがインダクタ内蔵基板10に搭載される。下側のビルドアップ層450S上に形成されている半田バンプ476Sを介してインダクタ内蔵基板10はマザーボードに搭載される。 The upper surfaces of the conductor layers 458C and 458D and the via conductors 460C and 460D exposed by the openings 471F and 471S of the solder resist layers 470F and 470S function as pads. A protective film 472 made of Ni / Au, Ni / Pd / Au, Pd / Au, and OSP is formed on the pad. Solder bumps 476F and 476S are formed on the protective film. An IC chip (not shown) is mounted on the inductor built-in substrate 10 via a solder bump 476F formed on the upper build-up layer 450F. The inductor built-in substrate 10 is mounted on the motherboard via the solder bumps 476S formed on the lower build-up layer 450S.

図1(C)は図1(A)中のコア基板30の一部を拡大して示す。コア基板30では、第1導体層58Fと第2導体層58Sとを接続するスルーホール導体36は、コア基板30を貫通する第2貫通孔20aに形成された第2スルーホール導体36Aと、コア基板30の開口20b内に充填された磁性体樹脂18の第1貫通孔18bに形成された第1スルーホール導体36Bとから成る。第2貫通孔20aの直径daと第1貫通孔18bの直径dbとはほぼ等しい。第2スルーホール導体36A、第1スルーホール導体36B内には樹脂充填剤16が充填され、スルーホールランド58FRは蓋めっきから成る。スルーホールランド58FRは、第2スルーホール導体36Aに形成された第2スルーホールランド58FRAと第1スルーホール導体36Bに形成された第1スルーホールランド58FRBとから成る。 FIG. 1 (C) shows an enlarged part of the core substrate 30 in FIG. 1 (A). In the core substrate 30, the through-hole conductor 36 connecting the first conductor layer 58F and the second conductor layer 58S is the second through-hole conductor 36A formed in the second through hole 20a penetrating the core substrate 30 and the core. It is composed of a first through-hole conductor 36B formed in the first through hole 18b of the magnetic resin 18 filled in the opening 20b of the substrate 30. The diameter da of the second through hole 20a and the diameter db of the first through hole 18b are substantially equal to each other. The second through-hole conductor 36A and the first through-hole conductor 36B are filled with the resin filler 16, and the through-hole land 58FR is made of lid plating. The through-hole land 58FR includes a second through-hole land 58FRA formed on the second through-hole conductor 36A and a first through-hole land 58FRB formed on the first through-hole conductor 36B.

図1(B)は、第2スルーホール導体36Aに形成された第2スルーホールランド58FRAと第1スルーホール導体36Bに形成された第1スルーホールランド58FRBとの平面図である。第2スルーホールランド58FRAは、第2スルーホール導体36Aと同心円状に形成され、第1スルーホールランド58FRBは、第1スルーホール導体36Bと同心円状に形成されている。第2スルーホールランド58FRAの直径Daと第1スルーホールランド58FRBの直径Dbとはほぼ等しい。第2スルーホールランド58FRAと第1スルーホールランド58FRBとは第1導体層(回路パターン)58Fにより接続されている。第1スルーホールランド58FRBの直径Dbは、磁性体樹脂18の充填された開口20bの直径DBよりも小径に形成されている。即ち、第1スルーホールランド58FRBは、磁性体樹脂18上から絶縁性基材20まで広がることが無い。 FIG. 1B is a plan view of a second through-hole land 58FRA formed on the second through-hole conductor 36A and a first through-hole land 58FRB formed on the first through-hole conductor 36B. The second through-hole land 58FRA is formed concentrically with the second through-hole conductor 36A, and the first through-hole land 58FRB is formed concentrically with the first through-hole conductor 36B. The diameter Da of the second through-hole land 58FRA and the diameter Db of the first through-hole land 58FRB are substantially equal to each other. The second through-hole land 58FRA and the first through-hole land 58FRB are connected by a first conductor layer (circuit pattern) 58F. The diameter Db of the first through-hole land 58FRB is formed to be smaller than the diameter DB of the opening 20b filled with the magnetic resin 18. That is, the first through-hole land 58FRB does not spread from the magnetic resin 18 to the insulating base material 20.

磁性体樹脂18は、酸化鉄フィラー(磁性粒子)とエポキシ等の樹脂を含む。磁性粒子として、酸化鉄(III)等の酸化鉄フィラーが挙げられる。磁性体樹脂中の酸化鉄フィラーの含有量は60重量%〜90重量%であることが好ましい。酸化鉄フィラーの粒子径は均一で無い方が、重量%を高め、透磁率及び伝熱性を高くできるため望ましい。 The magnetic resin 18 contains an iron oxide filler (magnetic particles) and a resin such as epoxy. Examples of the magnetic particles include iron oxide fillers such as iron (III) oxide. The content of the iron oxide filler in the magnetic resin is preferably 60% by weight to 90% by weight. It is desirable that the particle size of the iron oxide filler is not uniform because the weight% can be increased and the magnetic permeability and heat transfer property can be increased.

図1(C)に示されるように、コア基板30を貫通する第2貫通孔20aに形成された第2スルーホール導体36Aは、第2貫通孔20aに接触する。第2スルーホール導体36Aは、第2貫通孔20a上の第2無電解めっき膜32と、該第2無電解めっき膜32上の第2電解めっき膜34とから成る。磁性体樹脂18を貫通する第1貫通孔18bに形成された第1スルーホール導体36Bは、第1貫通孔18bに接触する。第1スルーホール導体36Bは、第1貫通孔18b上の第2無電解めっき膜32と、該第2無電解めっき膜32上の第2電解めっき膜34とから成る。第2スルーホール導体36Aを構成する第2無電解めっき膜32と第2電解めっき膜34との厚みtaは、第1スルーホール導体36Bを構成する第2無電解めっき膜32と第2電解めっき膜34との厚みtbよりも厚い。伝熱性の低い絶縁性基材20の第2貫通孔20aに形成された第2スルーホール導体36Aの厚みtaは、熱伝導性の高い磁性体樹脂18の第1貫通孔18bに形成された第1スルーホール導体36Bの厚みtbよりも厚くされることで、第2スルーホール導体36Aと第1スルーホール導体36Bとの放熱バランスが調整されている。 As shown in FIG. 1C, the second through-hole conductor 36A formed in the second through-hole 20a penetrating the core substrate 30 comes into contact with the second through-hole 20a. The second through-hole conductor 36A is composed of a second electroless plating film 32 on the second through hole 20a and a second electroless plating film 34 on the second electroless plating film 32. The first through-hole conductor 36B formed in the first through-hole 18b penetrating the magnetic resin 18 comes into contact with the first through-hole 18b. The first through-hole conductor 36B is composed of a second electroless plating film 32 on the first through hole 18b and a second electroless plating film 34 on the second electroless plating film 32. The thickness ta of the second electroless plating film 32 and the second electrolytic plating film 34 constituting the second through-hole conductor 36A is the second electroless plating film 32 and the second electrolytic plating forming the first through hole conductor 36B. It is thicker than the thickness tb with the film 34. The thickness ta of the second through-hole conductor 36A formed in the second through-hole 20a of the insulating base material 20 having low heat conductivity is the thickness ta formed in the first through-hole 18b of the magnetic resin 18 having high thermal conductivity. By making the thickness of the 1 through-hole conductor 36B thicker than tb, the heat dissipation balance between the second through-hole conductor 36A and the first through-hole conductor 36B is adjusted.

図5は、実施形態の第1スルーホール導体36Bの断面顕微鏡写真である。
中央のI字状の部分が第1スルーホール導体36B(第2無電解めっき膜32、第2電解めっき膜34)である。I字状の第1スルーホール導体36Bの左側が、磁性体樹脂18である。磁性体樹脂18に設けられた第1貫通孔18b上に第1スルーホール導体36Bが形成されている。I字状の第1スルーホール導体36Bの右側が樹脂充填剤16である。磁性体樹脂18中の丸い粒子は酸化鉄フィラー17である。樹脂充填剤16中の丸い粒子は無機フィラー21である。磁性体樹脂18の左側が絶縁性基材20で、磁性体樹脂18と絶縁性基材20との境が開口20bである。
FIG. 5 is a cross-sectional micrograph of the first through-hole conductor 36B of the embodiment.
The central I-shaped portion is the first through-hole conductor 36B (second electroless plating film 32, second electrolytic plating film 34). The left side of the I-shaped first through-hole conductor 36B is the magnetic resin 18. The first through-hole conductor 36B is formed on the first through hole 18b provided in the magnetic resin 18. The resin filler 16 is on the right side of the I-shaped first through-hole conductor 36B. The round particles in the magnetic resin 18 are iron oxide fillers 17. The round particles in the resin filler 16 are the inorganic filler 21. The left side of the magnetic resin 18 is the insulating base material 20, and the boundary between the magnetic resin 18 and the insulating base material 20 is the opening 20b.

図6は、図5中の矢印Aで指示した第1スルーホール導体36Bの中央部分の倍率を上げた断面顕微鏡写真である。第1スルーホール導体36Bと磁性体樹脂18との界面に存在する黒い部分が樹脂残渣層19である。樹脂残渣層19は、磁性体樹脂18に第1貫通孔18bをドリルで形成する際に、磁性体樹脂から分離した樹脂成分が、再度、磁性体樹脂側に付着した樹脂残渣である。一旦、分離して再付着しているため、磁性体樹脂から剥がれ易い。実施形態の第1スルーホール導体36Bでは、第1貫通孔18bの表面の樹脂残渣層19は、平均厚みが0.01μm以上、1μm以下である。樹脂残渣層19は、平均厚みが1μm以下であるため、樹脂残渣層19の切れ目が存在する。樹脂残渣層19の切れ目において第1貫通孔18bの表面から露出する酸化鉄フィラー17が第1スルーホール導体36Bを形成する金属膜と接し、第1スルーホール導体の信頼性が高くなる。なお、樹脂リッチ層の平均厚みが1μmを超えると、樹脂リッチ層がほぼ切れ目無く第1貫通孔の全面を覆うことになる。第1スルーホール導体の信頼性が低くなる。 FIG. 6 is a cross-sectional micrograph in which the magnification of the central portion of the first through-hole conductor 36B indicated by the arrow A in FIG. 5 is increased. The black portion existing at the interface between the first through-hole conductor 36B and the magnetic resin 18 is the resin residue layer 19. The resin residue layer 19 is a resin residue in which the resin component separated from the magnetic resin when the first through hole 18b is formed in the magnetic resin 18 with a drill is again attached to the magnetic resin side. Since it is once separated and reattached, it easily peels off from the magnetic resin. In the first through-hole conductor 36B of the embodiment, the resin residue layer 19 on the surface of the first through hole 18b has an average thickness of 0.01 μm or more and 1 μm or less. Since the resin residue layer 19 has an average thickness of 1 μm or less, there is a break in the resin residue layer 19. The iron oxide filler 17 exposed from the surface of the first through hole 18b at the cut of the resin residue layer 19 comes into contact with the metal film forming the first through hole conductor 36B, and the reliability of the first through hole conductor is improved. When the average thickness of the resin-rich layer exceeds 1 μm, the resin-rich layer covers the entire surface of the first through hole with almost no break. The reliability of the first through-hole conductor becomes low.

図7は、参考例の第1スルーホール導体36Bの断面顕微鏡写真である。
中央のI字状の部分が第1スルーホール導体36Bである。I字状の第1スルーホール導体36Bの右側が、磁性体樹脂18である。磁性体樹脂18に設けられた第1貫通孔18b上に第1スルーホール導体36Bが形成されている。I字状の第1スルーホール導体36Bの左側が樹脂充填剤16である。磁性体樹脂18中の丸い粒子は酸化鉄フィラー17である。樹脂充填剤16中の丸い粒子は無機フィラー21である。磁性体樹脂18の右側が絶縁性基材20で、磁性体樹脂18と絶縁性基材20との境が開口20bである。
FIG. 7 is a cross-sectional micrograph of the first through-hole conductor 36B of the reference example.
The central I-shaped portion is the first through-hole conductor 36B. The right side of the I-shaped first through-hole conductor 36B is the magnetic resin 18. The first through-hole conductor 36B is formed on the first through hole 18b provided in the magnetic resin 18. The left side of the I-shaped first through-hole conductor 36B is the resin filler 16. The round particles in the magnetic resin 18 are iron oxide fillers 17. The round particles in the resin filler 16 are the inorganic filler 21. The right side of the magnetic resin 18 is the insulating base material 20, and the boundary between the magnetic resin 18 and the insulating base material 20 is the opening 20b.

図8は、図7中の矢印Bで指示した第1スルーホール導体36Bの中央部分の倍率を上げた断面顕微鏡写真である。第1スルーホール導体36Bと磁性体樹脂18との界面に存在する黒い部分が樹脂残渣層19である。参考例の第1スルーホール導体36Bでは、第1貫通孔18bの表面の樹脂残渣層19は、平均厚みが1μm以上である。樹脂残渣層19は、平均厚みが1μm以上であるため、第1貫通孔18bの表面から露出する酸化鉄フィラー17と第1スルーホール導体36Bを形成する金属膜との間に切れ目無く樹脂残渣層19が介在する。参考例では、第1貫通孔18bから露出する酸化鉄フィラー17から樹脂残渣層19と共に第1スルーホール導体36Bを形成する金属膜が剥がれ易く、第1スルーホール導体の信頼性が低い。 FIG. 8 is a cross-sectional micrograph in which the magnification of the central portion of the first through-hole conductor 36B indicated by the arrow B in FIG. 7 is increased. The black portion existing at the interface between the first through-hole conductor 36B and the magnetic resin 18 is the resin residue layer 19. In the first through-hole conductor 36B of the reference example, the resin residue layer 19 on the surface of the first through hole 18b has an average thickness of 1 μm or more. Since the resin residue layer 19 has an average thickness of 1 μm or more, the resin residue layer has no break between the iron oxide filler 17 exposed from the surface of the first through hole 18b and the metal film forming the first through-hole conductor 36B. 19 intervenes. In the reference example, the metal film forming the first through-hole conductor 36B together with the resin residue layer 19 is easily peeled off from the iron oxide filler 17 exposed from the first through hole 18b, and the reliability of the first through-hole conductor is low.

図1(C)に示されるように、第2スルーホールランド58FRA及び絶縁性基材20上の第1導体層58Fは、最下層の銅箔22と、該銅箔22上の第1無電解めっき膜24mと、第1無電解めっき膜24m上の第1電解めっき膜24dと、第1電解めっき膜24d上の第2無電解めっき膜32と、第2無電解めっき膜32上の第2電解めっき膜34と、該第2電解めっき膜34上の第3無電解めっき膜35と、該第3無電解めっき膜35上の第3電解めっき膜37とから成る。第1スルーホールランド58FRB及び磁性体樹脂18上の第1導体層58Fは、最下層の第1無電解めっき膜24mと、第1無電解めっき膜24m上の第1電解めっき膜24dと、第1電解めっき膜24d上の第2無電解めっき膜32と、第2無電解めっき膜32上の第2電解めっき膜34と、該第2電解めっき膜34上の第3無電解めっき膜35と、該第3無電解めっき膜35上の第3電解めっき膜37とから成る。第1無電解めっき膜24mと第1電解めっき膜24dとはシールド層24を構成する。第2スルーホールランド58FRA及び絶縁性基材20上の第1導体層58Fの厚みtAは、第1スルーホールランド58FRB及び磁性体樹脂18上の第1導体層58Fの厚みtBよりも、銅箔22の厚み分厚い。伝熱性の低い絶縁性基材20上に形成された第2スルーホールランド58FRAの厚みtAは、熱伝導性の高い磁性体樹脂18上に形成された第1スルーホールランド58FRBの厚みtBよりも熱伝導率の高い銅箔22分厚くされることで、第2スルーホール導体36Aと第1スルーホール導体36Bとの放熱バランスが調整されている。 As shown in FIG. 1 (C), the second through hole land 58FRA and the first conductor layer 58F on the insulating base material 20 are the lowest layer copper foil 22 and the first electroplating on the copper foil 22. The plating film 24m, the first electrolytic plating film 24d on the first electrolytic plating film 24m, the second electrolytic plating film 32 on the first electrolytic plating film 24d, and the second on the second electrolytic plating film 32. It is composed of an electrolytic plating film 34, a third electrolytic plating film 35 on the second electrolytic plating film 34, and a third electrolytic plating film 37 on the third electrolytic plating film 35. The first through hole land 58FRB and the first conductor layer 58F on the magnetic resin 18 are the first electroless plating film 24m of the lowest layer, the first electroless plating film 24d on the first electroless plating film 24m, and the first. 1 The second electroless plating film 32 on the electrolytic plating film 24d, the second electroless plating film 34 on the second electroless plating film 32, and the third electroless plating film 35 on the second electroplating film 34. It is composed of a third electrolytic plating film 37 on the third electroless plating film 35. The first electroless plating film 24m and the first electrolytic plating film 24d form a shield layer 24. The thickness tA of the first conductor layer 58F on the second through-hole land 58FRA and the insulating base material 20 is larger than the thickness tB of the first conductor layer 58F on the first through-hole land 58FRB and the magnetic resin 18. 22 is thick. The thickness tA of the second through-hole land 58FRA formed on the insulating base material 20 having low thermal conductivity is larger than the thickness tB of the first through-hole land 58FRB formed on the magnetic resin 18 having high thermal conductivity. By thickening the copper foil having high thermal conductivity by 22 minutes, the heat dissipation balance between the second through-hole conductor 36A and the first through-hole conductor 36B is adjusted.

実施形態のコア基板30は、図1(A)中に示される磁性体樹脂18に形成された第1スルーホール導体36Bを介して接続される第1導体層58F(接続パターン58FL)、第2導体層58S(接続パターン58SL)とは、ヘリカル状(コア基板の表裏面に対して平行方向の軸線上に沿って螺旋状)に配置され、第1スルーホール導体36Bと共にインダクタ59を形成する。 The core substrate 30 of the embodiment has a first conductor layer 58F (connection pattern 58FL) and a second conductor layer 58F (connection pattern 58FL) connected via a first through-hole conductor 36B formed on the magnetic resin 18 shown in FIG. 1 (A). The conductor layer 58S (connection pattern 58SL) is arranged in a helical shape (spiral along an axis parallel to the front and back surfaces of the core substrate), and forms an inductor 59 together with the first through-hole conductor 36B.

実施形態のインダクタ内蔵基板10は、コア基板30の表面に第1導体層58Fと第2導体層58Sとが形成され、第1導体層58Fと第2導体層58Sとを接続する第1スルーホール導体36Bは、磁性体樹脂18を貫通する第1貫通孔18bに直接形成されている。このため、インダクタ内蔵基板10中の磁性体の割合が大きくなり、インダクタンスを大きくすることができる。 In the inductor-embedded substrate 10 of the embodiment, the first conductor layer 58F and the second conductor layer 58S are formed on the surface of the core substrate 30, and the first through hole connecting the first conductor layer 58F and the second conductor layer 58S. The conductor 36B is directly formed in the first through hole 18b that penetrates the magnetic resin 18. Therefore, the proportion of the magnetic material in the inductor built-in substrate 10 increases, and the inductance can be increased.

[実施形態のインダクタ内蔵基板の製造方法]
図2〜図4に実施形態のインダクタ内蔵基板の製造方法が示される。
絶縁性基材20の両面に銅箔22の積層された銅張り積層板から成る基板20zが準備される(図2(A))。絶縁性基材20に磁性体樹脂充填用の開口20bが形成される(図2(B))。開口20b内に60重量%〜90重量%の酸化鉄フィラー(磁性粒子)とエポキシ樹脂からなる樹脂ペーストが真空印刷される。樹脂ペーストが、樹脂ペーストの粘度が常温の2倍以下となる温度で仮硬化(半硬化)され仮硬化磁性体樹脂18βが形成される(図2(C))。
[Manufacturing method of the inductor built-in substrate of the embodiment]
2 to 4 show a method of manufacturing the inductor-embedded substrate of the embodiment.
A substrate 20z made of a copper-clad laminate in which copper foil 22 is laminated on both sides of the insulating base material 20 is prepared (FIG. 2 (A)). An opening 20b for filling the magnetic resin is formed in the insulating base material 20 (FIG. 2B). A resin paste composed of 60% by weight to 90% by weight of iron oxide filler (magnetic particles) and epoxy resin is vacuum-printed in the opening 20b. The resin paste is temporarily cured (semi-cured) at a temperature at which the viscosity of the resin paste is twice or less the room temperature to form the temporarily cured magnetic resin 18β (FIG. 2 (C)).

絶縁性基材20の表面、開口20bから露出する仮硬化磁性体樹脂18βの表面に無電解めっき処理で第1無電解めっき膜24mと、電解めっき処理で第1電解めっき膜24dが形成される(図2(D))。第1無電解めっき膜24mと第1電解めっき膜24dとはシールド層24を構成する。 A first electroless plating film 24m is formed by electroless plating treatment and a first electrolytic plating film 24d is formed by electroplating treatment on the surface of the insulating base material 20 and the surface of the temporarily cured magnetic resin 18β exposed from the opening 20b. (Fig. 2 (D)). The first electroless plating film 24m and the first electrolytic plating film 24d form a shield layer 24.

絶縁性基材20にドリル加工で第2貫通孔20aが形成される(図2(E))。この後、薬液により第2貫通孔20aがデスミア処理され、第2貫通孔20aの側壁に付着した樹脂残渣から成る樹脂リッチ層が除去される。樹脂リッチ層の平均厚みが0.5μm以下にされる。デスミア処理の際に、第1無電解めっき膜24mと第1電解めっき膜24dとから成るシールド層24で覆われた仮硬化磁性体樹脂18βは、薬液の影響を受けない。仮硬化磁性体樹脂18βの表面の酸化鉄フィラーは、デスミア処理の影響を受けない。 A second through hole 20a is formed in the insulating base material 20 by drilling (FIG. 2 (E)). After that, the second through hole 20a is desmeared with the chemical solution, and the resin rich layer composed of the resin residue adhering to the side wall of the second through hole 20a is removed. The average thickness of the resin-rich layer is set to 0.5 μm or less. During the desmear treatment, the temporarily cured magnetic resin 18β covered with the shield layer 24 composed of the first electroless plating film 24m and the first electrolytic plating film 24d is not affected by the chemical solution. The iron oxide filler on the surface of the false-cured magnetic resin 18β is not affected by the desmear treatment.

仮硬化磁性体樹脂18βにドリル加工で第1貫通孔18bが形成される。ドリル加工には、絶縁性基材20に第2貫通孔20aを形成した同じドリルが用いられる。ドリル回転数を下げることで、第1貫通孔18bの表面に付着する樹脂リッチ層(樹脂残渣)の平均厚みが薄くされる。この実施形態では、60重量%〜90重量%の酸化鉄フィラーを含むため、本硬化後の孔開けは容易ではないが、本硬化前に形成するため、貫通孔を容易に形成することができる。仮硬化状態の仮硬化磁性基材の磁性材層を加熱して含まれる樹脂を架橋させ、本硬化状態にして磁性体樹脂18が形成される(図3(A))。ここでは、150゜C〜190゜Cで1時間加熱する。高圧水洗により、孔開け時の加工スミアが取り除かれる(図3(B))。通常、デスミアはアルカリ性薬剤で行われるが、アルカリ性薬剤は樹脂を膨潤・剥離する過程で磁性体樹脂18に含まれる酸化鉄フィラーを脱落させる恐れがあるため、ここでは高圧水洗が行われる。更に、O2プラズマを用いるドライデスミアで、図6に示されたように第1貫通孔18bの表面の樹脂残渣層19は、平均厚み1μm以下にされる。ここで、ドライデスミアを用いても、樹脂残渣層19の平均厚みを0.01μm未満にすることはできない。第1貫通孔18bの表面の樹脂残渣層19の平均厚みは、薬液処理で樹脂リッチ層が除去される第2貫通孔20aの表面の樹脂リッチ層の平均厚みよりも厚い。絶縁性基材20、磁性体樹脂18の表面の第1電解めっき膜24d上、第2貫通孔20a、第1貫通孔18bの表面に、無電解めっき処理で第2無電解めっき膜32と、電解めっき処理で第2電解めっき膜34が形成される。第2無電解めっき膜32と第2電解めっき膜34とで、第2貫通孔20aに第2スルーホール導体36Aが、第1貫通孔18bに第1スルーホール導体36Bが形成される(図3(C))。 The first through hole 18b is formed in the temporarily cured magnetic resin 18β by drilling. For drilling, the same drill in which the second through hole 20a is formed in the insulating base material 20 is used. By lowering the drill rotation speed, the average thickness of the resin-rich layer (resin residue) adhering to the surface of the first through hole 18b is reduced. In this embodiment, since 60% by weight to 90% by weight of the iron oxide filler is contained, it is not easy to make holes after the main curing, but since it is formed before the main curing, through holes can be easily formed. .. The magnetic material layer of the temporarily cured magnetic base material in the temporarily cured state is heated to crosslink the resin contained therein, and the magnetic resin 18 is formed in the main cured state (FIG. 3 (A)). Here, it is heated at 150 ° C to 190 ° C for 1 hour. High-pressure water washing removes processed smear during drilling (Fig. 3 (B)). Normally, desmear is performed with an alkaline chemical, but since the alkaline chemical may cause the iron oxide filler contained in the magnetic resin 18 to fall off in the process of swelling and peeling the resin, high-pressure water washing is performed here. Further, in the dry desmear using O2 plasma, the resin residue layer 19 on the surface of the first through hole 18b is made to have an average thickness of 1 μm or less as shown in FIG. Here, even if dry desmear is used, the average thickness of the resin residue layer 19 cannot be less than 0.01 μm. The average thickness of the resin residue layer 19 on the surface of the first through hole 18b is thicker than the average thickness of the resin rich layer on the surface of the second through hole 20a from which the resin rich layer is removed by the chemical treatment. On the surface of the insulating base material 20 and the magnetic resin 18 on the first electrolytic plating film 24d, on the surfaces of the second through holes 20a and the first through holes 18b, the second electroless plating film 32 was formed by electroless plating. The second electroplating film 34 is formed by the electroplating treatment. The second electroless plating film 32 and the second electrolytic plating film 34 form a second through-hole conductor 36A in the second through hole 20a and a first through-hole conductor 36B in the first through hole 18b (FIG. 3). (C)).

第2貫通孔20aに形成された第2スルーホール導体36A内、第1貫通孔18bに形成された第1スルーホール導体36B内に樹脂充填剤16が充填され、絶縁性基材20の表面が研磨される(図3(D))。第2電解めっき膜34上、及び、樹脂充填剤16の露出面に無電解めっきにより第3無電解めっき膜35が形成され、第3無電解めっき膜35上に第3電解めっき膜37が形成される(図4(A))。第3電解めっき膜37上に所定パターンのエッチングレジスト54が形成される(図4(B))。 The resin filler 16 is filled in the second through-hole conductor 36A formed in the second through-hole 20a and the first through-hole conductor 36B formed in the first through-hole 18b, and the surface of the insulating base material 20 is formed. It is polished (FIG. 3 (D)). A third electroless plating film 35 is formed on the second electrolytic plating film 34 and on the exposed surface of the resin filler 16 by electroless plating, and a third electrolytic plating film 37 is formed on the third electroless plating film 35. (Fig. 4 (A)). A predetermined pattern of etching resist 54 is formed on the third electrolytic plating film 37 (FIG. 4 (B)).

エッチングレジスト54から露出する第3電解めっき膜37、第3無電解めっき膜35、第2電解めっき膜34、第2無電解めっき膜32、第1電解めっき膜24d、第1無電解めっき膜24m、銅箔22が除去された後、エッチングレジストが除去され、第1導体層58F、第2導体層58Sが形成され、コア基板30が完成する(図4(C))。絶縁性基材20上の第1導体層58F、第2導体層58S、第2スルーホール導体36Aの第1面F側の第2スルーホールランド58FRA及び第2面S側の第2スルーホールランド58SRAは、最下層の銅箔22と、該銅箔22上の第1無電解めっき膜24mと、第1無電解めっき膜24m上の第1電解めっき膜24dと、第1電解めっき膜24d上の第2無電解めっき膜32と、第2無電解めっき膜32上の第2電解めっき膜34と、該第2電解めっき膜34上の第3無電解めっき膜35と、該第3無電解めっき膜35上の第3電解めっき膜37とから成る。磁性体樹脂18上の第1導体層58F、第2導体層58S、第1スルーホール導体36Bの第1面F側の第1スルーホールランド58FRB及び第2面S側の第1スルーホールランド58SRBは、第1無電解めっき膜24mと、第1無電解めっき膜24m上の第1電解めっき膜24dと、第1電解めっき膜24d上の第2無電解めっき膜32と、第2無電解めっき膜32上の第2電解めっき膜34と、該第2電解めっき膜34上の第3無電解めっき膜35と、該第3無電解めっき膜35上の第3電解めっき膜37とから成る。 The third electrolytic plating film 37, the third electrolytic plating film 35, the second electrolytic plating film 34, the second electrolytic plating film 32, the first electrolytic plating film 24d, and the first electrolytic plating film 24m exposed from the etching resist 54. After the copper foil 22 is removed, the etching resist is removed, the first conductor layer 58F and the second conductor layer 58S are formed, and the core substrate 30 is completed (FIG. 4 (C)). The first conductor layer 58F, the second conductor layer 58S, and the second through hole conductor 36A on the insulating base material 20 are the second through hole land 58FRA on the first surface F side and the second through hole land on the second surface S side. The 58SRA has a copper foil 22 as a lowermost layer, a first electroplating film 24m on the copper foil 22, a first electroplating film 24d on the first electroplating film 24m, and a first electroplating film 24d. The second electroplating film 32, the second electroplating film 34 on the second electroplating film 32, the third electroplating film 35 on the second electroplating film 34, and the third electroplating film 35. It is composed of a third electrolytic plating film 37 on the plating film 35. The first through hole land 58FRB on the first surface F side and the first through hole land 58SRB on the second surface S side of the first conductor layer 58F, the second conductor layer 58S, and the first through hole conductor 36B on the magnetic resin 18. Is a first electroless plating film 24m, a first electroless plating film 24d on the first electroless plating film 24m, a second electroless plating film 32 on the first electroplating film 24d, and a second electroless plating. It is composed of a second electroplating film 34 on the film 32, a third electroless plating film 35 on the second electroplating film 34, and a third electroplating film 37 on the third electroless plating film 35.

コア基板30上に公知の製造方法により、上側のビルドアップ層450F、下側のビルドアップ層450S、ソルダーレジスト層470F、470S、半田バンプ476F、476Sが形成される(図1(A))。 An upper build-up layer 450F, a lower build-up layer 450S, a solder resist layer 470F, 470S, and solder bumps 476F and 476S are formed on the core substrate 30 by a known manufacturing method (FIG. 1 (A)).

実施形態のインダクタ内蔵基板の製造方法では、磁性体樹脂18の第1貫通孔18bに第2無電解めっき膜32、第2電解めっき膜34からなる第1スルーホール導体36Bを形成するため、インダクタ内蔵基板10の磁性体樹脂18の体積を大きくし、インダクタンスを大きくすることができる。磁性体樹脂18上に第1スルーホール導体36Bが直接設けられるが、樹脂リッチ層の平均厚みが1μm以下であるため、第1スルーホール導体の信頼性が低下しない。 In the method for manufacturing an inductor-embedded substrate of the embodiment, an inductor is formed in order to form a first through-hole conductor 36B composed of a second electroless plating film 32 and a second electrolytic plating film 34 in the first through hole 18b of the magnetic resin 18. The volume of the magnetic resin 18 of the built-in substrate 10 can be increased to increase the inductance. Although the first through-hole conductor 36B is directly provided on the magnetic resin 18, the reliability of the first through-hole conductor does not decrease because the average thickness of the resin-rich layer is 1 μm or less.

10 インダクタ内蔵基板
18 磁性体樹脂
18b 第1貫通孔
19 樹脂残渣層
20 コア基板
20a 第1貫通孔
20a 開口
22 銅箔
30 コア基板
36A 第2スルーホール導体
36B 第1スルーホール導体
10 Inductor built-in substrate 18 Magnetic resin 18b 1st through hole 19 Resin residue layer 20 Core substrate 20a 1st through hole 20a Opening 22 Copper foil 30 Core substrate 36A 2nd through hole conductor 36B 1st through hole conductor

Claims (5)

開口が形成されたコア基板と、
前記開口内に充填され、第1貫通孔を有する磁性体樹脂と、
前記第1貫通孔に形成された金属膜から成る第1スルーホール導体と、を有するインダクタ内蔵基板であって、
前記磁性体樹脂は60重量%以上の酸化鉄フィラーを含有し、
前記第1貫通孔の表面に平均厚みが0.01μm以上、1μm以下の樹脂残渣層が形成される。
The core substrate with the openings formed and
A magnetic resin filled in the opening and having a first through hole,
An inductor-embedded substrate having a first through-hole conductor made of a metal film formed in the first through hole.
The magnetic resin contains 60% by weight or more of an iron oxide filler and contains
A resin residue layer having an average thickness of 0.01 μm or more and 1 μm or less is formed on the surface of the first through hole.
請求項1のインダクタ内蔵基板であって、
さらに、前記コア基板に形成された第2貫通孔と、前記第2貫通孔に形成された金属膜から成る第2スルーホール導体を有する。
The board with a built-in inductor according to claim 1.
Further, it has a second through-hole conductor formed in the core substrate and a second through-hole conductor made of a metal film formed in the second through hole.
請求項2のインダクタ内蔵基板であって、
前記第2貫通孔の表面に樹脂残渣層が形成され、
前記第1貫通孔の前記樹脂残渣層の厚みは、前記第2貫通孔の前記樹脂残渣層の厚みよりも厚い。
The board with a built-in inductor according to claim 2.
A resin residue layer is formed on the surface of the second through hole,
The thickness of the resin residue layer of the first through hole is thicker than the thickness of the resin residue layer of the second through hole.
請求項3のインダクタ内蔵基板であって、
前記第2貫通孔の表面は、薬液処理で樹脂残渣層の厚みが低減され、
前記第1貫通孔の表面は、ドライデスミア処理で樹脂残渣層の厚みが低減されている。
The substrate with a built-in inductor according to claim 3.
The surface of the second through hole is treated with a chemical solution to reduce the thickness of the resin residue layer.
The thickness of the resin residue layer on the surface of the first through hole is reduced by the dry desmear treatment.
請求項1〜請求項4のいずれか1のインダクタ内蔵基板であって、
前記第1貫通孔の表面の前記樹脂残渣層の切れ目から露出する酸化鉄フィラーは、前記第1貫通孔に形成される金属膜と接している。
A substrate with a built-in inductor according to any one of claims 1 to 4.
The iron oxide filler exposed from the cut of the resin residue layer on the surface of the first through hole is in contact with the metal film formed in the first through hole.
JP2019081007A 2019-04-22 2019-04-22 Inductor built-in board Active JP7368693B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019081007A JP7368693B2 (en) 2019-04-22 2019-04-22 Inductor built-in board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019081007A JP7368693B2 (en) 2019-04-22 2019-04-22 Inductor built-in board

Publications (2)

Publication Number Publication Date
JP2020178096A true JP2020178096A (en) 2020-10-29
JP7368693B2 JP7368693B2 (en) 2023-10-25

Family

ID=72936218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019081007A Active JP7368693B2 (en) 2019-04-22 2019-04-22 Inductor built-in board

Country Status (1)

Country Link
JP (1) JP7368693B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007129526A1 (en) * 2006-05-08 2007-11-15 Ibiden Co., Ltd. Inductor and electric power source using same
WO2018194099A1 (en) * 2017-04-19 2018-10-25 味の素株式会社 Resin composition

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007129526A1 (en) * 2006-05-08 2007-11-15 Ibiden Co., Ltd. Inductor and electric power source using same
WO2018194099A1 (en) * 2017-04-19 2018-10-25 味の素株式会社 Resin composition

Also Published As

Publication number Publication date
JP7368693B2 (en) 2023-10-25

Similar Documents

Publication Publication Date Title
JP2021086856A (en) Inductor built-in board and manufacturing method thereof
JP2020178005A (en) Inductor built-in substrate
JP2019220504A (en) Inductor built-in substrate and manufacturing method of the same
US8541695B2 (en) Wiring board and method for manufacturing the same
JP2021097129A (en) Inductor built-in substrate
JP2015018979A (en) Printed wiring board
US20210195748A1 (en) Inductor built-in substrate
US20200335258A1 (en) Inductor built-in substrate
US11291118B2 (en) Inductor built-in substrate
JP2020178004A (en) Inductor built-in substrate
JP2020178007A (en) Manufacturing method of inductor built-in substrate
JP2015060981A (en) Printed wiring board
KR20150065029A (en) Printed circuit board, manufacturing method thereof and semiconductor package
JP7368693B2 (en) Inductor built-in board
JP2021097130A (en) Inductor built-in substrate and manufacturing method thereof
JP2020178095A (en) Inductor built-in substrate and manufacturing method thereof
JP2019129278A (en) Manufacturing method of inductor component, the inductor component, and wiring board with built-in component
JP2022108350A (en) Manufacturing method of inductor built-in substrate
JP2020178097A (en) Manufacturing method of inductor built-in substrate
JP2021097128A (en) Inductor built-in substrate
JP2021150435A (en) Inductor built-in substrate
JP2021150436A (en) Inductor built-in substrate
JP2021150437A (en) Inductor built-in substrate
KR101156854B1 (en) Substrate for a semiconductor package and manufacturing method thereof
JP2002043755A (en) Printed circuit board and manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220323

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20230216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230307

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230407

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20230711

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230713

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20230724

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230912

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230925

R150 Certificate of patent or registration of utility model

Ref document number: 7368693

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150