JP2020161312A - Multi-core cable and multi-core cable producing method - Google Patents

Abstract

To provide a multi-core cable and a multi-core cable producing method, in which a plurality of differential signal lines are stacked in a plurality of layers so as to suppress deterioration of signal transmission characteristics even when the differential signal lines are compressed in the stacking direction.SOLUTION: A multi-core cable 1 comprises a plurality of differential signal lines 2 in which an insulator 22 covering a pair of core wires 21, 21 is covered with a shield conductor 23, and a substrate 5 having a plurality of electrodes 51. The pair of core wires 21, 21 are connected to electrodes 52. The plurality of differential signal lines 2 are arranged in parallel with each other and are stacked in a plurality of layers including a first layer 2A in contact with the substrate 5 and a second layer 2B overlapping the first layer 2A. The plurality of differential signal lines 2 in the first layer 2A and the plurality of differential signal lines 2 in the second layer 2B are compressed in the stacking direction at a plurality of first and second compression sites 201 and 202 aligned in the longitudinal direction so as to plastically deform the insulator 22. An uncompressed part 200 having a predetermined width W0 is provided between the first and second compressed sites 201 and 202.SELECTED DRAWING: Figure 2

Description

本発明は、複数の差動信号線のそれぞれの心線が基板の電極に接続された多芯ケーブル及びその製造方法に関する。 The present invention relates to a multi-core cable in which the core wires of a plurality of differential signal lines are connected to electrodes on a substrate, and a method for manufacturing the same.

従来、複数の差動信号線のそれぞれの心線が基板の電極に接続された多芯ケーブルとして、特許文献１に記載のものが知られている。 Conventionally, a multi-core cable in which each core wire of a plurality of differential signal lines is connected to an electrode of a substrate is known as described in Patent Document 1.

特許文献１に記載の多芯ケーブル（アクティブモジュールケーブル）は、複数の差動信号伝送用ケーブルを内蔵したケーブルと、ケーブルの両端に設けられたコネクタと、コネクタに内蔵された基板とを備えている。基板は、接続対象の機器と差動信号伝送用ケーブルとを電気的に接続するためのものであり、差動信号伝送用ケーブルの芯線を接続するための複数の芯線パッドと、機器と電気的に接触するための複数の電極と、芯線パッドと電極とを接続する複数の送信側伝送路及び受信側伝送路とを有している。特許文献１に示された構成例では、基板の両面にそれぞれ４本の差動信号伝送用ケーブルが配置され、これらの差動信号伝送用ケーブルが基板の長手方向に沿って互いに平行に並んでいる。 The multi-core cable (active module cable) described in Patent Document 1 includes a cable incorporating a plurality of differential signal transmission cables, connectors provided at both ends of the cable, and a board incorporated in the connectors. There is. The board is for electrically connecting the device to be connected and the differential signal transmission cable, and a plurality of core wire pads for connecting the core wires of the differential signal transmission cable, and the device and the electrical wire. It has a plurality of electrodes for contacting the wire, and a plurality of transmission-side transmission lines and reception-side transmission lines for connecting the core wire pad and the electrodes. In the configuration example shown in Patent Document 1, four differential signal transmission cables are arranged on both sides of the substrate, and these differential signal transmission cables are arranged parallel to each other along the longitudinal direction of the substrate. There is.

特開２０１９−１６８９９号公報Japanese Unexamined Patent Publication No. 2019-16899

近年のコンピュータや通信機器の処理速度や通信速度のさらなる高速化により、多芯ケーブルにおいても差動信号線の多芯化及び高密度化が要請されている。この要請に対応するため、複数の差動信号線を基板の厚み方向に重ねて多層化することが考えられるが、例えばコネクタサイズの規格等による寸法の制約により、複数の差動信号線を積層方向に圧縮して変形させる必要が生じる場合がある。この場合、差動信号線において一対の心線を被覆する絶縁体の形状や、絶縁体を覆うシールド導体の形状が変わってしまうため、信号の伝送特性が劣化してしまうおそれがある。 In recent years, the processing speed and communication speed of computers and communication devices have been further increased, and there is a demand for multi-core and high-density differential signal lines even in multi-core cables. In order to meet this demand, it is conceivable to stack multiple differential signal lines in the thickness direction of the substrate to form multiple layers. However, due to dimensional restrictions such as connector size standards, multiple differential signal lines are stacked. It may be necessary to compress and deform in the direction. In this case, since the shape of the insulator covering the pair of core wires and the shape of the shield conductor covering the insulator change in the differential signal line, the signal transmission characteristics may be deteriorated.

そこで、本発明は、複数の差動信号線を複数層に積層し、これらの差動信号線を積層方向に圧縮した場合でも、信号の伝送特性の劣化を抑制することが可能な多芯ケーブル及び多芯ケーブルの製造方法を提供することを目的とする。 Therefore, the present invention is a multi-core cable capable of suppressing deterioration of signal transmission characteristics even when a plurality of differential signal lines are stacked in a plurality of layers and these differential signal lines are compressed in the stacking direction. And a method for manufacturing a multi-core cable.

本発明は、上記の目的を達成するため、一対の心線を被覆する絶縁体をシールド導体で覆ってなる複数の差動信号線と、複数の電極を有する基板とを備え、前記複数の差動信号線のそれぞれの長手方向の端部において前記絶縁体から露出した前記一対の心線が前記電極に接続された多芯ケーブルであって、前記複数の差動信号線は、互いに平行に配置され、かつ前記基板に接する第１層と前記第１層に重なる第２層とを含む複数層に積層されており、前記第１層の前記複数の差動信号線と前記第２層の前記複数の差動信号線とが、前記長手方向に並ぶ複数の圧縮箇所で積層方向に圧縮されて前記絶縁体が塑性変形しており、前記複数の圧縮箇所の間に所定の間隙が設けられている、多芯ケーブルを提供する。 In order to achieve the above object, the present invention includes a plurality of differential signal lines in which an insulator covering a pair of core wires is covered with a shield conductor, and a substrate having a plurality of electrodes. A multi-core cable in which the pair of core wires exposed from the insulator at each longitudinal end of the dynamic signal line is connected to the electrode, and the plurality of differential signal lines are arranged in parallel with each other. The plurality of differential signal lines in the first layer and the plurality of differential signal lines in the second layer are laminated in a plurality of layers including a first layer in contact with the substrate and a second layer overlapping the first layer. A plurality of differential signal lines are compressed in the stacking direction at a plurality of compression points arranged in the longitudinal direction to plastically deform the insulator, and a predetermined gap is provided between the plurality of compression points. We provide multi-core cables.

また、本発明は、上記の目的を達成するため、一対の心線を被覆する絶縁体をシールド導体で覆ってなる複数の差動信号線と、複数の電極を備えた基板と、前記基板を収容する筐体とを備え、前記複数の差動信号線のそれぞれの長手方向の端部において前記絶縁体から露出した前記一対の心線が前記電極に接続された多芯ケーブルの製造方法であって、前記複数の差動信号線を複数層に積層する積層工程と、前記積層工程で積層された前記複数の差動信号線を積層方向に圧縮して前記絶縁体を塑性変形させる圧縮工程と、前記圧縮工程で圧縮された部分の前記複数の差動信号線を前記基板と共に前記筐体に収容する収容工程とを有し、前記圧縮工程において、前記長手方向に所定の間隔をあけて複数箇所で前記複数の差動信号線を圧縮する、多芯ケーブルの製造方法を提供する。 Further, in order to achieve the above object, the present invention comprises a plurality of differential signal lines in which an insulator covering a pair of core wires is covered with a shield conductor, a substrate provided with a plurality of electrodes, and the substrate. A method for manufacturing a multi-core cable including a housing for accommodating the plurality of differential signal lines, in which the pair of core wires exposed from the insulator at the longitudinal ends of the plurality of differential signal lines are connected to the electrodes. A laminating step of laminating the plurality of differential signal lines in a plurality of layers, and a compression step of compressing the plurality of differential signal lines laminated in the laminating step in the laminating direction to plastically deform the insulator. It has a housing step of accommodating the plurality of differential signal lines of the portion compressed in the compression step together with the substrate in the housing, and in the compression step, a plurality of differential signal lines at a predetermined interval in the longitudinal direction. Provided is a method for manufacturing a multi-core cable, which compresses the plurality of differential signal lines at a location.

本発明に係る多芯ケーブル及び多芯ケーブルの製造方法によれば、複数の差動信号線を複数層に積層し、これらの差動信号線を積層方向に圧縮した場合でも、信号の伝送特性の劣化を抑制することが可能となる。 According to the method for manufacturing a multi-core cable and a multi-core cable according to the present invention, even when a plurality of differential signal lines are stacked in a plurality of layers and these differential signal lines are compressed in the stacking direction, signal transmission characteristics It is possible to suppress the deterioration of the.

本発明の実施の形態に係る多芯ケーブルの一方の端部を示す斜視図である。It is a perspective view which shows one end of the multi-core cable which concerns on embodiment of this invention. （ａ）は多芯ケーブルの筐体内部の構成を示す構成図であり、（ｂ）は（ａ）のＡ−Ａ線における多芯ケーブルの断面図である。(A) is a configuration diagram showing the configuration inside the housing of the multi-core cable, and (b) is a cross-sectional view of the multi-core cable on the AA line of (a). （ａ）及び（ｂ）は、多芯ケーブルの製造時における圧縮工程を示す説明図である。(A) and (b) are explanatory views which show the compression process at the time of manufacturing a multi-core cable. （ａ）及び（ｂ）は、圧縮前後の差動信号線を示す断面図である。(A) and (b) are cross-sectional views showing differential signal lines before and after compression. 第１の圧縮箇所と第２の圧縮箇所との間の非圧縮箇所２００の幅を０ｍｍから５ｍｍまで１ｍｍごとに大きくした場合の差動信号線の差動インピーダンスのシミュレーション結果を示すグラフである。It is a graph which shows the simulation result of the differential impedance of the differential signal line when the width of the uncompressed part 200 between the 1st compressed part and the 2nd compressed part is increased by 1 mm from 0 mm to 5 mm. 図５のシミュレーション結果における非圧縮箇所の幅と差動インピーダンスとの関係を示した折れ線グラフである。6 is a line graph showing the relationship between the width of the uncompressed portion and the differential impedance in the simulation result of FIG.

［実施の形態］
図１は、本発明の実施の形態に係る多芯ケーブルの一方の端部を示す斜視図である。図２（ａ）は、多芯ケーブルの筐体内部の構成を示す構成図であり、図２（ｂ）は、図２（ａ）のＡ−Ａ線における多芯ケーブルの断面図である。図３（ａ）及び（ｂ）は、多芯ケーブルの製造時における圧縮工程を示す説明図である。図４（ａ）及び（ｂ）は、圧縮前後の差動信号線を示す断面図である。 [Embodiment]
FIG. 1 is a perspective view showing one end of a multi-core cable according to an embodiment of the present invention. FIG. 2A is a configuration diagram showing the internal configuration of the multi-core cable housing, and FIG. 2B is a cross-sectional view of the multi-core cable taken along the line AA of FIG. 2A. 3 (a) and 3 (b) are explanatory views showing a compression process at the time of manufacturing a multi-core cable. 4 (a) and 4 (b) are cross-sectional views showing differential signal lines before and after compression.

多芯ケーブル１は、複数の差動信号線２と、複数の差動信号線２を収容する管状のジャケット３と、ジャケット３の端部を収容する筐体４と、筐体４に収容された基板５とを備えている。なお、図１では、多芯ケーブル１の一方の端部のみを図示しているが、他方の端部も同様に構成されている。 The multi-core cable 1 is housed in a plurality of differential signal lines 2, a tubular jacket 3 accommodating a plurality of differential signal lines 2, a housing 4 accommodating an end portion of the jacket 3, and a housing 4. It is provided with a substrate 5. Although only one end of the multi-core cable 1 is shown in FIG. 1, the other end is similarly configured.

図４（ａ）及び（ｂ）に示すように、差動信号線２は、一対の心線２１，２１を被覆する絶縁体２２をシールド導体２３で覆ってなり、差動信号を伝送する。より具体的には、差動信号線２は、一対の心線２１と、一対の心線２１を一括して被覆する絶縁体２２と、絶縁体２２の周囲に螺旋巻きで巻き付けられた帯状のシールド導体２３と、シールド導体２３の外周に巻き付けられた外層テープ２４とを有している。なお、本実施の形態では、一対の心線２１を絶縁体２２で一括して被覆した場合について説明するが、一対の心線２１のそれぞれを別個の絶縁体により被覆し、これらを差動信号線の長手方向に沿って平行に配置してもよい。 As shown in FIGS. 4A and 4B, the differential signal line 2 is formed by covering the insulator 22 covering the pair of core wires 21 and 21 with the shield conductor 23, and transmits the differential signal. More specifically, the differential signal line 2 has a pair of core wires 21, an insulator 22 that collectively covers the pair of core wires 21, and a strip-shaped spirally wound around the insulator 22. It has a shield conductor 23 and an outer layer tape 24 wound around the outer periphery of the shield conductor 23. In the present embodiment, the case where the pair of core wires 21 are collectively covered with the insulator 22 will be described. However, each of the pair of core wires 21 is covered with a separate insulator, and these are differential signals. It may be arranged in parallel along the longitudinal direction of the line.

一対の心線２１，２１は、銅等の良導電性の金属からなる導体線である。一対の心線２１，２１は、単体の絶縁体２２により一括して被覆されており、絶縁体２２に互いに平行に保持されている。差動信号線２が圧縮される前の絶縁体２２は、図４（ａ）に示すように、断面視において一対の心線２１，２１の並び方向の幅がこの並び方向に直交する方向の幅よりも長い長円形状である。絶縁体２２の材料としては、ポリエチレン、ポリテトラフルオロエチレン（ＰＴＦＥ）、テトラフルオロエチレン・ヘキサフルオロプロピレン共重合体（ＦＥＰ）等を好適に用いることができる。 The pair of core wires 21 and 21 are conductor wires made of a good conductive metal such as copper. The pair of core wires 21 and 21 are collectively covered with a single insulator 22, and are held parallel to each other by the insulator 22. As shown in FIG. 4A, the insulator 22 before the differential signal line 2 is compressed has a width in the alignment direction of the pair of core wires 21 and 21 in a direction orthogonal to the alignment direction in a cross-sectional view. It has an oval shape that is longer than its width. As the material of the insulator 22, polyethylene, polytetrafluoroethylene (PTFE), tetrafluoroethylene / hexafluoropropylene copolymer (FEP), or the like can be preferably used.

シールド導体２３は、ＰＥＴ（ポリエチレンテレフタレート）等の樹脂からなる絶縁体層の一方の面に銅箔やアルミ箔等の導電性を有する帯状の金属箔が形成されている。外層テープ２４は、例えばＰＥＴ等の絶縁体層の一方の面に接着剤を含む接着層が形成されている。外層テープ２４は、接着層が内側、絶縁体層が外側となるように、シールド導体２３の周囲に螺旋状に巻き付けられている。 In the shield conductor 23, a band-shaped metal foil having conductivity such as copper foil or aluminum foil is formed on one surface of an insulator layer made of a resin such as PET (polyethylene terephthalate). In the outer layer tape 24, an adhesive layer containing an adhesive is formed on one surface of an insulator layer such as PET. The outer layer tape 24 is spirally wound around the shield conductor 23 so that the adhesive layer is on the inside and the insulator layer is on the outside.

ジャケット３は、複数の差動信号線２と、複数の差動信号線２を一括して被覆する図略の編組線とを収容している。複数の差動信号線２は、筐体４内においてジャケット３から露出している。本実施の形態では、ジャケット３が１６本の差動信号線２を収容している。ただし、差動信号線２の数はこれに限らず、必要に応じて適宜変更することができる。 The jacket 3 houses a plurality of differential signal lines 2 and a braided line (not shown) that collectively covers the plurality of differential signal lines 2. The plurality of differential signal lines 2 are exposed from the jacket 3 in the housing 4. In this embodiment, the jacket 3 accommodates 16 differential signal lines 2. However, the number of differential signal lines 2 is not limited to this, and can be appropriately changed as needed.

筐体４は、第１ケース部材４１と第２ケース部材４２とを有し、第１ケース部材４１と第２ケース部材４２の間に基板５が収容されている。基板５は、長方形状であり、ガラスエポキシ等の平板状の基材５０の両面に配線パターンが形成されたソリッド基板である。基板５は、長手方向の一部が筐体４から露出している。 The housing 4 has a first case member 41 and a second case member 42, and the substrate 5 is housed between the first case member 41 and the second case member 42. The substrate 5 is a solid substrate having a rectangular shape and having wiring patterns formed on both sides of a flat plate-shaped substrate 50 such as glass epoxy. A part of the substrate 5 in the longitudinal direction is exposed from the housing 4.

基板５には、複数の心線接続用電極５１、複数の外部端子接続用電極５２、及び複数の心線接続用電極５１と複数の外部端子接続用電極５２とを接続する図略の配線パターンが両面に形成され、配線パターンがレジスト層５３に覆われている。複数の心線接続用電極５１及び外部端子接続用電極５２は、レジスト塗布されていないパッド電極である。複数の心線接続用電極５１には、差動信号線２のそれぞれの長手方向の端部において絶縁体２２から露出した一対の心線２１，２１がそれぞれ半田付けにより接続されている。複数の外部端子接続用電極５２は、筐体４から露出した基板５の長手方向の一端部に、基板５の短手方向に並んで形成されている。 On the substrate 5, a plurality of core wire connection electrodes 51, a plurality of external terminal connection electrodes 52, and a schematic wiring pattern for connecting the plurality of core wire connection electrodes 51 and the plurality of external terminal connection electrodes 52 are shown. Is formed on both sides, and the wiring pattern is covered with the resist layer 53. The plurality of core wire connecting electrodes 51 and the external terminal connecting electrode 52 are pad electrodes that are not resist-coated. A pair of core wires 21 and 21 exposed from the insulator 22 at the respective longitudinal end portions of the differential signal wire 2 are connected to the plurality of core wire connecting electrodes 51 by soldering. The plurality of external terminal connection electrodes 52 are formed at one end in the longitudinal direction of the substrate 5 exposed from the housing 4 so as to be arranged side by side in the lateral direction of the substrate 5.

基板５は、表裏の区別がなく、両面に同様の配線パターンが形成されているが、以下の説明では便宜上、基板５の一方の面を表（おもて）面５ａといい、他方の面を裏面５ｂという。１６本の差動信号線２のうち、半数の８本の差動信号線２は表面５ａ側に配置され、残りの８本の差動信号線２は裏面５ｂ側に配置されている。 The substrate 5 has no distinction between the front and back surfaces, and the same wiring pattern is formed on both sides. However, in the following description, for convenience, one surface of the substrate 5 is referred to as a front surface 5a, and the other surface is referred to as a front surface 5a. Is called the back surface 5b. Of the 16 differential signal lines 2, half of the eight differential signal lines 2 are arranged on the front surface 5a side, and the remaining eight differential signal lines 2 are arranged on the back surface 5b side.

複数の差動信号線２は、基板５の表面５ａ及び裏面５ｂ上において、基板５の長手方向に沿って互いに平行に配置され、かつ基板５の厚み方向に複数層に積層されている。本実施の形態では、８本の差動信号線２のそれぞれが、基板５に接する第１層２Ａと第１層２Ａに重なる第２層Ｂに積層されている。表面５ａ側の第１層２Ａ及び第２層２Ｂは、それぞれ４本の差動信号線２からなる。同様に、裏面５ｂ側の第１層２Ａ及び第２層２Ｂは、それぞれ４本の差動信号線２からなる。なお、複数の差動信号線２は、表面５ａ側及び裏面５ｂ側のそれぞれにおいて、第１層２Ａ及び第２層２Ｂを含む複数層に形成されていればよく、三層以上の層数を以って積層されていてもよい。 The plurality of differential signal lines 2 are arranged parallel to each other along the longitudinal direction of the substrate 5 on the front surface 5a and the back surface 5b of the substrate 5, and are laminated in a plurality of layers in the thickness direction of the substrate 5. In the present embodiment, each of the eight differential signal lines 2 is laminated on the first layer 2A in contact with the substrate 5 and the second layer B overlapping the first layer 2A. The first layer 2A and the second layer 2B on the surface 5a side are each composed of four differential signal lines 2. Similarly, the first layer 2A and the second layer 2B on the back surface 5b side each consist of four differential signal lines 2. The plurality of differential signal lines 2 may be formed in a plurality of layers including the first layer 2A and the second layer 2B on the front surface 5a side and the back surface 5b side, respectively, and may have three or more layers. Therefore, they may be laminated.

基板５は、表面５ａが第１ケース部材４１に対向し、裏面５ｂが第２ケース部材４２に対向している。表面５ａ側の複数の差動信号線２は、基板５と第１ケース部材４１との間に配置され、裏面５ｂ側の複数の差動信号線２は、基板５と第２ケース部材４２との間に配置されている。図２（ａ）では、第１ケース部材４１を除いて基板５の表面５ａ側を図示している。 The front surface 5a of the substrate 5 faces the first case member 41, and the back surface 5b faces the second case member 42. The plurality of differential signal lines 2 on the front surface 5a side are arranged between the substrate 5 and the first case member 41, and the plurality of differential signal lines 2 on the back surface 5b side are the substrate 5 and the second case member 42. It is placed between. In FIG. 2A, the surface 5a side of the substrate 5 is shown except for the first case member 41.

第２層２Ｂの複数の差動信号線２は、第１層２Ａの複数の差動信号線２よりも長くジャケット３から露出しており、基板５上における長さが長い。第２層２Ｂの複数の差動信号線２は、第１層２Ａの複数の差動信号線２よりも外部端子接続用電極５２に近い部分で、基板５側に屈曲されている。また、第２層２Ｂの複数の差動信号線２の一対の心線２１，２１は、第１層２Ａの複数の差動信号線２の一対の心線２１，２１よりも複数の外部端子接続用電極５２に近い位置で、複数の心線接続用電極５１に接続されている。 The plurality of differential signal lines 2 of the second layer 2B are longer than the plurality of differential signal lines 2 of the first layer 2A and are exposed from the jacket 3, and are longer on the substrate 5. The plurality of differential signal lines 2 of the second layer 2B are bent toward the substrate 5 at a portion closer to the external terminal connection electrode 52 than the plurality of differential signal lines 2 of the first layer 2A. Further, the pair of core wires 21 and 21 of the plurality of differential signal lines 2 of the second layer 2B have a plurality of external terminals more than the pair of core wires 21 and 21 of the plurality of differential signal lines 2 of the first layer 2A. It is connected to a plurality of core wire connecting electrodes 51 at a position close to the connecting electrode 52.

第１層２Ａの複数の差動信号線２と第２層２Ｂの複数の差動信号線２とは、これら複数の差動信号線２の長手方向に並ぶ複数の圧縮箇所で積層方向に圧縮されて絶縁体２２が塑性変形しており、これら複数の圧縮箇所の間に所定の間隙が設けられている。本実施の形態では、複数の差動信号線２が第１の圧縮箇所２０１及び第２の圧縮箇所２０２で圧縮されており、第１の圧縮箇所２０１と第２の圧縮箇所２０２との間に、圧縮されていない非圧縮箇所２００が存在している。第１及び第２の圧縮箇所２０１，２０２は、基板５の短手方向に延びる帯状の領域である。図２（ｂ）では、第１の圧縮箇所２０１における断面を図示している。 The plurality of differential signal lines 2 of the first layer 2A and the plurality of differential signal lines 2 of the second layer 2B are compressed in the stacking direction at a plurality of compression points arranged in the longitudinal direction of the plurality of differential signal lines 2. The insulator 22 is plastically deformed, and a predetermined gap is provided between the plurality of compression points. In the present embodiment, a plurality of differential signal lines 2 are compressed at the first compression point 201 and the second compression point 202, and are between the first compression point 201 and the second compression point 202. , There are uncompressed uncompressed locations 200. The first and second compression points 201 and 202 are strip-shaped regions extending in the lateral direction of the substrate 5. FIG. 2B illustrates a cross section at the first compression point 201.

複数の差動信号線２の長手方向における第１の圧縮箇所２０１及び第２の圧縮箇所２０２の幅Ｗ_１，Ｗ_２（図２（ａ）参照）は、例えば２．５ｍｍである。また、第１の圧縮箇所２０１と第２の圧縮箇所２０２との間の所定の間隔、すなわち複数の差動信号線２の長手方向における非圧縮箇所２００の幅Ｗ_０は、１ｍｍ以上であることが望ましく、４ｍｍ以上であることがより望ましい。この理由については後述する。なお、筐体４の非圧縮箇所２００に対応する部分では、第１ケース部材４１及び第２ケース部材４２の肉厚を薄くしてもよい。 The widths W ₁ and W ₂ (see FIG. 2A) of the first compression points 201 and the second compression points 202 in the longitudinal direction of the plurality of differential signal lines 2 are, for example, 2.5 mm. Further, the predetermined distance between the first compressed portion 201 and the second compressed portion 202, that is, the width W ₀ of the uncompressed portion 200 in the longitudinal direction of the plurality of differential signal lines 2 is 1 mm or more. Is desirable, and more preferably 4 mm or more. The reason for this will be described later. In the portion of the housing 4 corresponding to the uncompressed portion 200, the wall thickness of the first case member 41 and the second case member 42 may be reduced.

次に、多芯ケーブル１の製造方法について説明する。多芯ケーブル１は、ジャケット３の一部を除去して複数の差動信号線２を露出させると共に、それぞれの差動信号線２の絶縁体２２の一部を除去して一対の心線２１，２１を露出させる端末処理工程と、端末処理された複数の差動信号線２を複数層に積層する積層工程と、積層工程で積層された複数の差動信号線２を積層方向に圧縮して絶縁体２２を塑性変形させる圧縮工程と、圧縮工程で圧縮された部分の複数の差動信号線２を基板５と共に筐体４に収容する収容工程とを有している。本実施の形態では、絶縁体２２を変形させやすくするため、絶縁体２２が６０℃以上になるように差動信号線２を加熱した状態で圧縮工程を行う。 Next, a method of manufacturing the multi-core cable 1 will be described. In the multi-core cable 1, a part of the jacket 3 is removed to expose a plurality of differential signal lines 2, and a part of the insulator 22 of each differential signal line 2 is removed to expose a pair of core wires 21. , 21 is exposed, a stacking step of stacking a plurality of terminal-processed differential signal lines 2 in a plurality of layers, and a stacking step of compressing the plurality of differential signal lines 2 laminated in the stacking step in the stacking direction. It has a compression step of plastically deforming the insulator 22 and an accommodation step of accommodating a plurality of differential signal lines 2 of the portion compressed in the compression step in the housing 4 together with the substrate 5. In the present embodiment, in order to make the insulator 22 easily deformed, the compression step is performed in a state where the differential signal line 2 is heated so that the insulator 22 has a temperature of 60 ° C. or higher.

積層工程では、図３（ａ）に示すように、第２層２Ｂの複数の差動信号線２のうち少なくとも一部の差動信号線２を、第１層２Ａにおいて隣り合う二本の差動信号線２の間に重なるように配置する。本実施の形態では、第１層２Ａ及び第２層２Ｂが、基板５の短手方向一側及び他側にあたる二つの区域Ｄ_１，Ｄ_２に分かれて配置されており、それぞれの区域Ｄ_１，Ｄ_２において複数の差動信号線２が二層に積層されている。 In the laminating step, as shown in FIG. 3A, at least a part of the plurality of differential signal lines 2 of the second layer 2B is the difference between two adjacent differential signal lines 2 in the first layer 2A. It is arranged so as to overlap between the moving signal lines 2. In the present embodiment, the first layer 2A and the second layer 2B are divided into two areas D ₁ and D ₂ corresponding to one side and the other side in the lateral direction of the substrate 5, and the respective areas D ₁ are arranged. a plurality of differential signal lines 2 are stacked in two layers in D _2.

圧縮工程では、上型６１及び下型６２と、上型６１と下型６２との間に配置される平板状の板型６３とを用いて、１６本の差動信号線２を一括して圧縮する。上型６１は、平板状の基部６１１と、一対の側壁６１２，６１３と、区域Ｄ_１，Ｄ_２を区画する区画壁６１４とを一体に有し、一対の側壁６１２，６１３及び区画壁６１４によって二つの区域Ｄ_１，Ｄ_２の並び方向（図３の左右方向）への複数の差動信号線２の移動を規制しながら、基板５の表面５ａ側に配置される８本の差動信号線２を板型６３に向かって圧縮する。 In the compression step, 16 differential signal lines 2 are collectively used by using the upper mold 61 and the lower mold 62 and the flat plate mold 63 arranged between the upper mold 61 and the lower mold 62. Compress. The upper mold 61 integrally has a flat base portion 611, a pair of side walls 612, 613, and a partition wall 614 for partitioning areas D ₁ and D ₂ , and is provided by the pair of side walls 612, 613 and the partition wall 614. Eight differential signals arranged on the surface 5a side of the substrate 5 while restricting the movement of the plurality of differential signal lines 2 in the arrangement direction of the two areas D ₁ and D ₂ (horizontal direction in FIG. 3). The wire 2 is compressed toward the plate 63.

同様に、下型６２は、平板状の基部６２１と、一対の側壁６２２，６２３と、区域Ｄ_１，Ｄ_２を区画する区画壁６２４とを一体に有し、一対の側壁６２２，６２３及び区画壁６２４によって二つの区域Ｄ_１，Ｄ_２の並び方向への複数の差動信号線２の移動を規制しながら、基板５の裏面５ｂ側に配置される８本の差動信号線２を板型６３に向かって圧縮する。上型６１の一対の側壁６１２，６１３及び区画壁６１４と、下型６２の一対の側壁６２２，６２３と区画壁６２４とは、板型６３を挟む同じ位置に設けられている。 Similarly, the lower mold 62 integrally has a flat plate-shaped base 621, a pair of side walls 622, 623, and a partition wall 624 for partitioning areas D ₁ and D ₂ , and has a pair of side walls 622, 623 and a partition. Eight differential signal lines 2 arranged on the back surface 5b side of the substrate 5 are boarded while the wall 624 regulates the movement of the plurality of differential signal lines _{2 in} the alignment direction of the two areas D ₁ and D _2. Compress towards mold 63. The pair of side walls 612 and 613 and the partition wall 614 of the upper mold 61 and the pair of side walls 622 and 623 of the lower mold 62 and the partition wall 624 are provided at the same positions sandwiching the plate mold 63.

この圧縮工程では、複数の差動信号線２の長手方向に所定の間隔をあけて複数箇所で複数の差動信号線２を圧縮する。この圧縮方法として具体的には、一組の上下型６１，６２及び板型６３を用いて、二回に分けて第１の圧縮箇所２０１及び第２の圧縮箇所２０２を圧縮してもよく、二組の上下型６１，６２及び板型６３を用いて、第１の圧縮箇所２０１及び第２の圧縮箇所２０２を同時に圧縮してもよい。 In this compression step, the plurality of differential signal lines 2 are compressed at a plurality of locations at predetermined intervals in the longitudinal direction of the plurality of differential signal lines 2. Specifically, as this compression method, a set of upper and lower molds 61 and 62 and a plate mold 63 may be used to compress the first compression portion 201 and the second compression portion 202 in two steps. Two sets of upper and lower molds 61 and 62 and a plate mold 63 may be used to simultaneously compress the first compression portion 201 and the second compression portion 202.

圧縮工程により圧縮された複数（１６本）の差動信号線２は、板型６３が配置されていた部分の空間に基板５を挟むように、表面５ａ及び裏面５ｂ側に分かれて配置される。その後、それぞれの差動信号線２の一対の心線２１，２１が心線接続用電極５１に接続される。 The plurality of (16) differential signal lines 2 compressed by the compression step are separately arranged on the front surface 5a and the back surface 5b side so as to sandwich the substrate 5 in the space of the portion where the plate mold 63 is arranged. .. After that, a pair of core wires 21 and 21 of each differential signal line 2 are connected to the core wire connecting electrode 51.

収容工程では、心線２１，２１が心線接続用電極５１に接続された複数の差動信号線２を基板５と共に筐体４に収容する。より具体的には、複数の差動信号線２及び基板５を第１ケース部材４１と第２ケース部材４２との間に挟み込むように、第１ケース部材４１と第２ケース部材４２とを締結する。 In the accommodating step, a plurality of differential signal lines 2 in which the core wires 21 and 21 are connected to the core wire connecting electrodes 51 are accommodated in the housing 4 together with the substrate 5. More specifically, the first case member 41 and the second case member 42 are fastened so as to sandwich the plurality of differential signal lines 2 and the substrate 5 between the first case member 41 and the second case member 42. To do.

上記のようにして製造された多芯ケーブル１は、第１の圧縮箇所２０１及び第２の圧縮箇所２０２において差動信号線２の絶縁体２２が図４（ａ）に示す形状から図４（ｂ）に示す形状に変形するので、一対の心線２１，２１とシールド導体２３との間の距離が、圧縮された部分と圧縮されていない部分とで異なる。これにより、第１及び第２の圧縮箇所２０１，２０２と、第１及び第２の圧縮箇所２０１，２０２以外の部分とで、特に信号周波数が１ＧＨｚを越えるようなＧＨｚ帯の高周波領域において差動信号が一対の心線２１，２１を伝搬する際のインピーダンスが変化する。このようにインピーダンスが部位よって異なると、信号の反射特性に影響が生じる。本実施の形態では、第１の圧縮箇所２０１と第２の圧縮箇所２０２との間に非圧縮箇所２００を設けることで、この影響を抑制している。次に、図５及び図６を参照し、非圧縮箇所２００による信号の反射抑制効果について説明する。 In the multi-core cable 1 manufactured as described above, the insulator 22 of the differential signal line 2 at the first compression portion 201 and the second compression portion 202 has the shape shown in FIG. Since it is deformed into the shape shown in b), the distance between the pair of core wires 21 and 21 and the shield conductor 23 differs between the compressed portion and the uncompressed portion. As a result, differential between the first and second compression points 201 and 202 and the parts other than the first and second compression points 201 and 202, especially in the high frequency region of the GHz band where the signal frequency exceeds 1 GHz. The impedance changes when the signal propagates through the pair of core wires 21 and 21. If the impedance differs depending on the part in this way, the reflection characteristics of the signal will be affected. In the present embodiment, this influence is suppressed by providing the uncompressed portion 200 between the first compressed portion 201 and the second compressed portion 202. Next, with reference to FIGS. 5 and 6, the reflection suppression effect of the signal by the uncompressed portion 200 will be described.

図５は、第１の圧縮箇所２０１及び第２の圧縮箇所２０２の幅Ｗ_１，Ｗ_２を２．５ｍｍとして固定し、非圧縮箇所２００の幅Ｗ_０を０ｍｍから５ｍｍまで１ｍｍごとに大きくした場合の差動信号線２の差動インピーダンスのシミュレーション結果を示すグラフである。このシミュレーションでは、差動信号線２の端部に差動信号を入力したときの差動インピーダンスを信号入力時点からの経過時間と共に示している。図５のグラフは、横軸が経過時間（ｎｓ）を示し、縦軸が差動インピーダンス（Ω）を示している。横軸は、差動信号線２の端部からの距離と読み替えることができる。 In FIG. 5, the widths W ₁ and W ₂ of the first compressed portion 201 and the second compressed portion 202 are fixed as 2.5 mm, and the width W ₀ of the uncompressed portion 200 is increased from ₀ mm to 5 mm in 1 mm increments. It is a graph which shows the simulation result of the differential impedance of the differential signal line 2 in the case. In this simulation, the differential impedance when a differential signal is input to the end of the differential signal line 2 is shown together with the elapsed time from the time of signal input. In the graph of FIG. 5, the horizontal axis represents the elapsed time (ns) and the vertical axis represents the differential impedance (Ω). The horizontal axis can be read as the distance from the end of the differential signal line 2.

図６は、図５のシミュレーション結果における非圧縮箇所２００の幅Ｗ_０と差動インピーダンスとの関係をより分かりやすく示した折れ線グラフである。図６のグラフでは、非圧縮箇所２００の幅Ｗ_０が０ｍｍの場合、すなわち第１の圧縮箇所２０１と第２の圧縮箇所２０２とが連続して５ｍｍ幅の圧縮領域が形成された場合の差動インピーダンスの極小値を基準値（０）とし、非圧縮箇所２００の幅Ｗ_０を０ｍｍから５ｍｍまで順次大きくした場合の差動インピーダンスの極小値の基準値からの変化量を縦軸に示している。 FIG. 6 is a line graph showing the relationship between the width W ₀ of the uncompressed portion 200 and the differential impedance in the simulation result of FIG. 5 in a more understandable manner. In the graph of FIG. 6, the difference when the width W ₀ of the uncompressed portion 200 is ₀ mm, that is, when the first compressed portion 201 and the second compressed portion 202 continuously form a compressed region having a width of 5 mm. The vertical axis shows the amount of change from the reference value of the minimum value of the differential impedance when the width W ₀ of the uncompressed portion 200 is gradually increased from ₀ mm to 5 mm with the minimum value of the dynamic impedance as the reference value (0). There is.

図５に示すように、第１の圧縮箇所２０１から第２の圧縮箇所２０２までの間を外れた部分の差動インピーダンスは９９．３Ωであり、非圧縮箇所２００の幅Ｗ_０が０ｍｍの場合の差動インピーダンスの極小値は９６．６Ωである。このため、図６のグラフにおいて、差動インピーダンスの変化量が正値で２．７（＝９９．３−９６．６）Ωに近いほど、第１の圧縮箇所２０１から第２の圧縮箇所２０２までの間のインピーダンス特性が、第１の圧縮箇所２０１から第２の圧縮箇所２０２までの間を外れた部分のインピーダンス特性に近いこととなる。 As shown in FIG. 5, the differential impedance of the portion deviated from the first compressed portion 201 to the second compressed portion 202 is 99.3 Ω, and the width W _{0 of the} uncompressed portion 200 is ₀ mm. The minimum value of the differential impedance of is 96.6Ω. Therefore, in the graph of FIG. 6, the closer the change amount of the differential impedance is to 2.7 (= 99.3-96.6) Ω, the more the first compression point 201 to the second compression point 202. The impedance characteristic between the first compression point 201 and the second compression point 202 is close to the impedance characteristic of the portion deviated from the second compression point 202.

なお、信号の反射は、インピーダンス特性が変化する部分で発生し、インピーダンスの変化量が大きいほど反射が大きくなる。したがって、第１の圧縮箇所２０１から第２の圧縮箇所２０２までの間の差動インピーダンスの極小値が、第１の圧縮箇所２０１から第２の圧縮箇所２０２までの間を外れた部分の差動インピーダンス（本例では９９．３Ω）に近いほど信号の反射が抑えられる。 The signal reflection occurs at the portion where the impedance characteristic changes, and the larger the impedance change amount, the larger the reflection. Therefore, the differential of the portion where the minimum value of the differential impedance between the first compression point 201 and the second compression point 202 is out of the range between the first compression point 201 and the second compression point 202. The closer it is to the impedance (99.3Ω in this example), the more the signal reflection is suppressed.

図６に示すように、基準値からの差動インピーダンスの極小値の変化量は、幅Ｗ_０を０ｍｍから１ｍｍに大きくすることにより増大し、幅Ｗ_０を１ｍｍから２ｍｍに大きくすることによりさらに大きな変化幅で増大する。幅Ｗ_０が２ｍｍを超えると、差動インピーダンスの極小値の変化幅は徐々に縮小し、４ｍｍを超えると差動インピーダンスの極小値の変化が飽和する。このため、幅Ｗ_０は１ｍｍ以上であることが望ましく、４ｍｍ以上であることがより望ましい。ただし、幅Ｗ_０の増大は基板５や筐体４の大型化を招来するので、幅Ｗ_０は５ｍｍ以下であることが望ましい。 As shown in FIG. 6, the amount of change in the minimum value of the differential impedance from the reference value is increased by increasing the width W ₀ from ₀ mm to 1 mm, and further by increasing the width W ₀ from 1 mm to 2 mm. It increases with a large range of change. When the width W ₀ exceeds 2 mm, the change width of the minimum value of the differential impedance gradually decreases, and when it exceeds 4 mm, the change of the minimum value of the differential impedance is saturated. Therefore, the width W ₀ is preferably 1 mm or more, and more preferably 4 mm or more. However, since an increase in the width W ₀ leads to an increase in the size of the substrate 5 and the housing 4, it is desirable that the width W ₀ is 5 mm or less.

（実施の形態の作用及び効果）
以上説明した本実施の形態によれば、複数の差動信号線２を複数層に積層し、さらに第１及び第２の圧縮箇所２０１，２０２において積層方向に圧縮しているので、複数の差動信号線２を高密度に配置することができる。また、このように複数の差動信号線２を積層及び圧縮した場合でも、第１の圧縮箇所２０１と第２の圧縮箇所２０２との間に非圧縮箇所２００を設けることにより、信号の伝送特性の劣化が抑制される。 (Actions and effects of embodiments)
According to the present embodiment described above, since the plurality of differential signal lines 2 are laminated in a plurality of layers and further compressed in the stacking direction at the first and second compression points 201 and 202, a plurality of differences are obtained. The dynamic signal lines 2 can be arranged at a high density. Further, even when a plurality of differential signal lines 2 are laminated and compressed in this way, the signal transmission characteristic is provided by providing the uncompressed portion 200 between the first compressed portion 201 and the second compressed portion 202. Deterioration is suppressed.

（実施の形態のまとめ）
次に、以上説明した実施の形態から把握される技術思想について、実施の形態における符号等を援用して記載する。ただし、以下の記載における各符号は、特許請求の範囲における構成要素を実施の形態に具体的に示した部材等に限定するものではない。 (Summary of embodiments)
Next, the technical idea grasped from the above-described embodiment will be described with reference to the reference numerals and the like in the embodiment. However, each reference numeral in the following description is not limited to the member or the like in which the components in the claims are specifically shown in the embodiment.

［１］一対の心線（２１，２１）を被覆する絶縁体（２２）をシールド導体（２３）で覆ってなる複数の差動信号線（２）と、複数の電極（５１）を有する基板（５）とを備え、前記複数の差動信号線（２）のそれぞれの長手方向の端部において前記絶縁体（２２）から露出した前記一対の心線（２１，２１）が前記電極（５２）に接続された多芯ケーブルであって、前記複数の差動信号線（２）は、互いに平行に配置され、かつ前記基板（５）に接する第１層（２Ａ）と前記第１層（２Ａ）に重なる第２層（２Ｂ）とを含む複数層に積層されており、前記第１層（２Ａ）の前記複数の差動信号線（２）と前記第２層（２Ｂ）の前記複数の差動信号線（２）とが、前記長手方向に並ぶ複数の圧縮箇所（２０１，２０２）で積層方向に圧縮されて前記絶縁体（２２）が塑性変形しており、前記複数の圧縮箇所（２０１，２０２）の間に所定の間隙（Ｗ_０）が設けられている、多芯ケーブル（１）。 [1] A substrate having a plurality of differential signal lines (2) formed by covering an insulator (22) covering a pair of core wires (21, 21) with a shield conductor (23), and a plurality of electrodes (51). The pair of core wires (21, 21) exposed from the insulator (22) at the longitudinal end of each of the plurality of differential signal lines (2) provided with (5) are the electrodes (52). The first layer (2A) and the first layer (2A) in which the plurality of differential signal lines (2) are arranged in parallel with each other and are in contact with the substrate (5). It is laminated on a plurality of layers including a second layer (2B) overlapping the 2A), and the plurality of differential signal lines (2) of the first layer (2A) and the plurality of the second layer (2B). The differential signal line (2) of the above is compressed in the stacking direction at the plurality of compression points (201, 202) arranged in the longitudinal direction, and the insulator (22) is plastically deformed, and the plurality of compression points are formed. A multi-core cable (1) in which a predetermined gap (W ₀ ) is provided between (201, 202).

［２］前記第２層（２Ｂ）の前記複数の差動信号線（２）のうち少なくとも一部の差動信号線（２）は、前記第１層（２Ａ）において隣り合う二本の前記差動信号線（２）の間に重なるように配置されている、上記［１］に記載の多芯ケーブル（１）。 [2] At least a part of the plurality of differential signal lines (2) in the second layer (2B) is the two adjacent differential signal lines (2) in the first layer (2A). The multi-core cable (1) according to the above [1], which is arranged so as to overlap between the differential signal lines (2).

［３］前記第２層（２Ｂ）の前記複数の差動信号線（２）は、前記第１層（２Ａ）の前記複数の差動信号線（２）より前記基板（５）上における長さが長い、上記［１］又は［２］に記載の多芯ケーブル（１）。 [3] The plurality of differential signal lines (2) of the second layer (2B) are longer on the substrate (5) than the plurality of differential signal lines (2) of the first layer (2A). The multi-core cable (1) according to the above [1] or [2], which has a long length.

［４］前記所定の間隙（Ｗ_０）が１ｍｍ以上である、上記［１］乃至上記［３］に記載の多芯ケーブル（５０）。 [4] The multi-core cable (50) according to the above [1] to the above [3], wherein the predetermined gap (W ₀ ) is 1 mm or more.

［５］前記所定の間隙（Ｗ_０）が４ｍｍ以上である、上記［４］に記載の多芯ケーブル（５０）。 [5] The multi-core cable (50) according to the above [4], wherein the predetermined gap (W ₀ ) is 4 mm or more.

［６］一対の心線（２１，２１）を被覆する絶縁体（２２）をシールド導体（２３）で覆ってなる複数の差動信号線（２）と、複数の電極（５１）を有する基板（５）と、前記基板（５）を収容する筐体（４）とを備え、前記複数の差動信号線（２）のそれぞれの長手方向の端部において前記絶縁体（２２）から露出した前記一対の心線（２１，２１）が前記電極（５１）に接続された多芯ケーブル（１）の製造方法であって、前記複数の差動信号線（２）を複数層に積層する積層工程と、前記積層工程で積層された前記複数の差動信号線（２）を積層方向に圧縮して前記絶縁体（２２）を塑性変形させる圧縮工程と、前記圧縮工程で圧縮された部分の前記複数の差動信号線（２）を前記基板（５）と共に前記筐体（４）に収容する収容工程とを有し、前記圧縮工程において、前記長手方向に所定の間隔（Ｗ_０）をあけて複数箇所で前記複数の差動信号線（２）を圧縮する、多芯ケーブル（１）の製造方法。 [6] A substrate having a plurality of differential signal lines (2) formed by covering an insulator (22) covering a pair of core wires (21, 21) with a shield conductor (23), and a plurality of electrodes (51). (5) and a housing (4) for accommodating the substrate (5) are provided, and the plurality of differential signal lines (2) are exposed from the insulator (22) at their respective longitudinal ends. A method for manufacturing a multi-core cable (1) in which the pair of core wires (21, 21) are connected to the electrode (51), and the plurality of differential signal wires (2) are laminated in a plurality of layers. A step, a compression step of compressing the plurality of differential signal lines (2) laminated in the stacking step in the stacking direction to plastically deform the insulator (22), and a portion compressed in the compression step. It has a housing step of accommodating the plurality of differential signal lines (2) together with the substrate (5) in the housing (4), and in the compression step, a predetermined interval (W ₀ ) is provided in the longitudinal direction. A method for manufacturing a multi-core cable (1) in which the plurality of differential signal lines (2) are compressed at a plurality of locations.

以上、本発明の実施の形態を説明したが、上記に記載した実施の形態は特許請求の範囲に係る発明を限定するものではない。また、実施の形態の中で説明した特徴の組合せの全てが発明の課題を解決するための手段に必須であるとは限らない点に留意すべきである。 Although the embodiments of the present invention have been described above, the embodiments described above do not limit the invention according to the claims. It should also be noted that not all combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

例えば、上記実施の形態では、基板５の裏面５ｂ側にも複数層に差動信号線２を配置したが、裏面５ｂには複数の差動信号線２を複数層に重ねることなく配置してもよい。また、裏面５ｂには差動信号線２を配置しなくともよい。 For example, in the above embodiment, the differential signal lines 2 are arranged in a plurality of layers on the back surface 5b side of the substrate 5, but the plurality of differential signal lines 2 are arranged on the back surface 5b without overlapping the plurality of layers. May be good. Further, the differential signal line 2 does not have to be arranged on the back surface 5b.

また、上記の実施の形態では、上型６１及び下型６２によって板型６３に向かって複数の差動信号線２を圧縮する場合について説明したが、板型６３に替えて、基板５に向かって複数の差動信号線２を圧縮してもよい。この場合、上型６１及び下型６２によって差動信号線２を圧縮したまま、それぞれの差動信号線２の一対の心線２１，２１を外部端子接続用電極５２に半田付けしてもよい。 Further, in the above embodiment, the case where a plurality of differential signal lines 2 are compressed toward the plate mold 63 by the upper mold 61 and the lower mold 62 has been described, but instead of the plate mold 63, the head toward the substrate 5. The plurality of differential signal lines 2 may be compressed. In this case, the pair of core wires 21 and 21 of the respective differential signal lines 2 may be soldered to the external terminal connection electrode 52 while the differential signal lines 2 are compressed by the upper die 61 and the lower die 62. ..

１…多芯ケーブル
２…差動信号線
２Ａ…第１層
２Ｂ…第２層
２０１…第１の圧縮箇所
２０２…第２の圧縮箇所
２１，２１…心線
２２…絶縁体
２３…シールド導体
４…筐体
５…基板
５１…心線接続用電極
1 ... Multi-core cable 2 ... Differential signal line 2A ... First layer 2B ... Second layer 201 ... First compression point 202 ... Second compression point 21 and 21 ... Core wire 22 ... Insulator 23 ... Shield conductor 4 ... Housing 5 ... Substrate 51 ... Electrodes for connecting core wires

Claims (6)

一対の心線を被覆する絶縁体をシールド導体で覆ってなる複数の差動信号線と、複数の電極を有する基板とを備え、前記複数の差動信号線のそれぞれの長手方向の端部において前記絶縁体から露出した前記一対の心線が前記電極に接続された多芯ケーブルであって、
前記複数の差動信号線は、互いに平行に配置され、かつ前記基板に接する第１層と前記第１層に重なる第２層とを含む複数層に積層されており、
前記第１層の前記複数の差動信号線と前記第２層の前記複数の差動信号線とが、前記長手方向に並ぶ複数の圧縮箇所で積層方向に圧縮されて前記絶縁体が塑性変形しており、
前記複数の圧縮箇所の間に所定の間隙が設けられている、
多芯ケーブル。 A plurality of differential signal lines in which an insulator covering a pair of core wires is covered with a shield conductor and a substrate having a plurality of electrodes are provided, and at the end portions of the plurality of differential signal lines in the longitudinal direction. A multi-core cable in which the pair of core wires exposed from the insulator is connected to the electrodes.
The plurality of differential signal lines are arranged in parallel with each other and are laminated in a plurality of layers including a first layer in contact with the substrate and a second layer overlapping the first layer.
The plurality of differential signal lines of the first layer and the plurality of differential signal lines of the second layer are compressed in the stacking direction at a plurality of compression points arranged in the longitudinal direction, and the insulator is plastically deformed. And
A predetermined gap is provided between the plurality of compression points.
Multi-core cable. 前記第２層の前記複数の差動信号線のうち少なくとも一部の差動信号線は、前記第１層において隣り合う二本の前記差動信号線の間に重なるように配置されている、
請求項１に記載の多芯ケーブル。 At least a part of the plurality of differential signal lines in the second layer is arranged so as to overlap between two adjacent differential signal lines in the first layer.
The multi-core cable according to claim 1. 前記第２層の前記複数の差動信号線は、前記第１層の前記複数の差動信号線より前記基板上における長さが長い、
請求項１又は２に記載の多芯ケーブル。 The plurality of differential signal lines in the second layer have a longer length on the substrate than the plurality of differential signal lines in the first layer.
The multi-core cable according to claim 1 or 2. 前記所定の間隔が１ｍｍ以上である、
請求項１及至請求項３に記載のいずれか１項に記載の多芯ケーブル。 The predetermined interval is 1 mm or more.
The multi-core cable according to any one of claims 1 and 3. 前記所定の間隔が４ｍｍ以上である、
請求項４に記載の多芯ケーブル。 The predetermined interval is 4 mm or more.
The multi-core cable according to claim 4. 一対の心線を被覆する絶縁体をシールド導体で覆ってなる複数の差動信号線と、複数の電極を有する基板と、前記基板を収容する筐体とを備え、前記複数の差動信号線のそれぞれの長手方向の端部において前記絶縁体から露出した前記一対の心線が前記電極に接続された多芯ケーブルの製造方法であって、
前記複数の差動信号線を複数層に積層する積層工程と、
前記積層工程で積層された前記複数の差動信号線を積層方向に圧縮して前記絶縁体を塑性変形させる圧縮工程と、
前記圧縮工程で圧縮された部分の前記複数の差動信号線を前記基板と共に前記筐体に収容する収容工程とを有し、
前記圧縮工程において、前記長手方向に所定の間隔をあけて複数箇所で前記複数の差動信号線を圧縮する、
多芯ケーブルの製造方法。 The plurality of differential signal lines are provided with a plurality of differential signal lines in which an insulator covering a pair of core wires is covered with a shield conductor, a substrate having a plurality of electrodes, and a housing for accommodating the substrate. A method for manufacturing a multi-core cable in which the pair of core wires exposed from the insulator at each longitudinal end of the cable are connected to the electrodes.
A laminating step of laminating the plurality of differential signal lines in a plurality of layers, and
A compression step of compressing the plurality of differential signal lines laminated in the lamination step in the lamination direction to plastically deform the insulator, and
It has a housing step of accommodating the plurality of differential signal lines of the portion compressed in the compression step together with the substrate in the housing.
In the compression step, the plurality of differential signal lines are compressed at a plurality of locations at predetermined intervals in the longitudinal direction.
Manufacturing method of multi-core cable.

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