JP2020150094A - Printed wiring board and manufacturing method thereof - Google Patents

Printed wiring board and manufacturing method thereof Download PDF

Info

Publication number
JP2020150094A
JP2020150094A JP2019045470A JP2019045470A JP2020150094A JP 2020150094 A JP2020150094 A JP 2020150094A JP 2019045470 A JP2019045470 A JP 2019045470A JP 2019045470 A JP2019045470 A JP 2019045470A JP 2020150094 A JP2020150094 A JP 2020150094A
Authority
JP
Japan
Prior art keywords
hole
electronic component
resin
core substrate
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019045470A
Other languages
Japanese (ja)
Other versions
JP7184679B2 (en
Inventor
清水 敬介
Keisuke Shimizu
敬介 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP2019045470A priority Critical patent/JP7184679B2/en
Publication of JP2020150094A publication Critical patent/JP2020150094A/en
Application granted granted Critical
Publication of JP7184679B2 publication Critical patent/JP7184679B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

To improve connection reliability of a through-hole conductor of an electronic component built in an opening of a resin core substrate.SOLUTION: In a printed wiring board with an electronic component built into an opening of a resin core substrate, the electronic component includes a through-hole conductor that electrically connects conductor circuits on both sides of the electronic component and a through hole that penetrates the central portion of the through-hole conductor in the through-hole that penetrates the electronic component, and a resin having higher fluidity in a molten state than the resin constituting the core substrate is filled around the electronic component in the opening of the resin core substrate and in the through hole.SELECTED DRAWING: Figure 1

Description

本発明は、樹脂製コア基板の開口内にICチップや回路基板等の電子部品を内蔵するプリント配線板およびその製造方法に関する。 The present invention relates to a printed wiring board in which electronic components such as an IC chip and a circuit board are embedded in an opening of a resin core substrate, and a method for manufacturing the printed wiring board.

近年のプリント配線板の高密度化および低背化の要求に対して、樹脂でガラス基板を被覆するプリント基板のデザインが提案されている(例えば特許文献1参照)。 In response to recent demands for higher density and lower profile of printed wiring boards, a design of a printed circuit board in which a glass substrate is coated with a resin has been proposed (see, for example, Patent Document 1).

このようなプリント配線板においては、樹脂製コア基板の開口内に電子部品を内蔵する場合があり、そのような電子部品は、該電子部品を貫通するスルーホール内に、該電子部品の両面上の導体回路を電気的に接続するスルーホール導体と、そのスルーホール導体の中心部を貫通する貫通孔とを有する場合がある。 In such a printed wiring board, an electronic component may be built in an opening of a resin core substrate, and such an electronic component is placed on both sides of the electronic component in a through hole penetrating the electronic component. It may have a through-hole conductor that electrically connects the conductor circuit of the above, and a through-hole that penetrates the central portion of the through-hole conductor.

そしてこのように樹脂製コア基板の開口内に電子部品を内蔵する際には、その樹脂製コア基板の材料となる層間絶縁材を構成する樹脂をプレスにより加熱および加圧して溶融させ、その樹脂製コア基板の開口内の電子部品の周囲に流し込むことで、その樹脂製コア基板の開口内の電子部品の周囲を樹脂で充填して、電子部品をその開口内に固定するのが通常である。 When an electronic component is built in the opening of the resin core substrate in this way, the resin constituting the interlayer insulating material that is the material of the resin core substrate is heated and pressurized by a press to be melted, and the resin is melted. It is usual to fill the periphery of the electronic component in the opening of the resin core substrate with resin by pouring it around the electronic component in the opening of the core substrate, and fix the electronic component in the opening. ..

特許第6148764号公報Japanese Patent No. 6148764

ところで近年のプリント配線板の小型化に伴い、従来はあらかじめスルーホール導体の貫通孔内に樹脂を充填した電子部品を樹脂製コア基板の開口内に内蔵するが、その貫通孔内に樹脂を充填する工程をプリント配線板の製造過程で行うにあたり、その開口内に内蔵する電子部品も小型化し、その電子部品のスルーホール導体の貫通孔も微細化しているため、樹脂製コア基板の材料となる層間絶縁材の樹脂をプレスにより加熱および加圧して樹脂製コア基板の開口内の電子部品の周囲に流し込む方法では、電子部品用開口と電子部品に設けられた貫通孔を同時に埋めるのは充填体積の比率からして困難となる。このため、スルーホール導体の貫通孔内まで樹脂を充填することはできず、その貫通孔内に空洞が残り、その空洞内の空気がスルーホール導体の腐食の原因となって、電子部品の両面上の導体回路の電気的接続の信頼性を低下させる可能性がある。 By the way, with the recent miniaturization of printed wiring boards, electronic components in which the through holes of through-hole conductors are previously filled with resin are built in the openings of the resin core substrate, but the through holes are filled with resin. In the process of manufacturing the printed wiring board, the electronic component built in the opening is also miniaturized, and the through hole of the through-hole conductor of the electronic component is also miniaturized, so that it can be used as a material for a resin core substrate. In the method in which the resin of the interlayer insulating material is heated and pressed by a press and poured around the electronic component in the opening of the resin core substrate, it is the filling volume that simultaneously fills the opening for the electronic component and the through hole provided in the electronic component. It becomes difficult from the ratio of. For this reason, the resin cannot be filled into the through hole of the through hole conductor, a cavity remains in the through hole, and the air in the cavity causes corrosion of the through hole conductor, so that both sides of the electronic component are both sides. It may reduce the reliability of the electrical connection of the upper conductor circuit.

この発明のプリント配線板は、樹脂製コア基板の開口内に電子部品を内蔵するプリント配線板であって、前記電子部品は、該電子部品を貫通するスルーホール内に、該電子部品の両面上の導体回路を電気的に接続するスルーホール導体と、そのスルーホール導体の中心部を貫通する貫通孔とを有しており、前記開口内の前記電子部品の周囲と前記貫通孔内とに、前記コア基板を構成する樹脂よりも溶融状態での流動性が高い樹脂が充填されている。 The printed wiring board of the present invention is a printed wiring board in which an electronic component is built in an opening of a resin core substrate, and the electronic component is placed on both sides of the electronic component in a through hole penetrating the electronic component. It has a through-hole conductor that electrically connects the conductor circuit of the above, and a through hole that penetrates the central portion of the through-hole conductor, and has a through hole around the electronic component in the opening and in the through hole. It is filled with a resin having higher fluidity in a molten state than the resin constituting the core substrate.

この発明のプリント配線板の製造方法は、樹脂製コア基板の開口内に電子部品を内蔵するプリント配線板を製造するに際し、前記電子部品は、該電子部品を貫通するスルーホール内に、該電子部品の両面上の導体回路を電気的に接続するスルーホール導体と、そのスルーホール導体の中心部を貫通する貫通孔とを有しており、前記開口内の前記電子部品の周囲と前記貫通孔内とに、前記コア基板を構成する樹脂よりも流動性が高い溶融樹脂を充填する。 In the method for manufacturing a printed wiring board of the present invention, when manufacturing a printed wiring board in which an electronic component is incorporated in an opening of a resin core substrate, the electronic component is placed in a through hole penetrating the electronic component. It has a through-hole conductor that electrically connects the conductor circuits on both sides of the component, and a through hole that penetrates the central portion of the through-hole conductor, and has a through hole around the electronic component in the opening and the through hole. The inside is filled with a molten resin having a higher fluidity than the resin constituting the core substrate.

本発明の実施形態によれば、樹脂製コア基板の開口内の前記電子部品の周囲と前記貫通孔内とに、例えば低粘度や小径フィラーの含有等によって前記コア基板を構成する樹脂よりも溶融状態での流動性を高くされて小径や狭いキャビティに対応した樹脂が充填されているため、その貫通孔内に空洞が全く残らないので、電子部品の両面上の導体回路のスルーホール導体による電気的接続の信頼性を向上させることができる。 According to the embodiment of the present invention, the periphery of the electronic component in the opening of the resin core substrate and the inside of the through hole are melted more than the resin constituting the core substrate due to, for example, low viscosity or inclusion of a small diameter filler. Since the fluidity in the state is increased and the resin is filled with a resin corresponding to a small diameter or a narrow cavity, no cavity remains in the through hole, so that electricity is generated by the through-hole conductor of the conductor circuit on both sides of the electronic component. The reliability of the target connection can be improved.

本発明の一実施形態のプリント配線板を示す断面図である。It is sectional drawing which shows the printed wiring board of one Embodiment of this invention. (a)〜(g)は、図1に示される実施形態のプリント配線板の製造方法の各工程を説明する断面図である。(A) to (g) are cross-sectional views illustrating each step of the manufacturing method of the printed wiring board of the embodiment shown in FIG.

以下、図面を参照して本発明に係るプリント配線板の実施形態について説明する。図面の説明において、同様の要素には同一符号を付し、重複説明は省略する。 Hereinafter, embodiments of the printed wiring board according to the present invention will be described with reference to the drawings. In the description of the drawings, similar elements are designated by the same reference numerals, and duplicate description will be omitted.

図1は、本発明の一実施形態に係るプリント配線板を示す断面図であり、図2(a)〜図2(g)は、図1に示される実施形態のプリント配線板の製造方法の各工程を示す断面図である。この実施形態のプリント配線板10は、コア基板12と、ビルドアップ層14とを具える。 FIG. 1 is a cross-sectional view showing a printed wiring board according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (g) show a method for manufacturing a printed wiring board according to the embodiment shown in FIG. It is sectional drawing which shows each process. The printed wiring board 10 of this embodiment includes a core board 12 and a build-up layer 14.

コア基板12は、例えばシリカやアルミナ等の無機フィラーを含有するエポキシ樹脂やBT(ビスマレイミドトリアジン)樹脂等の絶縁性樹脂組成物で構成されており、ガラスクロス等の補強材を含んでいる。コア基板12の表側の面であるF面12Fと、コア基板12の裏側の面であるB面12Bとにはそれぞれ、導体回路層22が形成されている。導体回路層22は、導電性金属、例えば銅で形成される。コア基板12には複数のスルーホール導体24が形成されている。スルーホール導体24は各々、導電性金属、例えば銅で形成され、コア基板12の表側の面であるF面12Fおよび裏側の面であるB面12B上の導体回路層22同士を電気的に接続している。 The core substrate 12 is made of an insulating resin composition such as an epoxy resin containing an inorganic filler such as silica or alumina or a BT (bismaleimide triazine) resin, and contains a reinforcing material such as glass cloth. A conductor circuit layer 22 is formed on each of the F surface 12F, which is the front surface of the core substrate 12, and the B surface 12B, which is the back surface of the core substrate 12. The conductor circuit layer 22 is made of a conductive metal such as copper. A plurality of through-hole conductors 24 are formed on the core substrate 12. Each of the through-hole conductors 24 is made of a conductive metal such as copper, and electrically connects the conductor circuit layers 22 on the F surface 12F, which is the front surface of the core substrate 12, and the B surface 12B, which is the back surface. are doing.

コア基板12は、中央部に矩形の開口を画成する部品収容部26を有し、部品収容部26は、コア基板12をその厚み方向に貫通する貫通孔からなる。部品収容部26には、例えばICチップや回路基板を構成するガラス基板等の電子部品28が収容されている。電子部品28の表側の面であるF面28Fと、電子部品28の裏側の面であるB面28Bとにはそれぞれ、導体回路層30が形成されている。導体回路層30は、導電性金属、例えば銅で形成される。電子部品28は、その電子部品28をその厚み方向に貫通する例えば複数のスルーホールを有し、各スルーホールの内周面上には円筒状のスルーホール導体32が形成されている。スルーホール導体32は各々、導電性金属、例えば銅で形成され、電子部品28のF面28FおよびB面28B上の導体回路層30同士を電気的に接続している。各スルーホール導体32の中心部には微細な貫通孔34が形成されている。 The core substrate 12 has a component accommodating portion 26 defining a rectangular opening in the central portion, and the component accommodating portion 26 includes a through hole penetrating the core substrate 12 in the thickness direction thereof. The component accommodating portion 26 accommodates electronic components 28 such as an IC chip and a glass substrate constituting a circuit board. A conductor circuit layer 30 is formed on each of the F surface 28F, which is the front surface of the electronic component 28, and the B surface 28B, which is the back surface of the electronic component 28. The conductor circuit layer 30 is made of a conductive metal such as copper. The electronic component 28 has, for example, a plurality of through holes that penetrate the electronic component 28 in the thickness direction thereof, and a cylindrical through-hole conductor 32 is formed on the inner peripheral surface of each through hole. Each of the through-hole conductors 32 is made of a conductive metal such as copper, and electrically connects the conductor circuit layers 30 on the F surface 28F and the B surface 28B of the electronic component 28. A fine through hole 34 is formed in the center of each through-hole conductor 32.

ビルドアップ層14は、コア基板12のF面12F上およびB面12B上にそれぞれ形成されている。ビルドアップ層14は、層間絶縁層36と導体回路層38とを交互に積層してなる。層間絶縁層36は、例えばシリカやアルミナ等の無機フィラーを含有するエポキシ樹脂やBT(ビスマレイミドトリアジン)樹脂等の樹脂組成物からなる。層間絶縁層36は、好ましくは、ガラスクロス等の補強材を含んでいる。導体回路層38は、導電性金属、例えば銅で形成される。 The build-up layer 14 is formed on the F surface 12F and the B surface 12B of the core substrate 12, respectively. The build-up layer 14 is formed by alternately laminating the interlayer insulating layer 36 and the conductor circuit layer 38. The interlayer insulating layer 36 is made of a resin composition such as an epoxy resin containing an inorganic filler such as silica or alumina or a BT (bismaleimide triazine) resin. The interlayer insulating layer 36 preferably contains a reinforcing material such as a glass cloth. The conductor circuit layer 38 is made of a conductive metal such as copper.

部品収容部26内の電子部品28の周囲の隙間およびスルーホール導体32の貫通孔34内には、コア基板12を構成する絶縁性樹脂組成物とは別組成の、層間絶縁層36を構成する絶縁性樹脂組成物と同じ組成の絶縁性樹脂40が充填されて固化しており、この絶縁性樹脂40が、電子部品28を部品収容部26内の所定位置に固定するとともに、スルーホール導体32と空気との接触を遮ってスルーホール導体32の腐食を防止している。この絶縁性樹脂40は、好ましくは例えばシリカやアルミナ等の無機フィラーを含有する。 An interlayer insulating layer 36 having a composition different from that of the insulating resin composition constituting the core substrate 12 is formed in the gap around the electronic component 28 in the component accommodating portion 26 and in the through hole 34 of the through-hole conductor 32. An insulating resin 40 having the same composition as the insulating resin composition is filled and solidified, and the insulating resin 40 fixes the electronic component 28 at a predetermined position in the component accommodating portion 26 and the through-hole conductor 32. The through-hole conductor 32 is prevented from corroding by blocking the contact between the conductor and the air. The insulating resin 40 preferably contains an inorganic filler such as silica or alumina.

コア基板12のF面12F上およびB面12B上のビルドアップ層14の導体回路層38は、コア基板12のF面12FおよびB面12B上の導体回路層22に、それらのビルドアップ層14の層間絶縁層36を貫通するバイアホール導体42を介してそれぞれ電気的に接続されている。F面12F上のビルドアップ層14の導体回路層38はまた、コア基板12の部品収容部26内の電子部品28のF面28F上の導体回路層30に、そのビルドアップ層14のバイアホール導体42を介して電気的に接続されている。バイアホール導体42は、導体回路層22、導体回路層30および導体回路層38と同じ導電性金属、例えば銅で形成することができる。 The conductor circuit layer 38 of the build-up layer 14 on the F surface 12F and the B surface 12B of the core substrate 12 is formed on the conductor circuit layer 22 on the F surface 12F and the B surface 12B of the core substrate 12. They are electrically connected to each other via a via hole conductor 42 penetrating the interlayer insulating layer 36 of the above. The conductor circuit layer 38 of the build-up layer 14 on the F surface 12F also has a via hole of the build-up layer 14 in the conductor circuit layer 30 on the F surface 28F of the electronic component 28 in the component accommodating portion 26 of the core substrate 12. It is electrically connected via a conductor 42. The via hole conductor 42 can be formed of the same conductive metal as the conductor circuit layer 22, the conductor circuit layer 30, and the conductor circuit layer 38, for example, copper.

この実施形態のプリント配線板10によれば、部品収容部26内に内蔵された電子部品28を例えばインターポーザとして、この実施形態のプリント配線板10上にフリップチップ実装される複数のICチップのピッチの異なる電極同士や、それらのICチップの電極とビルドアップ層14の導体回路層38の電極パッドとの間の電気的接続に使用することができる。また、部品収容部26内に内蔵された電子部品28の周囲とその電子部品28のスルーホール導体32の貫通孔34内とに充填された、コア基板12を構成する絶縁性樹脂組成物とは別組成の、層間絶縁層36を構成する絶縁性樹脂組成物と同じ絶縁性樹脂40が固化しているので、部品収容部26内で電子部品28を精度良く位置決め固定できるとともに、電子部品28の両面上の導体回路層30のスルーホール導体32による電気的接続の信頼性を向上させることができる。 According to the printed wiring board 10 of this embodiment, the pitch of a plurality of IC chips mounted on the printed wiring board 10 of this embodiment by using the electronic component 28 built in the component accommodating portion 26 as an interposer, for example. It can be used for electrical connection between different electrodes or between the electrodes of those IC chips and the electrode pads of the conductor circuit layer 38 of the build-up layer 14. Further, what is the insulating resin composition constituting the core substrate 12 filled in the periphery of the electronic component 28 built in the component accommodating portion 26 and in the through hole 34 of the through-hole conductor 32 of the electronic component 28? Since the same insulating resin 40 as the insulating resin composition constituting the interlayer insulating layer 36 having a different composition is solidified, the electronic component 28 can be accurately positioned and fixed in the component accommodating portion 26, and the electronic component 28 can be positioned and fixed. The reliability of the electrical connection by the through-hole conductor 32 of the conductor circuit layer 30 on both sides can be improved.

次に、本発明のプリント配線板の製造方法の一実施形態が、図2(a)〜図2(g)を参照して説明される。図1で説明された要素と同様の要素には、同じ符号が付され、適宜説明が省略される。 Next, an embodiment of the method for manufacturing a printed wiring board of the present invention will be described with reference to FIGS. 2 (a) and 2 (g). Elements similar to those described in FIG. 1 are designated by the same reference numerals, and description thereof will be omitted as appropriate.

(1)先ず、図2(a)に示されるようなコア基板12の材料として、エポキシ樹脂又はBT(ビスマレイミドトリアジン)樹脂とガラスクロスなどの補強材とからなる絶縁性基材の表裏両面が銅箔でラミネートされたものが用意される。 (1) First, as the material of the core substrate 12 as shown in FIG. 2A, both the front and back surfaces of an insulating base material made of an epoxy resin or BT (bismaleimide triazine) resin and a reinforcing material such as glass cloth are used. Those laminated with copper foil are prepared.

(2)次いで、その絶縁性基材の表面側から例えば炭酸ガスレーザの照射、もしくはメカニカルドリルでの孔加工が適用されて、スルーホール導体用貫通孔を形成するための孔が穿孔される。また、絶縁性基材の裏面側のうち前述した表面の孔の真裏となる位置に例えば炭酸ガスレーザの照射、もしくはメカニカルドリルでの孔加工が適用されて孔が穿孔され、それら表面および裏面の孔同士が繋がることで、スルーホール導体24用の貫通孔を有するコア基板12が形成される。また、そのコア基板12の中央部には、例えば炭酸ガスレーザの照射、もしくはメカニカルドリルでの孔加工により、矩形の開口を持つ貫通孔としての部品収容部26が形成される。 (2) Next, irradiation with a carbon dioxide gas laser or hole processing with a mechanical drill is applied from the surface side of the insulating base material to drill holes for forming through holes for through-hole conductors. Further, on the back surface side of the insulating base material, holes are drilled by applying, for example, carbon dioxide laser irradiation or hole processing with a mechanical drill to the positions directly behind the holes on the front surface, and the holes on the front surface and the back surface thereof. By connecting them to each other, a core substrate 12 having a through hole for the through-hole conductor 24 is formed. Further, in the central portion of the core substrate 12, a component accommodating portion 26 as a through hole having a rectangular opening is formed by, for example, irradiation with a carbon dioxide gas laser or hole processing with a mechanical drill.

(3)次いで、無電解めっき処理が行われ、コア基板12の表側の面であるF面12Fおよび裏側の面であるB面12Bの銅箔上と貫通孔の内周面とに無電解めっき膜が形成される。そして銅箔上の無電解めっき膜上に、所定パターンのめっきレジストが形成され、そのめっきレジストは、部品収容部26を覆っているが、スルーホール導体用貫通孔は露出させている。 (3) Next, electroless plating is performed on the copper foil of the F surface 12F, which is the front surface of the core substrate 12, and the B surface 12B, which is the back surface, and the inner peripheral surface of the through hole. A film is formed. Then, a plating resist having a predetermined pattern is formed on the electroless plating film on the copper foil, and the plating resist covers the component accommodating portion 26, but the through holes for the through-hole conductor are exposed.

(4)次いで、電解めっき処理が行われ、電解めっきがスルーホール導体用貫通孔内に充填されてスルーホール導体24が形成されて後に、銅箔上の無電解めっき膜のうちめっきレジストから露出している部分に電解めっき膜が形成される。その後、めっきレジストが剥離されるとともにめっきレジストの下方の無電解めっき膜及び銅箔が除去され、残された電解めっき膜と無電解めっき膜と銅箔とにより、コア基板12のF面12FおよびB面12B上に導体回路層22がそれぞれ形成される。コア基板12のF面12FおよびB面12B上の導体回路層22は、スルーホール導体24によって互いに電気的に接続されている。 (4) Next, an electrolytic plating process is performed, the electrolytic plating is filled in the through holes for the through-hole conductor to form the through-hole conductor 24, and then the electroplating film on the copper foil is exposed from the plating resist. An electroplating film is formed on the part where it is formed. After that, the plating resist is peeled off, the electroless plating film and the copper foil below the plating resist are removed, and the remaining electrolytic plating film, the electroless plating film, and the copper foil form the F surface 12F of the core substrate 12 and the copper foil. The conductor circuit layer 22 is formed on the B surface 12B, respectively. The conductor circuit layers 22 on the F surface 12F and the B surface 12B of the core substrate 12 are electrically connected to each other by the through-hole conductor 24.

(5)しかる後、図2(a)に示されるように、例えば粘着性を有するフィルムからなるテープ44が、図では下向きとされている上記のコア基板12のB面12B側の導体回路層22上に、部品収容部26を塞ぐように張り付けられる。次いで、プリント配線板10の部品収容部26内に内蔵されるべき電子部品28が準備され、その電子部品28がマウンタ(図示せず)によって部品収容部26の所定位置に配置される。 (5) After that, as shown in FIG. 2A, for example, the tape 44 made of an adhesive film is the conductor circuit layer on the B side 12B side of the core substrate 12 which is downward in the drawing. It is attached on the 22 so as to close the component accommodating portion 26. Next, an electronic component 28 to be incorporated in the component accommodating portion 26 of the printed wiring board 10 is prepared, and the electronic component 28 is arranged at a predetermined position of the component accommodating portion 26 by a mounter (not shown).

(6)電子部品28も、例えばコア基板12と同様にして、表側の面であるF面28Fおよび裏側の面であるB面28B上に導体回路層30とされる導体層がそれぞれ形成される。電子部品28のF面28FおよびB面28B上の導体層は、スルーホール導体32によって互いに電気的に接続されている。また、各スルーホール導体32の中心部には電子部品28のF面28F側からB面28B側まで貫通する微細な貫通孔34が形成されている。 (6) In the electronic component 28 as well, for example, similarly to the core substrate 12, a conductor layer to be a conductor circuit layer 30 is formed on the F surface 28F which is the front side surface and the B surface 28B which is the back side surface, respectively. .. The conductor layers on the F surface 28F and the B surface 28B of the electronic component 28 are electrically connected to each other by the through-hole conductor 32. Further, a fine through hole 34 penetrating from the F surface 28F side to the B surface 28B side of the electronic component 28 is formed in the central portion of each through hole conductor 32.

(7)次いで、このテープ44上のコア基板12とその部品収容部26内に配置された電子部品28とが、その部品収容部26のみを露出させる図示しない印刷用版を被せられてコア基板12のF面12Fを全体的に覆われ、その状態で次に、コア基板12を構成する絶縁性樹脂組成物とは別組成の、層間絶縁層36を構成する絶縁性樹脂組成物と同じ組成の溶融状態の絶縁性樹脂材料が例えば印刷塗布により選択的に部品収容部26内に供給されて、減圧により部品収容部26内の電子部品28の周囲およびスルーホール導体32の中心部の貫通孔34内に密に充填される。充填の際の減圧レベルを−5Pa〜−10,000Paとするとともに、溶融樹脂の粘度を、コア基板12の絶縁性樹脂組成物の溶融状態よりも流動性が高い、100Pa・s〜1,000Pa・sとすると、貫通孔34内への溶融樹脂の充填が確実に行われる。さらに、溶融樹脂が含有するフィラーは、コア基板12の絶縁性樹脂組成物が含有するフィラーより小径の、中心粒径が0.1μm〜15μmのものであると、貫通孔34内への溶融樹脂の充填がより確実に行われる。 (7) Next, the core substrate 12 on the tape 44 and the electronic component 28 arranged in the component accommodating portion 26 are covered with a printing plate (not shown) that exposes only the component accommodating portion 26, and the core substrate. The F surface 12F of 12 is totally covered, and in that state, the composition is the same as that of the insulating resin composition constituting the interlayer insulating layer 36, which is different from the insulating resin composition constituting the core substrate 12. The insulated resin material in the molten state is selectively supplied into the component housing 26 by, for example, printing and coating, and through holes around the electronic component 28 in the component housing 26 and in the center of the through-hole conductor 32 due to reduced pressure. It is densely filled in 34. The reduced pressure level at the time of filling is -5 Pa to -10000 Pa, and the viscosity of the molten resin is 100 Pa · s to 1,000 Pa, which is higher in fluidity than the molten state of the insulating resin composition of the core substrate 12. When s is set, the molten resin is surely filled in the through hole 34. Further, when the filler contained in the molten resin has a smaller diameter than the filler contained in the insulating resin composition of the core substrate 12 and a central particle size of 0.1 μm to 15 μm, the molten resin into the through hole 34 Filling is done more reliably.

(8)その後、部品収容部26内の電子部品28の周囲およびスルーホール導体32の中心部の貫通孔34内に充填された溶融樹脂が硬化し、図2(b)に示されるように、その硬化した絶縁性樹脂が、電子部品28を部品収容部26内の所定位置に精度良く位置決め固定するとともに、スルーホール導体32の中心部の貫通孔34の内周面と空気との接触を遮断する。 (8) After that, the molten resin filled around the electronic component 28 in the component accommodating portion 26 and in the through hole 34 at the center of the through-hole conductor 32 is cured, and as shown in FIG. 2B, The cured insulating resin accurately positions and fixes the electronic component 28 at a predetermined position in the component accommodating portion 26, and blocks contact between the inner peripheral surface of the through hole 34 at the center of the through-hole conductor 32 and air. To do.

(9)次いで、図2(c)に示されるように、コア基板12とその部品収容部26内に配置された電子部品28とからテープ44が剥離される。 (9) Next, as shown in FIG. 2C, the tape 44 is peeled off from the core substrate 12 and the electronic component 28 arranged in the component accommodating portion 26 thereof.

(10)次いで、図2(d)に示されるように、コア基板12のF面12F上およびB面12B上の導体回路層22と、電子部品28のF面28F上およびB面28B上の導体層とが例えばエッチングにより除去される。また、コア基板12のF面12FおよびB面12Bから突出する樹脂および電子部品28のF面28FおよびB面28Bから突出する樹脂が例えば切削や研削等により除去され、コア基板12のF面12Fおよび電子部品28のF面28Fは平坦かつ面一にされ、コア基板12のB面12Bおよび電子部品28のB面28Bも平坦かつ面一にされる。 (10) Next, as shown in FIG. 2D, the conductor circuit layer 22 on the F surface 12F and the B surface 12B of the core substrate 12 and the electronic component 28 on the F surface 28F and the B surface 28B. The conductor layer is removed by, for example, etching. Further, the resin protruding from the F surface 12F and the B surface 12B of the core substrate 12 and the resin protruding from the F surface 28F and the B surface 28B of the electronic component 28 are removed by, for example, cutting or grinding, and the F surface 12F of the core substrate 12 is removed. The F surface 28F of the electronic component 28 is also flat and flush, and the B surface 12B of the core substrate 12 and the B surface 28B of the electronic component 28 are also flat and flush.

(11)次いで、図2(e)に示されるように、コア基板12のF面12F上およびB面12B上と、電子部品28のF面28F上およびB面28B上とに、電解めっきによる導体回路層の形成のためのシード層となる無電解めっき膜46が形成される。 (11) Next, as shown in FIG. 2E, the core substrate 12 is electroplated on the F surface 12F and the B surface 12B, and on the F surface 28F and the B surface 28B of the electronic component 28. The electroless plating film 46 serving as a seed layer for forming the conductor circuit layer is formed.

(12)次いで、図2(f)に示されるように、セミアディティブ法により、コア基板12のF面12F上およびB面12B上と、電子部品28のF面28F上およびB面28B上との無電解めっき膜46上にそれぞれ所定パターンのめっきレジストが形成され、次に、電解めっき処理が行われ、無電解めっき膜46のうちめっきレジストから露出している部分に電解めっき膜が形成される。その後、めっきレジストが剥離されるとともにめっきレジストの下方の無電解めっき膜が除去され、残された電解めっき膜と無電解めっき膜とにより、コア基板12のF面12FおよびB面12B上に導体回路層22がそれぞれ形成されるとともに、電子部品28のF面28F上およびB面28B上にも導体回路層30がそれぞれ形成される。 (12) Next, as shown in FIG. 2 (f), by the semi-additive method, on the F surface 12F and the B surface 12B of the core substrate 12, and on the F surface 28F and the B surface 28B of the electronic component 28. A predetermined pattern of plating resist is formed on each of the electroless plating films 46, and then an electrolytic plating process is performed to form an electrolytic plating film on a portion of the electroless plating film 46 exposed from the plating resist. To. After that, the plating resist is peeled off and the electroless plating film below the plating resist is removed, and the remaining electrolytic plating film and the electroless plating film form a conductor on the F surface 12F and the B surface 12B of the core substrate 12. The circuit layer 22 is formed, and the conductor circuit layer 30 is also formed on the F surface 28F and the B surface 28B of the electronic component 28, respectively.

(13)次いで、図2(g)に示されるように、図では上向きとされているコア基板12のF面12F側の導体回路層22上および電子部品28のF面28F側の導体回路層30上に、層間絶縁層36を形成するための、ガラスクロス等の補強材にエポキシ樹脂やBT樹脂等の絶縁性樹脂が含浸したBステージのプリプレグ48が積層され、そのプリプレグ48上に銅箔(図示せず)が積層され、その後、プリプレグ48とその上の銅箔とが加熱プレスされる。 (13) Next, as shown in FIG. 2 (g), the conductor circuit layer on the F surface 12F side conductor circuit layer 22 of the core substrate 12 and the F surface 28F side of the electronic component 28, which are upward in the figure. A B-stage prepreg 48 in which an insulating resin such as epoxy resin or BT resin is impregnated with a reinforcing material such as glass cloth for forming an interlayer insulating layer 36 is laminated on the prepreg 48, and a copper foil is placed on the prepreg 48. (Not shown) are laminated, after which the prepreg 48 and the copper foil on it are heat pressed.

(14)次いで、上記と同様にして、図では下向きとされているコア基板12のB面12B側の導体回路層22上および電子部品28のB面28B側の導体回路層30上にも、層間絶縁層36を形成するための、ガラスクロス等の補強材にエポキシ樹脂やBT樹脂等の絶縁性樹脂が含浸したBステージのプリプレグ48が積層され、そのプリプレグ48上に銅箔(図示せず)が積層され、その後、プリプレグ48とその上の銅箔とが加熱プレスされる。なお、コア基板12のF面12F側およびB面12B側の少なくとも一方のプリプレグ48に替えて、ガラスクロス等の補強材無しの絶縁性樹脂材料を適用することも可能である。 (14) Next, in the same manner as described above, on the conductor circuit layer 22 on the B surface 12B side of the core substrate 12 and on the conductor circuit layer 30 on the B surface 28B side of the electronic component 28, which are oriented downward in the drawing. A B-stage prepreg 48 impregnated with an insulating resin such as epoxy resin or BT resin is laminated on a reinforcing material such as glass cloth for forming the interlayer insulating layer 36, and a copper foil (not shown) is laminated on the prepreg 48. ) Are laminated, and then the prepreg 48 and the copper foil on it are heat-pressed. It is also possible to apply an insulating resin material without a reinforcing material such as glass cloth instead of at least one prepreg 48 on the F surface 12F side and the B surface 12B side of the core substrate 12.

(15)このようにしてプリプレグ48の樹脂成分が加熱プレスにより固化されて、コア基板12のF面12Fおよび電子部品28のF面28F上に層間絶縁層36が形成されるとともにコア基板12のB面12B上および電子部品28のB面28B上にも層間絶縁層36が形成された後、それらの層間絶縁層36上の銅箔の上から所定の位置に例えば炭酸ガスレーザが照射され、銅箔および層間絶縁層36を貫くバイアホールが形成される。バイアホールは、導体回路層22および導体回路層30を部分的に露出させる。 (15) In this way, the resin component of the prepreg 48 is solidified by a heating press to form an interlayer insulating layer 36 on the F surface 12F of the core substrate 12 and the F surface 28F of the electronic component 28, and the core substrate 12 is formed. After the interlayer insulating layer 36 is also formed on the B surface 12B and the B surface 28B of the electronic component 28, for example, a carbon dioxide gas laser is irradiated to a predetermined position from above the copper foil on the interlayer insulating layer 36 to copper. Via holes are formed through the foil and the interlayer insulating layer 36. The via hole partially exposes the conductor circuit layer 22 and the conductor circuit layer 30.

(16)次いで、それらの層間絶縁層36上の銅箔の上に、例えばフォトリソグラフィ法によって、上記バイアホールの位置に加えて導体回路層22および導体回路層30が形成される位置に開口を有するめっきレジストが形成される。 (16) Next, an opening is opened on the copper foil on the interlayer insulating layer 36 at a position where the conductor circuit layer 22 and the conductor circuit layer 30 are formed in addition to the position of the via hole by, for example, a photolithography method. The plating resist to have is formed.

(17)次いで、上記めっきレジストの開口およびバイアホールの内面上に、例えば無電解めっき処理により金属膜(図示せず)が形成される。金属膜は、スパッタリングや真空蒸着により形成されてもよい。この金属膜をシード層とした電解めっき処理により、バイアホール導体42および銅箔上のめっき膜が形成される。電解めっき処理は、好ましくは、電解銅めっき処理である。その後、めっきレジストは剥離により除去される。 (17) Next, a metal film (not shown) is formed on the inner surface of the opening and the via hole of the plating resist by, for example, electroless plating. The metal film may be formed by sputtering or vacuum deposition. By the electrolytic plating treatment using this metal film as a seed layer, a plating film on the via hole conductor 42 and the copper foil is formed. The electrolytic plating treatment is preferably an electrolytic copper plating treatment. After that, the plating resist is removed by peeling.

(18)次いで、表面にめっき膜が形成されていない銅箔の部分がエッチングにより除去される。これによりコア基板12のF面12FおよびB面12B上並びに電子部品28のF面28FおよびB面28B上の層間絶縁層36上に、銅箔およびめっき膜からなる導体回路層38が形成される。図1に示されるように、層間絶縁層36上の導体回路層38はバイアホール導体42によって、コア基板12のF面12FおよびB面12B上の導体回路層22に電気的に接続されるとともに、部品収容部26内の電子部品28のF面28F上の導体回路層30にも電気的に接続されている。 (18) Next, the portion of the copper foil on which the plating film is not formed on the surface is removed by etching. As a result, a conductor circuit layer 38 made of a copper foil and a plating film is formed on the interlayer insulating layer 36 on the F surface 12F and the B surface 12B of the core substrate 12 and on the F surface 28F and the B surface 28B of the electronic component 28. .. As shown in FIG. 1, the conductor circuit layer 38 on the interlayer insulating layer 36 is electrically connected to the conductor circuit layer 22 on the F surface 12F and the B surface 12B of the core substrate 12 by the via hole conductor 42. , It is also electrically connected to the conductor circuit layer 30 on the F surface 28F of the electronic component 28 in the component accommodating portion 26.

本発明は、上記実施形態に限定されず、請求の範囲の記載から逸脱しない範囲で種々の変更、修正が可能である。例えば、図1に示される実施形態のプリント配線板および図2(a)〜(g)に示される実施形態のプリント配線板の製造方法では、コア基板の表面および裏面上に、層間絶縁層を有する1層のビルドアップ層を具えているが、本発明のプリント配線板および本発明のプリント配線板の製造方法はこれに限られず、コア基板の表面および裏面の少なくとも一方の上に、各々層間絶縁層を有する2層以上のビルドアップ層を具えるものでも良い。 The present invention is not limited to the above embodiment, and various modifications and modifications can be made without departing from the description of the claims. For example, in the method for manufacturing the printed wiring board of the embodiment shown in FIG. 1 and the printed wiring board of the embodiment shown in FIGS. 2 (a) to 2 (g), an interlayer insulating layer is provided on the front surface and the back surface of the core substrate. Although it has one build-up layer, the method for manufacturing the printed wiring board of the present invention and the printed wiring board of the present invention is not limited to this, and each layer is placed on at least one of the front surface and the back surface of the core substrate. It may include two or more build-up layers having an insulating layer.

10 プリント配線板
12 コア基板
12F 表側の面(F面)
12B 裏側の面(B面)
14 ビルドアップ層
22 導体回路層
24 スルーホール導体
26 部品収容部
28 電子部品
28F 表側の面(F面)
28B 裏側の面(B面)
30 導体回路層
32 スルーホール導体
34 貫通孔
36 層間絶縁層
38 導体回路層
40 絶縁性樹脂
42 バイアホール導体
44 テープ
46 無電解めっき膜
48 プリプレグ
10 Printed circuit board 12 Core board 12F Front side (F side)
12B back side (B side)
14 Build-up layer 22 Conductor circuit layer 24 Through-hole conductor 26 Parts housing 28 Electronic components 28F Front side surface (F surface)
28B back side (B side)
30 Conductor circuit layer 32 Through-hole conductor 34 Through hole 36 Interlayer insulation layer 38 Conductor circuit layer 40 Insulation resin 42 Viahole conductor 44 Tape 46 Electrolytic plating film 48 Prepreg

Claims (6)

樹脂製コア基板の開口内に電子部品を内蔵するプリント配線板であって、
前記電子部品は、該電子部品を貫通するスルーホール内に、該電子部品の両面上の導体回路を電気的に接続するスルーホール導体と、そのスルーホール導体の中心部を貫通する貫通孔とを有しており、
前記開口内の前記電子部品の周囲と前記貫通孔内とに、前記コア基板を構成する樹脂よりも溶融状態での流動性が高い樹脂が充填されている。
A printed wiring board with electronic components built into the openings of a resin core board.
The electronic component has a through-hole conductor that electrically connects conductor circuits on both sides of the electronic component and a through-hole that penetrates the center of the through-hole conductor in the through-hole that penetrates the electronic component. Have and
The periphery of the electronic component and the inside of the through hole in the opening are filled with a resin having a higher fluidity in a molten state than the resin constituting the core substrate.
樹脂製コア基板の開口内にガラス基板を内蔵するプリント配線板の製造方法において、
前記ガラス基板は、該ガラス基板を貫通するスルーホール内に、該ガラス基板の両面上の導体回路を電気的に接続するスルーホール導体と、そのスルーホール導体の中心部を貫通する貫通孔とを有しており、
前記開口内の前記ガラス基板の周囲と前記貫通孔内とに、前記コア基板を構成する樹脂の溶融状態よりも流動性が高い溶融樹脂を充填する。
In the method of manufacturing a printed wiring board in which a glass substrate is built in an opening of a resin core substrate,
The glass substrate has a through-hole conductor that electrically connects conductor circuits on both sides of the glass substrate and a through-hole that penetrates the center of the through-hole conductor in a through-hole that penetrates the glass substrate. Have and
The periphery of the glass substrate and the inside of the through hole in the opening are filled with a molten resin having a higher fluidity than the molten state of the resin constituting the core substrate.
請求項2記載のプリント配線板の製造方法であって、
前記溶融樹脂は、前記コア基板を構成する樹脂と別組成で、前記コア基板上に積層される層間絶縁層を構成する樹脂と同一組成のものである。
The method for manufacturing a printed wiring board according to claim 2.
The molten resin has a composition different from that of the resin constituting the core substrate, and has the same composition as the resin constituting the interlayer insulating layer laminated on the core substrate.
請求項2または3記載のプリント配線板の製造方法であって、
前記溶融樹脂の粘度は、100Pa・s〜1,000Pa・sである。
The method for manufacturing a printed wiring board according to claim 2 or 3.
The viscosity of the molten resin is 100 Pa · s to 1,000 Pa · s.
請求項2から4までの何れか1項記載のプリント配線板の製造方法であって、
前記溶融樹脂は、印刷法もしくはフィルムラミネートによって前記開口内に充填される。
The method for manufacturing a printed wiring board according to any one of claims 2 to 4.
The molten resin is filled in the opening by a printing method or a film laminate.
請求項2から5までの何れか1項記載のプリント配線板の製造方法であって、
前記溶融樹脂は、中心粒径が0.1μm〜15μmのフィラーを含んでいる。
The method for manufacturing a printed wiring board according to any one of claims 2 to 5.
The molten resin contains a filler having a center particle size of 0.1 μm to 15 μm.
JP2019045470A 2019-03-13 2019-03-13 Printed wiring board and manufacturing method thereof Active JP7184679B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2019045470A JP7184679B2 (en) 2019-03-13 2019-03-13 Printed wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019045470A JP7184679B2 (en) 2019-03-13 2019-03-13 Printed wiring board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2020150094A true JP2020150094A (en) 2020-09-17
JP7184679B2 JP7184679B2 (en) 2022-12-06

Family

ID=72429872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019045470A Active JP7184679B2 (en) 2019-03-13 2019-03-13 Printed wiring board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP7184679B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022049861A1 (en) 2020-09-07 2022-03-10 昭和電工マテリアルズ株式会社 Laminated structure and object detection structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339482A (en) * 2005-06-03 2006-12-14 Ngk Spark Plug Co Ltd Wiring board and its manufacturing method
JP2013074178A (en) * 2011-09-28 2013-04-22 Ngk Spark Plug Co Ltd Method for manufacturing wiring board with built-in component
JP2013219191A (en) * 2012-04-09 2013-10-24 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339482A (en) * 2005-06-03 2006-12-14 Ngk Spark Plug Co Ltd Wiring board and its manufacturing method
JP2013074178A (en) * 2011-09-28 2013-04-22 Ngk Spark Plug Co Ltd Method for manufacturing wiring board with built-in component
JP2013219191A (en) * 2012-04-09 2013-10-24 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022049861A1 (en) 2020-09-07 2022-03-10 昭和電工マテリアルズ株式会社 Laminated structure and object detection structure

Also Published As

Publication number Publication date
JP7184679B2 (en) 2022-12-06

Similar Documents

Publication Publication Date Title
JP4767269B2 (en) Method for manufacturing printed circuit board
US8945329B2 (en) Printed wiring board and method for manufacturing printed wiring board
JP5955023B2 (en) Printed wiring board with built-in component and manufacturing method thereof
KR100990546B1 (en) A printed circuit board comprising a plating-pattern buried in via and a method of manufacturing the same
JP2010135721A (en) Printed circuit board comprising metal bump and method of manufacturing the same
JP2010135720A (en) Printed circuit board comprising metal bump and method of manufacturing the same
KR100747022B1 (en) Imbedded circuit board and fabricating method therefore
JP2004134679A (en) Core substrate, manufacturing method thereof, and multilayer wiring board
KR100752017B1 (en) Manufacturing Method of Printed Circuit Board
JP7184679B2 (en) Printed wiring board and manufacturing method thereof
JP5432800B2 (en) Wiring board manufacturing method
KR20120046602A (en) Printed circuit board and method for manufacturing the same
JP4219541B2 (en) Wiring board and method of manufacturing wiring board
JP2004200412A (en) Wiring board with solder bump, and manufacturing method thereof
JP7278114B2 (en) Method for manufacturing printed wiring board
JP3694708B2 (en) Printed wiring board manufacturing method and printed wiring board
JP5565951B2 (en) Wiring board and manufacturing method thereof
KR100658437B1 (en) Pcb and it's manufacturing method used bump board
JP3955799B2 (en) Wiring board manufacturing method
JP2001015912A (en) Multilayered printed wiring board and production thereof
JP2002185139A (en) Printed wiring board and its manufacturing method
JP3582645B2 (en) Manufacturing method of three-dimensional wiring board
JP3610769B2 (en) Multi-layer electronic component mounting board
KR100807487B1 (en) Method of fabricating printed circuit board
JP2009290044A (en) Wiring substrate

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220105

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20221028

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20221101

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20221124

R150 Certificate of patent or registration of utility model

Ref document number: 7184679

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150