JP2020043307A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2020043307A
JP2020043307A JP2018171821A JP2018171821A JP2020043307A JP 2020043307 A JP2020043307 A JP 2020043307A JP 2018171821 A JP2018171821 A JP 2018171821A JP 2018171821 A JP2018171821 A JP 2018171821A JP 2020043307 A JP2020043307 A JP 2020043307A
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trench
insulating film
semiconductor substrate
gate insulating
curvature
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仁志 藤岡
Hitoshi Fujioka
仁志 藤岡
恵太 片岡
Keita Kataoka
恵太 片岡
泰 浦上
Yasushi Uragami
泰 浦上
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

To suppress a gate leakage current in a semiconductor device in which a trench is bent on the surface of a semiconductor substrate.SOLUTION: A semiconductor device includes a semiconductor substrate, a trench provided on the surface of the semiconductor substrate, a gate insulating film covering an inner surface of the trench, a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. When the surface of the semiconductor substrate is viewed in a plan view, the trench is meandering. When the surface of the semiconductor substrate is viewed in plan view, a radius of curvature of a side surface of the trench is 900 nm or more.SELECTED DRAWING: Figure 2

Description

本明細書に開示の技術は、半導体装置に関する。   The technology disclosed in this specification relates to a semiconductor device.

特許文献１には、トレンチゲート型の半導体装置が開示されている。この半導体装置は、トレンチの内面を覆うゲート絶縁膜と、トレンチ内に配置されているとともにゲート絶縁膜によって半導体基板から絶縁されたゲート電極を有している。半導体基板の表面を平面視したときに、トレンチが、折れ線状に曲がっている。このようにトレンチが曲がっていることで、チャネル密度が高くなる。   Patent Literature 1 discloses a trench gate type semiconductor device. This semiconductor device has a gate insulating film covering the inner surface of the trench, and a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. When the surface of the semiconductor substrate is viewed in a plan view, the trench is bent in a polygonal line shape. Such a bent trench increases the channel density.

特開２００７−１３４５００号公報JP 2007-134500 A

特許文献１のようにトレンチが曲がっていると、トレンチの側面に凸状部が形成される。凸状部を有するトレンチの側面にゲート絶縁膜を形成すると、凸状部においてゲート絶縁膜が薄くなる。このため、ゲート絶縁膜が薄い部分でゲートリーク電流が生じ易い。したがって、本明細書では、半導体基板の表面においてトレンチが曲がっていると共に、ゲートリーク電流が生じ難い半導体装置を提案する。   When the trench is bent as in Patent Document 1, a convex portion is formed on the side surface of the trench. When the gate insulating film is formed on the side surface of the trench having the convex portion, the gate insulating film in the convex portion becomes thin. Therefore, a gate leak current is likely to occur in a portion where the gate insulating film is thin. Therefore, this specification proposes a semiconductor device in which a trench is bent on a surface of a semiconductor substrate and a gate leakage current is less likely to occur.

本明細書が開示する半導体装置は、半導体基板と、半導体基板の表面に設けられたトレンチと、前記トレンチの内面を覆うゲート絶縁膜と、前記トレンチ内に配置されているとともに前記ゲート絶縁膜によって前記半導体基板から絶縁されたゲート電極を有している。前記半導体基板の前記表面を平面視したときに、前記トレンチが蛇行している。前記半導体基板の前記表面を平面視したときに、前記トレンチの側面の曲率半径が９００ｎｍ以上である。   A semiconductor device disclosed in this specification includes a semiconductor substrate, a trench provided on a surface of the semiconductor substrate, a gate insulating film covering an inner surface of the trench, and a gate insulating film disposed in the trench and the gate insulating film. A gate electrode insulated from the semiconductor substrate. When the surface of the semiconductor substrate is viewed in a plan view, the trench is meandering. When the surface of the semiconductor substrate is viewed in a plan view, a radius of curvature of a side surface of the trench is 900 nm or more.

この半導体装置では、トレンチが半導体基板の表面において蛇行しているので、チャネル密度が高い。また、この半導体装置では、トレンチの側面が９００ｎｍ以上の曲率半径で曲がっている。このようにトレンチの側面の曲がりが緩やかだと、トレンチの側面の凸状部でゲート絶縁膜が薄くなり難い。したがって、ゲートリーク電流を抑制することができる。   In this semiconductor device, since the trench is meandering on the surface of the semiconductor substrate, the channel density is high. In this semiconductor device, the side surface of the trench is bent with a radius of curvature of 900 nm or more. If the side surface of the trench has a gentle bend, the gate insulating film is unlikely to be thin at the convex portion on the side surface of the trench. Therefore, gate leak current can be suppressed.

実施形態のＭＯＳＦＥＴ（metal oxide semiconductor field effect transistor）の断面図。FIG. 1 is a cross-sectional view of a MOSFET (metal oxide semiconductor field effect transistor) according to an embodiment. 半導体基板の上面の平面図。FIG. 3 is a plan view of the upper surface of a semiconductor substrate. ゲート絶縁膜の厚さの説明図。FIG. 4 is an explanatory diagram of a thickness of a gate insulating film. ゲート絶縁膜の厚さの説明図。FIG. 4 is an explanatory diagram of a thickness of a gate insulating film. トレンチの側面の曲率半径とゲート絶縁膜の厚さとの関係を示すグラフ。4 is a graph showing a relationship between a radius of curvature of a side surface of a trench and a thickness of a gate insulating film. トレンチの側面の曲率半径とチャネル密度増加率との関係を示すグラフ。5 is a graph showing a relationship between a radius of curvature of a side surface of a trench and a channel density increase rate.

図１に示す実施形態のＭＯＳＦＥＴは、半導体基板１２を有している。半導体基板１２は、シリコン、ＳｉＣ等により構成されている。半導体基板１２の上面１２ａには、トレンチ２０が設けられている。なお、図示していないが、半導体基板１２の上面１２ａには、複数のトレンチ２０が設けられている。各トレンチ２０は、図１、２に示す構造を備えている。トレンチ２０の内面は、ゲート絶縁膜２２によって覆われている。トレンチ２０内に、ゲート電極２４が配置されている。ゲート電極２４は、ゲート絶縁膜２２によって半導体基板１２から絶縁されている。ゲート電極２４の上面は、層間絶縁膜２６によって覆われている。半導体基板１２の上面１２ａは、ソース電極３０によって覆われている。ゲート電極２４は、層間絶縁膜２６によってソース電極３０から絶縁されている。半導体基板１２の下面１２ｂは、ドレイン電極３２によって覆われている。   The MOSFET of the embodiment shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of silicon, SiC, or the like. On the upper surface 12a of the semiconductor substrate 12, a trench 20 is provided. Although not shown, a plurality of trenches 20 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 20 has the structure shown in FIGS. The inner surface of trench 20 is covered with gate insulating film 22. A gate electrode 24 is arranged in the trench 20. The gate electrode 24 is insulated from the semiconductor substrate 12 by the gate insulating film 22. The upper surface of the gate electrode 24 is covered with an interlayer insulating film 26. The upper surface 12 a of the semiconductor substrate 12 is covered with the source electrode 30. Gate electrode 24 is insulated from source electrode 30 by interlayer insulating film 26. The lower surface 12b of the semiconductor substrate 12 is covered with the drain electrode 32.

半導体基板１２は、ソース領域４０、ボディ領域４２、ドリフト領域４４、ドレイン領域４６を有している。ソース領域４０は、ｎ型領域であり、ソース電極３０にオーミック接触している。ソース領域４０は、トレンチ２０の上端部において、ゲート絶縁膜２２に接している。ボディ領域４２は、ｐ型領域である。ボディ領域４２は、ソース電極３０の下側でゲート絶縁膜２２に接している。ボディ領域４２は、図示しない位置で、ソース電極３０にオーミック接触している。ドリフト領域４４は、ｎ型不純物濃度が低いｎ型領域である。ドリフト領域４４は、ボディ領域４２によってソース領域４０から分離されている。ドリフト領域４４は、ボディ領域４２の下側でゲート絶縁膜２２に接している。ドレイン領域４６は、ドリフト領域４４よりもｎ型不純物濃度が高いｎ型領域である。ドレイン領域４６は、ドリフト領域４４に対して下側から接している。ドレイン領域４６は、ドレイン電極３２にオーミック接触している。   The semiconductor substrate 12 has a source region 40, a body region 42, a drift region 44, and a drain region 46. The source region 40 is an n-type region and is in ohmic contact with the source electrode 30. Source region 40 is in contact with gate insulating film 22 at the upper end of trench 20. Body region 42 is a p-type region. The body region 42 is in contact with the gate insulating film 22 below the source electrode 30. Body region 42 is in ohmic contact with source electrode 30 at a position not shown. The drift region 44 is an n-type region having a low n-type impurity concentration. Drift region 44 is separated from source region 40 by body region 42. Drift region 44 is in contact with gate insulating film 22 below body region 42. The drain region 46 is an n-type region having a higher n-type impurity concentration than the drift region 44. The drain region 46 is in contact with the drift region 44 from below. The drain region 46 is in ohmic contact with the drain electrode 32.

ゲート電極２４に閾値以上の電位を印加すると、ゲート絶縁膜２２近傍のボディ領域４２にチャネルが形成され、ＭＯＳＦＥＴがオンする。すなわち、ゲート絶縁膜２２とボディ領域４２の境界部が、チャネルとなる領域である。   When a potential equal to or higher than the threshold is applied to the gate electrode 24, a channel is formed in the body region 42 near the gate insulating film 22, and the MOSFET is turned on. That is, the boundary between the gate insulating film 22 and the body region 42 is a region to be a channel.

図２に示すように半導体基板１２の上面１２ａを平面視したときに、トレンチ２０は、蛇行している。上述したように、ゲート絶縁膜２２とボディ領域４２の境界部はチャネルとなる領域である。図２のようにトレンチ２０が蛇行することで、トレンチ２０が直線である場合に比べて、ゲート絶縁膜２２とボディ領域４２の境界部が長くなる。したがって、トレンチ２０を蛇行させることで、チャネル密度を高くすることができ、ＭＯＳＦＥＴのオン抵抗を低減することができる。本実施形態では、半導体基板１２の上面１２ａを平面視したときにトレンチ２０の各側面２０ａの曲率半径が９００ｎｍ以上となるように、トレンチ２０が蛇行している。すなわち、各側面２０ａの曲率半径がいずれの位置でも９００ｎｍ以上となるようにトレンチ２０が蛇行している。トレンチ２０が蛇行しているので、トレンチ２０の側面２０ａには凸状部２１が存在する。   As shown in FIG. 2, when the upper surface 12a of the semiconductor substrate 12 is viewed in plan, the trench 20 is meandering. As described above, the boundary between the gate insulating film 22 and the body region 42 is a region serving as a channel. By meandering the trench 20 as shown in FIG. 2, the boundary between the gate insulating film 22 and the body region 42 becomes longer than when the trench 20 is straight. Therefore, by meandering the trench 20, the channel density can be increased, and the on-resistance of the MOSFET can be reduced. In the present embodiment, the trench 20 meanders so that the curvature radius of each side surface 20a of the trench 20 when viewed from above the top surface 12a of the semiconductor substrate 12 is 900 nm or more. That is, the trenches 20 meander so that the radius of curvature of each side surface 20a is 900 nm or more at any position. Since the trench 20 is meandering, a convex portion 21 exists on the side surface 20 a of the trench 20.

ゲート絶縁膜２２は、トレンチ２０の側面２０ａを酸化させることで形成される。本願発明者らの実験により、上面１２ａを平面視したときのトレンチ２０の側面２０ａの曲率半径に応じて、ゲート絶縁膜２２の厚さが変化することが分かった。図３に示すように、側面２０ａの曲率半径が小さいと、凸状部２１においてゲート絶縁膜２２の厚さＴ１が薄くなる。これに対し、図４に示すように、側面２０ａの曲率半径が大きいと、側面２０ａ全体に均一な厚さでゲート絶縁膜２２が形成される。このため、図４では、図３よりも、凸状部２１におけるゲート絶縁膜２２の厚さＴ１が厚くなる。図５は、側面２０ａの曲率半径とゲート絶縁膜２２の厚さとの関係を示している。なお、図５の実験では、トレンチ２０がストレートである（蛇行していない）ときに厚さＴ２のゲート絶縁膜２２が形成される条件において、曲率半径がそれぞれ異なるトレンチ２０に対してゲート絶縁膜２２を形成した。縦軸は、凸状部２１におけるゲート絶縁膜２２の厚さＴ１を、設計上のゲート絶縁膜２２の厚さＴ２で除算した値を示している。図５から明らかなように、曲率半径が９００ｎｍ未満の場合には、曲率半径が小さいほど、凸状部２１におけるゲート絶縁膜２２の厚さＴ１が薄くなり、値Ｔ１／Ｔ２が小さくなる。他方、曲率半径が９００ｎｍ以上の場合には、値Ｔ１／Ｔ２がほぼ１００％となる。すなわち、曲率半径が９００ｎｍ以上の場合には、凸状部２１において、トレンチ２０がストレートである場合と同等の厚さのゲート絶縁膜２２が得られる。図５から明らかなように、トレンチ２０の側面２０ａの曲率半径を９００ｎｍ以上とすることで、凸状部２１に十分な厚さのゲート絶縁膜２２を形成することができる。したがって、側面２０ａの曲率半径を９００ｎｍ以上とすることで、凸状部２１においてゲートリーク電流が生じることを抑制することができる。   The gate insulating film 22 is formed by oxidizing the side surface 20a of the trench 20. The experiments by the inventors of the present application have revealed that the thickness of the gate insulating film 22 changes according to the radius of curvature of the side surface 20a of the trench 20 when the upper surface 12a is viewed in plan. As shown in FIG. 3, when the radius of curvature of the side surface 20 a is small, the thickness T <b> 1 of the gate insulating film 22 in the convex portion 21 decreases. On the other hand, as shown in FIG. 4, when the radius of curvature of the side surface 20a is large, the gate insulating film 22 is formed with a uniform thickness on the entire side surface 20a. For this reason, in FIG. 4, the thickness T1 of the gate insulating film 22 in the convex portion 21 is larger than in FIG. FIG. 5 shows the relationship between the radius of curvature of the side surface 20a and the thickness of the gate insulating film 22. In the experiment of FIG. 5, under the condition that the gate insulating film 22 having the thickness T2 is formed when the trench 20 is straight (not meandering), the gate insulating film is different for the trenches 20 having different curvature radii. No. 22 was formed. The vertical axis indicates a value obtained by dividing the thickness T1 of the gate insulating film 22 in the convex portion 21 by the designed thickness T2 of the gate insulating film 22. As is clear from FIG. 5, when the radius of curvature is less than 900 nm, the smaller the radius of curvature, the smaller the thickness T1 of the gate insulating film 22 in the convex portion 21 and the smaller the value T1 / T2. On the other hand, when the radius of curvature is 900 nm or more, the value T1 / T2 is almost 100%. That is, when the radius of curvature is 900 nm or more, a gate insulating film 22 having the same thickness as that in the case where the trench 20 is straight is obtained in the convex portion 21. As is clear from FIG. 5, by setting the radius of curvature of the side surface 20 a of the trench 20 to 900 nm or more, the gate insulating film 22 having a sufficient thickness can be formed on the convex portion 21. Therefore, by setting the radius of curvature of the side surface 20a to 900 nm or more, it is possible to suppress the occurrence of a gate leak current in the convex portion 21.

また、図６は、トレンチ２０の側面２０ａの曲率半径とチャネル密度増加率との関係を示している。なお、チャネル密度増加率は、トレンチ２０がストレートである場合のチャネル密度に対して、トレンチ２０を蛇行させた場合のチャネル密度がどの程度上昇するかを示す。図６から明らかなように、側面２０ａの曲率半径が２５００ｎｍ以下であれば、側面２０ａの曲率半径が小さいほど、チャネル密度増加率が大きくなる。側面２０ａの曲率半径を２５００ｎｍ以下とすることで、チャネル密度を１〜４０％増加させることができる。   FIG. 6 shows the relationship between the radius of curvature of the side surface 20a of the trench 20 and the channel density increase rate. Note that the channel density increase rate indicates how much the channel density when the trench 20 is meandered increases with respect to the channel density when the trench 20 is straight. As is clear from FIG. 6, when the radius of curvature of the side surface 20a is 2500 nm or less, the smaller the radius of curvature of the side surface 20a, the larger the channel density increase rate. By setting the radius of curvature of the side surface 20a to 2500 nm or less, the channel density can be increased by 1 to 40%.

以上に説明したように、トレンチ２０の側面２０ａの曲率半径を９００ｎｍ以上とすることで、ゲートリーク電流を抑制することができる。また、側面２０ａの曲率半径を２５００ｎｍ以下とすることで、効果的にチャネル密度を増加させることができる。このように側面２０ａの曲率半径を設定することで、ゲートリーク電流が生じ難く、チャネル密度が高いＭＯＳＦＥＴを実現することができる。   As described above, the gate leakage current can be suppressed by setting the radius of curvature of the side surface 20a of the trench 20 to 900 nm or more. By setting the radius of curvature of the side surface 20a to 2500 nm or less, the channel density can be effectively increased. By setting the radius of curvature of the side surface 20a in this manner, it is possible to realize a MOSFET in which a gate leakage current hardly occurs and a channel density is high.

なお、上述した実施形態ではＭＯＳＦＥＴについて説明したが、ＩＧＢＴ（insulated gate bipolar transistor）等の他のトレンチゲート型スイッチング素子に本明細書に開示の技術を適用してもよい。   Although the MOSFET has been described in the above embodiment, the technology disclosed in this specification may be applied to another trench gate type switching element such as an IGBT (insulated gate bipolar transistor).

以上、実施形態について詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例をさまざまに変形、変更したものが含まれる。本明細書または図面に説明した技術要素は、単独あるいは各種の組み合わせによって技術有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの１つの目的を達成すること自体で技術有用性を持つものである。   The embodiments have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Further, the technology exemplified in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

１２ ：半導体基板
２０ ：トレンチ
２０ａ ：側面
２１ ：凸状部
２２ ：ゲート絶縁膜
２４ ：ゲート電極
２６ ：層間絶縁膜
３０ ：ソース電極
３２ ：ドレイン電極
４０ ：ソース領域
４２ ：ボディ領域
４４ ：ドリフト領域
４６ ：ドレイン領域 12: semiconductor substrate 20: trench 20a: side surface 21: convex portion 22: gate insulating film 24: gate electrode 26: interlayer insulating film 30: source electrode 32: drain electrode 40: source region 42: body region 44: drift region 46 ： Drain region

Claims (1)

半導体装置であって、
半導体基板と、
前記半導体基板の表面に設けられたトレンチと、
前記トレンチの内面を覆うゲート絶縁膜と、
前記トレンチ内に配置されており、前記ゲート絶縁膜によって前記半導体基板から絶縁されたゲート電極、
を有しており、
前記半導体基板の前記表面を平面視したときに、前記トレンチが蛇行しており
前記半導体基板の前記表面を平面視したときに、前記トレンチの側面の曲率半径が９００ｎｍ以上である、
半導体装置。 A semiconductor device,
A semiconductor substrate;
A trench provided on the surface of the semiconductor substrate,
A gate insulating film covering an inner surface of the trench;
A gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film;
Has,
When the surface of the semiconductor substrate is viewed in plan, the trench is meandering, and when the surface of the semiconductor substrate is viewed in plan, a radius of curvature of a side surface of the trench is 900 nm or more.
Semiconductor device.
JP2018171821A 2018-09-13 2018-09-13 Semiconductor device Pending JP2020043307A (en)

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Country Link
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217419A (en) * 2000-02-03 2001-08-10 Denso Corp Semiconductor device
JP2003197910A (en) * 2001-12-26 2003-07-11 Toshiba Corp Semiconductor device
JP2009088198A (en) * 2007-09-28 2009-04-23 Rohm Co Ltd Semiconductor device
JP2017135245A (en) * 2016-01-27 2017-08-03 株式会社東芝 Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217419A (en) * 2000-02-03 2001-08-10 Denso Corp Semiconductor device
JP2003197910A (en) * 2001-12-26 2003-07-11 Toshiba Corp Semiconductor device
JP2009088198A (en) * 2007-09-28 2009-04-23 Rohm Co Ltd Semiconductor device
JP2017135245A (en) * 2016-01-27 2017-08-03 株式会社東芝 Semiconductor device

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