JP2019527477A - ドナー基材を再生するための方法 - Google Patents
ドナー基材を再生するための方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Recrystallisation Techniques (AREA)
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Abstract
Description
本PCT特許出願は、以下の各々の優先権を主張する。
・米国特許仮出願第62/361,468号、2016年7月12日出願
・米国特許非仮出願第15/643,384号、2017年7月6日出願
・米国特許仮出願第62/367,911号、2016年7月28日出願
・米国特許非仮出願第15/643,370号、2017年7月6日出願
切断領域と相互作用し、ドナー基材の残りの部分から残留材料が分離されるようにエネルギーを印加すること、および
微細処理を実施して、切断領域のドナー基材の粗さを除去することを含む方法。
中心部ギャップ=0.696pr4/Et3 (1)
式中、p=単位がPaの圧力、r=ウエハ半径、E=ヤング弾性率、t=アッセンブリの厚さである。
第1の面を裏当て基材に付着させること、
ドナー基材を処理して、内部応力を生成すること、
第2の面を標的基材に接合すること、
ドナー基材を切断領域で切断して、材料の層を標的基材に移転させ、ドナー基材の残りの材料は裏当て基材に付着されたままであること、および
ドナー基材の第1の面が裏当て基材に付着されたままの状態で、残りの材料を再生すること
を含む方法。
Claims (18)
- 第1の面および第2の面を含むドナー基材を準備すること、
前記第1の面を裏当て基材に付着させること、
前記ドナー基材を処理して、内部応力を生成すること、
前記第2の面を標的基材に接合すること、
前記ドナー基材を切断領域で切断して、材料の層を前記標的基材に移転させ、前記ドナー基材の残りの材料は前記裏当て基材に付着されたままであること、および
前記ドナー基材の前記第1の面が前記裏当て基材に付着されたままの状態で、前記残りの材料を再生すること
を含む方法。 - 前記切断領域は、粒子を、前記裏当て基材に付着されている前記ドナー基材に打ち込むことにより形成され、前記内部応力は、前記打ち込みにより生じる、請求項1に記載の方法。
- 前記裏当て基材は、前記ドナー基材の熱膨張係数と同様の熱膨張係数を示す、請求項1に記載の方法。
- 前記裏当て基材に接合されている前記ドナー基材を含むアッセンブリは、打ち込みプロセス、前記切断、または前記再生を容易にする、請求項1に記載の方法。
- 前記裏当て基材は、前記ドナー基材の縁端をクランプして、前記ドナー基材の膨張を抑制する、請求項1に記載の方法。
- 前記再生は、熱曝露を含む、請求項1に記載の方法。
- 前記再生は、化学曝露を含む、請求項1に記載の方法。
- 前記化学曝露は、エッチングを含む、請求項7に記載の方法。
- 前記化学曝露は、化学機械研磨を含む、請求項6に記載の方法。
- 前記再生は、研削を含む、請求項1に記載の方法。
- 前記再生は、プラズマ曝露を含む、請求項1に記載の方法。
- 前記ドナー基材は、GaNを含む、請求項1に記載の方法。
- 前記第1の面は、前記GaNドナー基材のGa面を含む、請求項12に記載の方法。
- 前記第1の面は、前記GaNドナー基材のN面を含む、請求項12に記載の方法。
- 前記裏当て基材は、縁部を含む、請求項1に記載の方法。
- 前記裏当て基材は、サファイアを含む、請求項1に記載の方法。
- 前記ドナー基材は、GaAsを含む、請求項1に記載の方法。
- 前記裏当て基材は、サファイアを含む、請求項17に記載の方法。
Applications Claiming Priority (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662361468P | 2016-07-12 | 2016-07-12 | |
US62/361,468 | 2016-07-12 | ||
US201662367911P | 2016-07-28 | 2016-07-28 | |
US62/367,911 | 2016-07-28 | ||
US15/643,370 US20180019169A1 (en) | 2016-07-12 | 2017-07-06 | Backing substrate stabilizing donor substrate for implant or reclamation |
US15/643,384 | 2017-07-06 | ||
US15/643,370 | 2017-07-06 | ||
US15/643,384 US20180033609A1 (en) | 2016-07-28 | 2017-07-06 | Removal of non-cleaved/non-transferred material from donor substrate |
PCT/IB2017/054209 WO2018011731A1 (en) | 2016-07-12 | 2017-07-12 | Method of a donor substrate undergoing reclamation |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019527477A true JP2019527477A (ja) | 2019-09-26 |
JP2019527477A5 JP2019527477A5 (ja) | 2020-08-20 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2019501489A Pending JP2019527477A (ja) | 2016-07-12 | 2017-07-12 | ドナー基材を再生するための方法 |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP3485505A1 (ja) |
JP (1) | JP2019527477A (ja) |
KR (1) | KR20190027821A (ja) |
CN (1) | CN109478493A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6915191B1 (ja) * | 2021-01-21 | 2021-08-04 | 信越エンジニアリング株式会社 | ワーク分離装置及びワーク分離方法 |
WO2022168217A1 (ja) * | 2021-02-04 | 2022-08-11 | 三菱電機株式会社 | 半導体基板の製造方法および半導体装置の製造方法 |
WO2022185906A1 (ja) * | 2021-03-04 | 2022-09-09 | 信越半導体株式会社 | 紫外線発光素子用エピタキシャルウェーハの製造方法、紫外線発光素子用基板の製造方法、紫外線発光素子用エピタキシャルウェーハ及び紫外線発光素子用基板 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110190163B (zh) * | 2019-05-24 | 2020-04-28 | 康佳集团股份有限公司 | 图形化衬底、外延片、制作方法、存储介质及led芯片 |
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2017
- 2017-07-12 EP EP17755560.4A patent/EP3485505A1/en not_active Withdrawn
- 2017-07-12 CN CN201780042232.5A patent/CN109478493A/zh active Pending
- 2017-07-12 KR KR1020197001310A patent/KR20190027821A/ko unknown
- 2017-07-12 JP JP2019501489A patent/JP2019527477A/ja active Pending
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6915191B1 (ja) * | 2021-01-21 | 2021-08-04 | 信越エンジニアリング株式会社 | ワーク分離装置及びワーク分離方法 |
WO2022168217A1 (ja) * | 2021-02-04 | 2022-08-11 | 三菱電機株式会社 | 半導体基板の製造方法および半導体装置の製造方法 |
JP7475503B2 (ja) | 2021-02-04 | 2024-04-26 | 三菱電機株式会社 | 半導体基板の製造方法および半導体装置の製造方法 |
WO2022185906A1 (ja) * | 2021-03-04 | 2022-09-09 | 信越半導体株式会社 | 紫外線発光素子用エピタキシャルウェーハの製造方法、紫外線発光素子用基板の製造方法、紫外線発光素子用エピタキシャルウェーハ及び紫外線発光素子用基板 |
JP7484773B2 (ja) | 2021-03-04 | 2024-05-16 | 信越半導体株式会社 | 紫外線発光素子用エピタキシャルウェーハの製造方法、紫外線発光素子用基板の製造方法及び紫外線発光素子用エピタキシャルウェーハ |
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EP3485505A1 (en) | 2019-05-22 |
CN109478493A (zh) | 2019-03-15 |
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