JP2019188456A - Solder alloy, solder paste, mold solder, and semiconductor device using solder alloy - Google Patents

Solder alloy, solder paste, mold solder, and semiconductor device using solder alloy Download PDF

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JP2019188456A
JP2019188456A JP2018087111A JP2018087111A JP2019188456A JP 2019188456 A JP2019188456 A JP 2019188456A JP 2018087111 A JP2018087111 A JP 2018087111A JP 2018087111 A JP2018087111 A JP 2018087111A JP 2019188456 A JP2019188456 A JP 2019188456A
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solder
alloy
solder alloy
semiconductor chip
mass
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JP6529632B1 (en
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進 三谷
Susumu Mitani
進 三谷
元 渡邉
Hajime Watanabe
元 渡邉
祥平 上方
Shohei Kamigata
祥平 上方
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Nihon Handa Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

To obtain a solder alloy with a high melting point and high ductility.SOLUTION: The solder alloy contains nickel, which is 0.03 mass%-0.09 mass% of the total mass%, and bismuth, which is the balance of it, excluding the nickel and unavoidable impurities.SELECTED DRAWING: Figure 4

Description

本発明は、不可避不純物以上のＰｂ（鉛）を含まないはんだ合金、ソルダペースト、成形はんだ、及びはんだ合金を用いた半導体装置に関する。   The present invention relates to a solder alloy, a solder paste, a molded solder, and a semiconductor device using a solder alloy that does not contain Pb (lead) above inevitable impurities.

はんだ合金には、融点の高い高温はんだと称されるものがある。高温はんだの用途の一つは、階層はんだ付けである。階層はんだ付けは、少なくとも２度のはんだ接合が行われることを言う。階層はんだ付けの一例を、ＩＣ（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）等のパッケージ部品の場合で説明する。ダイパッド上に半導体チップを搭載し、ダイパッドと半導体チップとを接合するとき、１度目のはんだ接合が行われる。続いて、半導体チップ及びダイパッドを樹脂封止することで、パッケージ部品が作製される。その後、パッケージ部品をプリント基板上に表面実装する際、リードフレームをはんだでプリント配線に接合する２度目のはんだ接合が行われる。２度目のはんだ接合はリフロー工程と呼ばれている。２度目のはんだ接合で、パッケージ部品内のはんだが溶融しないためには、その融点が２度目のはんだ接合の温度よりも高い必要がある。   Some solder alloys are called high-temperature solders with a high melting point. One application of high temperature soldering is hierarchical soldering. Hierarchical soldering means that at least two solder joints are made. An example of hierarchical soldering will be described in the case of a package component such as an IC (Integrated Circuit). When a semiconductor chip is mounted on the die pad and the die pad and the semiconductor chip are joined, the first solder joint is performed. Subsequently, the semiconductor chip and the die pad are resin-sealed to produce a package component. Thereafter, when the package component is surface-mounted on the printed circuit board, a second solder bonding is performed in which the lead frame is bonded to the printed wiring with solder. The second solder joint is called a reflow process. In order that the solder in the package component does not melt in the second solder joint, the melting point needs to be higher than the temperature of the second solder joint.

従来、高温はんだとして、Ｐｂが９０質量％以上のＰｂ基はんだ合金が知られている。しかし、Ｐｂ基はんだ合金は、環境に有害な鉛を含んでいるため、その使用が制限される傾向がある。以下では、はんだ合金組成に関して、読みやすさの観点から一部の「質量％」を「％」と省略して表記し、「質量％」と「％」が併存している。   Conventionally, a Pb-based solder alloy having a Pb of 90% by mass or more is known as a high-temperature solder. However, since the Pb-based solder alloy contains lead harmful to the environment, its use tends to be limited. In the following, regarding the solder alloy composition, some “mass%” is abbreviated as “%” from the viewpoint of readability, and “mass%” and “%” coexist.

一方、Ｐｂフリーの高温系はんだとして、Ｓｎ（スズ）及びＳｂ（アンチモン）を含むＳｎ−（５〜１０）％Ｓｂ（融点：２３５〜２４３℃）が、一般に知られている。しかし、Ｓｎを主成分とした鉛フリーはんだを用いると、はんだ付け部を、例えば２５０℃といった高温下に暴露することになり、電子部品内部の接続では、電極の溶解又は断線など、いわゆる耐熱性不良の問題が発生する場合がある。従って階層はんだ付けのためのＰｂフリーはんだとしては、リフロー温度２４０〜２５０℃でも溶融しない２６０℃以上の融点が求められている。   On the other hand, Sn— (5-10)% Sb (melting point: 235-243 ° C.) containing Sn (tin) and Sb (antimony) is generally known as a Pb-free high-temperature solder. However, when lead-free solder containing Sn as a main component is used, the soldered portion is exposed to a high temperature of, for example, 250 ° C., and so-called heat resistance such as melting or disconnection of electrodes is caused in the connection inside the electronic component. Defect issues may occur. Accordingly, a Pb-free solder for layer soldering is required to have a melting point of 260 ° C. or higher that does not melt even at a reflow temperature of 240 to 250 ° C.

高温はんだの別の用途は、パワーデバイスにおける接合材である。パワーデバイスの分野においては、近年、高温使用の要求が高まっている。従来、動作温度仕様の上限が自己発熱レベルの１５０℃程度であったが、近年、１７５℃及び２００℃など、パワーデバイスの製品に要求される動作温度仕様の上限が上昇している。そのため、パワーデバイスの接合部についても耐熱性向上が求められている。   Another application of high temperature solders is as a bonding material in power devices. In the field of power devices, the demand for high temperature use has increased in recent years. Conventionally, the upper limit of the operating temperature specification was about 150 ° C., which is a self-heating level, but in recent years, the upper limit of the operating temperature specification required for power device products such as 175 ° C. and 200 ° C. has increased. Therefore, improvement in heat resistance is also required for the joint portion of the power device.

パワーデバイスは、例えば、絶縁基板の両面に銅回路板が接合された基板に半導体チップが搭載された構成である。絶縁基板は、例えば、アルミナセラミックス板である。絶縁基板の上面側の銅回路板に半導体チップがダイボンド材で接合される。絶縁基板の下面側の銅回路板に放熱板がダイボンド材で接合される。このダイボンド材に、はんだが用いられている。半導体チップと上面側の銅回路板とを接合するはんだを上部ダイボンド材と称し、下面側の銅回路板と放熱板とを接合するはんだを下部ダイボンド材と称する。このように、パワーデバイスでは上下２か所の接合部ではんだが使用される。以下では、パワーデバイスの接合部で使用されるはんだを、ダイボンド用はんだと称する。   The power device has, for example, a configuration in which a semiconductor chip is mounted on a substrate in which a copper circuit board is bonded to both surfaces of an insulating substrate. The insulating substrate is, for example, an alumina ceramic plate. A semiconductor chip is bonded to the copper circuit board on the upper surface side of the insulating substrate with a die bond material. A heat sink is bonded to the copper circuit board on the lower surface side of the insulating substrate with a die bond material. Solder is used for this die bond material. The solder that joins the semiconductor chip and the copper circuit board on the upper surface side is called an upper die bond material, and the solder that joins the copper circuit board on the lower surface side and the heat sink is called a lower die bond material. Thus, in the power device, solder is used at the joints at two places on the upper and lower sides. Hereinafter, the solder used at the joint of the power device is referred to as die bonding solder.

パワーデバイスは自己発熱が大きいため、ダイボンド用はんだは、一般に固相線温度が高いことが要求される。そのため、従来、９０質量％以上の鉛を含有するＰｂ基はんだ合金のうち、固相線温度が高いものが使用されてきた。固相線温度の高いＰｂ基はんだ合金として、例えば、母材となるＰｂにＳｎが添加されたＰｂ−５％Ｓｎがある。Ｐｂ−５％Ｓｎの固相線温度は３００℃である。その他にも、母材となるＰｂにＳｎ及び銀（Ａｇ）が添加されたＰｂ−５％Ｓｎ−１．５％Ａｇが知られている。Ｐｂ−５％Ｓｎ−１．５％Ａｇの固相線温度は２９６℃である。このような、固相線温度の高いはんだ合金が、ダイボンド用はんだに使用されていた。   Since power devices generate large amounts of self-heating, die bonding solder is generally required to have a high solidus temperature. Therefore, conventionally, a Pb-based solder alloy containing 90% by mass or more of lead having a high solidus temperature has been used. An example of a Pb-based solder alloy having a high solidus temperature is Pb-5% Sn in which Sn is added to Pb as a base material. The solidus temperature of Pb-5% Sn is 300 ° C. In addition, Pb-5% Sn-1.5% Ag in which Sn and silver (Ag) are added to Pb as a base material is known. The solidus temperature of Pb-5% Sn-1.5% Ag is 296 ° C. Such a solder alloy having a high solidus temperature has been used as a solder for die bonding.

Ｐｂ基はんだ合金は安価で接合信頼性が高いが、上述したように、環境に有害な鉛を含んでいるため、ダイボンド用はんだにも鉛フリー化が求められている。そのため、動作温度が１５０℃程度のパワーデバイスには、ダイボンド用はんだとして、Ｓｎ−Ａｇ−Ｃｕ系の鉛フリーはんだが使われるようになってきた。Ｓｎ−Ａｇ−Ｃｕ系のはんだ合金は、接合信頼性がＰｂ基はんだ合金に劣るという欠点があるが、固相線温度が２２０℃付近にあるという利点がある。   Pb-based solder alloys are inexpensive and have high bonding reliability. However, as described above, lead-free solder is also required for die bonding solder because it contains lead harmful to the environment. For this reason, Sn—Ag—Cu-based lead-free solder has come to be used as die bonding solder for power devices having an operating temperature of about 150 ° C. The Sn—Ag—Cu based solder alloy has the disadvantage that the bonding reliability is inferior to that of the Pb-based solder alloy, but has the advantage that the solidus temperature is around 220 ° C.

しかし、既にＳｉパワーデバイスの動作温度の上限はで１７５℃であり、今後、ＳｉＣパワーデバイスでは動作温度が２００℃以上に高温化すると見込まれている。このような動作温度仕様を満たす、従来のＰｂフリーはんだとして、Ａｕ（金）を多く含むＡｕ−２０％Ｓｎが知られている。Ａｕ−２０％Ｓｎは、共晶温度が２８０℃という利点があるが、Ａｕ含有量が多いため、高価という欠点がある。そのため、Ａｕ−２０％Ｓｎの汎用化は容易ではない。   However, the upper limit of the operating temperature of the Si power device is already 175 ° C., and the operating temperature of the SiC power device is expected to increase to 200 ° C. or higher in the future. As a conventional Pb-free solder satisfying such an operating temperature specification, Au-20% Sn containing a large amount of Au (gold) is known. Au-20% Sn has an advantage that the eutectic temperature is 280 ° C., but has a disadvantage that it is expensive because of a large Au content. Therefore, generalization of Au-20% Sn is not easy.

そのため、融点がより高い、Ｐｂフリーはんだが必要となる。具体的には、このような高温動作パワーデバイス用の高温はんだとしては、固相線温度２６０℃以上が必要になると言われている。ただし、いまだ周辺部材の耐熱性が高くないこと及び冷却時の残留応力の観点から、液相線温度は３００℃以下であることが望ましいと言われている（例えば、非特許文献１参照）。   Therefore, Pb-free solder having a higher melting point is required. Specifically, it is said that a high temperature solder for such a high temperature operation power device requires a solidus temperature of 260 ° C. or higher. However, it is said that the liquidus temperature is desirably 300 ° C. or lower from the viewpoint that the heat resistance of the peripheral members is not yet high and the residual stress at the time of cooling is desirable (for example, see Non-Patent Document 1).

固相線温度が２６０℃〜３００℃の範囲に属する条件に合致するはんだ合金の一例として、Ｓｎ−高Ｓｂ系はんだ合金が提案されている（例えば、特許文献１参照）。特許文献１には、ＳｎにＡｇ及びＣｕを加えさらにＡｌを微量添加したＳｎ−３７％Ｓｂ−１５％Ａｇ−６％Ｃｕ−０．０１３％Ａｌの成分のはんだ合金が開示されている。このはんだ合金は、固相線温度が２９７．７℃であり、液相線温度が３５７．０℃である。   An Sn-high Sb solder alloy has been proposed as an example of a solder alloy that satisfies the conditions where the solidus temperature falls within the range of 260 ° C to 300 ° C (see, for example, Patent Document 1). Patent Document 1 discloses a solder alloy having a component of Sn-37% Sb-15% Ag-6% Cu-0.013% Al in which Ag and Cu are added to Sn and a small amount of Al is added. This solder alloy has a solidus temperature of 297.7 ° C. and a liquidus temperature of 357.0 ° C.

また、固相線温度が２６０℃〜３００℃の範囲に属する条件に合致するはんだ合金の別の例として、Ｂｉ（ビスマス）−Ａｇ系はんだ合金が提案されている（例えば、特許文献２参照）。特許文献２には、Ｂｉ−２．５％Ａｇ−０．１％Ｓｂの成分のはんだ合金が開示されている。このはんだ合金は、固相線温度が２６３℃であり、液相線温度が２８０℃である。   Moreover, Bi (bismuth) -Ag solder alloy has been proposed as another example of a solder alloy that meets the conditions that the solidus temperature falls within the range of 260 ° C. to 300 ° C. (see, for example, Patent Document 2). . Patent Document 2 discloses a solder alloy having a component of Bi-2.5% Ag-0.1% Sb. This solder alloy has a solidus temperature of 263 ° C. and a liquidus temperature of 280 ° C.

特許第５５８５７４６号公報Japanese Patent No. 5585746 特許第３６７１８１５号公報Japanese Patent No. 3671815

平塚大祐、外２名、「パワー半導体の高温動作を可能にするダイボンド材料及び焼結接合技術」、東芝レビュー、株式会社東芝、２０１５年１１月、Ｖｏｌ．７０、Ｎｏ．１１、Ｐ．４６−４９Daisuke Hiratsuka and two others, “Die-bonding materials and sintered bonding technology that enable high-temperature operation of power semiconductors”, Toshiba Review, Toshiba Corporation, November 2015, Vol. 70, no. 11, P.I. 46-49

Ａｕ−Ｓｎ系はんだ合金、Ｓｎ−高Ｓｂ系はんだ合金およびＢｉ−Ａｇ系はんだ合金は、室温での延性が極めて低いという欠点がある。例えば、Ａｕ−２０％Ｓｎ、Ｓｎ−２．５％Ａｇ−０．１％Ｓｂ及びＳｎ−２．５％Ａｇの各はんだ合金の室温での伸び率は、僅か２〜３パーセントである。パワーデバイスのダイボンド用はんだにおいて、伸び率が低いことは、接合信頼性において不安要素となる。   Au-Sn solder alloys, Sn-high Sb solder alloys, and Bi-Ag solder alloys have a drawback that ductility at room temperature is extremely low. For example, each of the solder alloys of Au-20% Sn, Sn-2.5% Ag-0.1% Sb, and Sn-2.5% Ag has an elongation at room temperature of only 2 to 3 percent. In the solder for power device die-bonding, the low elongation rate is an uneasy factor in bonding reliability.

例えば、パワーデバイスが動作すると、半導体チップが発熱し、その発熱量が大きいため、半導体チップ及び放熱板が熱膨張する。半導体チップ及び放熱板の膨張係数が異なるため、半導体チップ裏面と放熱板とを接合するはんだは、引き伸ばされることになる。また、パワーデバイスの動作が停止すると、半導体チップ及び放熱板が常温に戻るため、はんだは収縮する。パワーデバイスの動作と停止との繰り返しによる熱サイクルに伴って、はんだの伸縮も繰り返される。その結果、はんだに亀裂が生じ、ついには接合不良が生じてしまうおそれがある。はんだの伸縮の繰り返しによる材料劣化は、熱疲労又は低サイクル疲労と呼ばれている。低サイクル疲労とは、弾性変形領域（弾性ひずみ範囲）ではなく、変形の大きい塑性変形領域（非弾性ひずみ範囲）で変形が繰り返されるため、１万回以下の少ない回数で生じる劣化現象である。熱疲労及び低サイクル疲労による寿命を、疲労寿命と称する。   For example, when the power device operates, the semiconductor chip generates heat, and the amount of generated heat is large, so that the semiconductor chip and the heat dissipation plate thermally expand. Since the expansion coefficients of the semiconductor chip and the heat radiating plate are different, the solder for joining the back surface of the semiconductor chip and the heat radiating plate is stretched. When the operation of the power device is stopped, the semiconductor chip and the heat sink return to room temperature, so that the solder contracts. As the power device is repeatedly operated and stopped, the expansion and contraction of the solder is repeated. As a result, cracks may occur in the solder, which may result in poor bonding. Material deterioration due to repeated solder expansion and contraction is called thermal fatigue or low cycle fatigue. Low cycle fatigue is a deterioration phenomenon that occurs in a small number of times of 10,000 or less because deformation is repeated not in an elastic deformation region (elastic strain range) but in a plastic deformation region (inelastic strain range) with large deformation. The life due to thermal fatigue and low cycle fatigue is referred to as fatigue life.

疲労寿命と非弾性ひずみ範囲との関係は、式（１）に示すＭａｎｓｏｎ−Ｃｏｆｆｉｎ則に従うことが明らかになっている。   It has been clarified that the relationship between the fatigue life and the inelastic strain range follows the Manson-Coffin rule shown in Equation (1).

Figure 2019188456
Figure 2019188456

式（１）において、Δεｐは非弾性ひずみ範囲であり、Ｎfは破断までの繰り返し数である。べき数αは材料によって異なるが、概ね０．３〜０．５程度である。また、Ｃは一定値であり、材料の破断延性と強く関連する値である。式（１）から２つの重要なことが分かる。一つ目は、ΔεｐとＮfが逆比例の関係があり、非弾性ひずみ範囲Δεｐが大きくなると、破断までの繰り返し数Ｎfが小さくなることである。もう一つは、伸び率に関係するＣが大きいはんだ材料ほど、破断までの繰り返し数Ｎfが大きくなることである。固相線温度が２６０℃から３００℃の範囲のはんだ合金であっても、延性が低いと、熱サイクルで劣化が早まってしまう。 In equation (1), Δε p is the inelastic strain range, and N f is the number of repetitions until breakage. Although the power number α varies depending on the material, it is about 0.3 to 0.5. C is a constant value and is strongly related to the fracture ductility of the material. Two important things can be seen from equation (1). The first is that Δε p and N f are inversely proportional to each other, and when the inelastic strain range Δε p is increased, the number of repetitions N f until fracture is reduced. The other is that the larger the C related to the elongation rate, the larger the number of repetitions N f to break. Even in the case of a solder alloy having a solidus temperature in the range of 260 ° C. to 300 ° C., if the ductility is low, deterioration is accelerated by thermal cycling.

本発明は、上記のような課題を解決するためになされたもので、融点が高温で、かつ延性の大きいはんだ合金、ソルダペースト、成形はんだ、及びはんだ合金を用いた半導体装置を得るものである。   The present invention has been made to solve the above-described problems, and provides a semiconductor device using a solder alloy, solder paste, molded solder, and solder alloy having a high melting point and high ductility. .

本発明に係るはんだ合金は、全体の質量％のうち、０．０３質量％〜０．０９質量％のニッケルと、全体から前記ニッケル及び不可避不純物を除いた残部であるビスマスと、からなるものである。   The solder alloy according to the present invention is composed of 0.03% by mass to 0.09% by mass of nickel and bismuth which is the balance obtained by removing the nickel and unavoidable impurities from the total. is there.

本発明に係るソルダペーストは、上記のはんだ合金の粉末と、フラックスと、を有するものである。   The solder paste according to the present invention has the above solder alloy powder and flux.

本発明に係る成形はんだは、上記のはんだ合金が一定の形状の成形されたものである。   The molded solder according to the present invention is obtained by molding the above solder alloy into a certain shape.

本発明に係る半導体装置は、半導体チップと、前記半導体チップを支持するダイパッドと、前記半導体チップと前記ダイパッドとの間に設けられた上記のはんだ合金と、前記半導体チップ及び前記ダイパッドを覆う樹脂と、を有するものである。   A semiconductor device according to the present invention includes a semiconductor chip, a die pad that supports the semiconductor chip, the solder alloy provided between the semiconductor chip and the die pad, and a resin that covers the semiconductor chip and the die pad. , Has.

また、本発明に係る半導体装置は、半導体チップと、前記半導体チップを支持する絶縁基板と、前記絶縁基板と前記半導体チップとの間に設けられた上記のはんだ合金と、を有するものである。   The semiconductor device according to the present invention includes a semiconductor chip, an insulating substrate that supports the semiconductor chip, and the solder alloy provided between the insulating substrate and the semiconductor chip.

さらに、本発明に係る半導体装置は、半導体チップを支持する絶縁基板と、前記半導体チップから発生する熱を放出する放熱板と、前記絶縁基板と前記放熱板との間に設けられた上記のはんだ合金と、を有するものである。   Furthermore, a semiconductor device according to the present invention includes an insulating substrate that supports a semiconductor chip, a heat radiating plate that releases heat generated from the semiconductor chip, and the solder provided between the insulating substrate and the heat radiating plate. And an alloy.

本発明によれば、Ｂｉ単体に０．０３質量％〜０．０９質量％のＮｉを添加することで、融点が高温で、かつ延性を向上させることができる。   According to the present invention, by adding 0.03% to 0.09% by mass of Ni to Bi alone, the melting point is high and ductility can be improved.

Ｂｉ−Ｎｉ系合金の二元系状態図である。It is a binary system phase diagram of a Bi-Ni type alloy. 延性評価に用いた３点曲げ試験装置の一構成例を示す外観図である。It is an external view which shows one structural example of the 3 point | piece bending test apparatus used for ductility evaluation. 評価対象の試験片について３点曲げ試験後の状態を示す写真である。It is a photograph which shows the state after a 3-point bending test about the test piece of evaluation object. ＢｉへのＮｉ添加量と曲げたわみとの関係を示すグラフである。It is a graph which shows the relationship between Ni addition amount to Bi, and bending deflection. 比較例となるＢｉ単体の冷間圧延後の外観形状を示す写真である。It is a photograph which shows the external appearance shape after the cold rolling of Bi simple substance used as a comparative example. 本発明の実施の形態１に係るはんだ合金の冷間圧延後の外観形状を示す写真である。It is a photograph which shows the external appearance shape after cold rolling of the solder alloy which concerns on Embodiment 1 of this invention. はんだの濡れ広がり率の定義を説明するための模式図である。It is a schematic diagram for demonstrating the definition of the wetting spread rate of a solder. 比較例となるＢｉ単体の濡れ広がりと実施の形態１のはんだ合金の濡れ広がりとを示す写真である。It is a photograph which shows the wetting spread of the Bi simple substance used as a comparative example, and the wetting spread of the solder alloy of Embodiment 1. ＢｉへのＮｉ添加量と電気抵抗との関係を示すグラフである。It is a graph which shows the relationship between Ni addition amount to Bi, and electrical resistance. 本発明の実施の形態２に係るソルダペーストを用いたパッケージ部品の製造から表面実装までの工程を示す図である。It is a figure which shows the process from manufacture of the package components using the solder paste which concerns on Embodiment 2 of this invention to surface mounting. 本発明の実施の形態２に係るソルダペーストをダイボンド材に用いた半導体装置の一構成例を示す側面図である。It is a side view which shows one structural example of the semiconductor device which used the solder paste which concerns on Embodiment 2 of this invention for the die-bonding material.

以下に、図面を参照して本発明の実施の形態を説明する。本発明は、以下に説明する実施の形態によって限定されるものではない。   Embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to the embodiments described below.

実施の形態１．
本実施の形態１のはんだ合金は、融点が、例えば、２６０℃以上の高温はんだ合金に属するものである。本実施の形態１のはんだ合金は、全体の質量％のうち、質量％が０．０３質量％〜０．０９質量％のＮｉ（ニッケル）と、全体からＮｉ及び不可避不純物を除いた残部であるＢｉとを有する。本実施の形態１では、例えば、Ｎｉの質量％が０．０３質量％〜０．０９質量％である場合、Ｂｉ−０．０３％〜０．０９％Ｎｉ合金と表記する。 Embodiment 1 FIG.
The solder alloy of the first embodiment belongs to a high temperature solder alloy having a melting point of, for example, 260 ° C. or higher. The solder alloy of the first embodiment is Ni (nickel) whose mass% is 0.03 mass% to 0.09 mass% in the total mass%, and the balance obtained by removing Ni and inevitable impurities from the whole. Bi. In the first embodiment, for example, when the mass% of Ni is 0.03% by mass to 0.09% by mass, it is expressed as a Bi-0.03% to 0.09% Ni alloy.

（Ｂｉ−Ｎｉ合金の製造方法）
本実施の形態１のはんだ合金として、Ｂｉ−０．０３％〜０．０９％Ｎｉ合金の製造方法を説明する。Ｂｉ及びＮｉの各原料は純度が９９．９％以上のものを使用することが好ましい。Ｂｉ−０．０３％〜０．０９％Ｎｉ合金は、Ｂｉ及びＮｉと、不可避不純物とからなる。不可避不純物とは、主として、Ｃｕ（銅）、Ｎｉ、Ｚｎ（亜鉛）、Ｆｅ（鉄）、Ａｌ（アルミニウム）、Ａｓ（ヒ素）、Ｃｄ（カドミウム）、Ａｇ、Ａｕ（金）、Ｉｎ（インジウム）、Ｐ（リン）、Ｐｂ及びＳｎなどである。本実施の形態１では、Ｎｉを除いた不可避不純物の合計の質量％は、はんだ合金全体のうち、０．０１％未満である。特に、Ｓｎについて、本実施の形態１のはんだ合金は、不可避不純物としての質量％しか含んでいない。Ｂｉ−Ｓｎ共晶組成がはんだ合金の融点を低下させることを防ぐためである。 (Production method of Bi-Ni alloy)
As a solder alloy according to the first embodiment, a method for producing a Bi-0.03% to 0.09% Ni alloy will be described. It is preferable to use Bi and Ni raw materials having a purity of 99.9% or more. The Bi-0.03% to 0.09% Ni alloy is composed of Bi and Ni and inevitable impurities. Inevitable impurities are mainly Cu (copper), Ni, Zn (zinc), Fe (iron), Al (aluminum), As (arsenic), Cd (cadmium), Ag, Au (gold), In (indium). , P (phosphorus), Pb and Sn. In the first embodiment, the total mass% of inevitable impurities excluding Ni is less than 0.01% of the entire solder alloy. In particular, for Sn, the solder alloy of the first embodiment contains only mass% as an inevitable impurity. This is to prevent the Bi—Sn eutectic composition from lowering the melting point of the solder alloy.

融解において、Ｂｉ融点の２７１℃に対して、Ｎｉ融点は１４５１℃であり、両元素の融点差が大きすぎるため、純金属のＢｉにＮｉを添加すると、Ｎｉ添加時におけるＮｉの酸化又はＮｉの蒸発などによって目的組成にならないことが多い。そのため、添加する元素を目標濃度よりも高濃度に母材に含ませた母合金をあらかじめ作製し、作製した母合金に母材の元素を必要量添加することで、目的組成の合金を得る方法を採用した。母合金の組成は、Ｂｉ単体の融点に近いことが望ましい。   In melting, Ni melting point is 1451 ° C with respect to Bi melting point of 271 ° C, and the difference in melting point between both elements is too large. Therefore, when Ni is added to pure metal Bi, oxidation of Ni or Ni In many cases, the target composition is not obtained by evaporation or the like. Therefore, a method for obtaining an alloy having a target composition by preparing in advance a mother alloy in which the element to be added is contained in the base material at a concentration higher than the target concentration, and adding the necessary amount of the element of the base material to the prepared mother alloy. It was adopted. The composition of the mother alloy is preferably close to the melting point of Bi alone.

例えば、Ｂｉ−０．５％Ｎｉ合金である場合、この合金の融点は３２６℃であり、Ｂｉ融点に近い。そのため、Ｂｉ−０．５％Ｎｉ合金は母合金として適当である。例えば、目的組成の合金がＢｉ−０．０５％Ｎｉ合金である場合、１００ｇのＢｉ−０．５％合金に、９００ｇのＢｉを配合し、融解後凝固させる。このようにして、目的組成のＢｉ−０．０５％Ｎｉ合金を作製できる。   For example, in the case of a Bi-0.5% Ni alloy, the melting point of this alloy is 326 ° C., which is close to the Bi melting point. Therefore, a Bi-0.5% Ni alloy is suitable as a mother alloy. For example, when the alloy having the target composition is a Bi-0.05% Ni alloy, 900 g of Bi is added to 100 g of Bi-0.5% alloy and solidified after melting. In this way, a Bi-0.05% Ni alloy having the target composition can be produced.

（ＢｉへのＮｉ添加による延性の変化）
本実施の形態１のはんだ合金の基本特性として、Ｂｉ−Ｎｉ系合金の二元系状態図について説明する。図１は、Ｂｉ−Ｎｉ系合金の二元系状態図である。図１の横軸はＢｉへのＮｉの添加量［質量％］であり、縦軸は温度である。図１では、Ｎｉの添加量が０〜０．４％の範囲の状態図を示し、温度については、２７２℃以上の状態図の表示を省略している。 (Change in ductility due to Ni addition to Bi)
As a basic characteristic of the solder alloy according to the first embodiment, a binary phase diagram of a Bi—Ni alloy will be described. FIG. 1 is a binary phase diagram of a Bi—Ni alloy. The horizontal axis in FIG. 1 is the amount of Ni added to Bi [% by mass], and the vertical axis is temperature. In FIG. 1, a state diagram in which the addition amount of Ni is in a range of 0 to 0.4% is shown, and a state diagram of 272 ° C. or higher is omitted for the temperature.

図１を参照すると、Ｎｉの添加量が０〜０．４％の範囲で、固相線温度は一定の２６９．６５℃であるが、液相線温度はＮｉ添加量が０．２３％までは添加量が増すと低下する。Ｎｉを添加しないＢｉ単体では液相線温度は２７１．３５℃である。一方、０．２３％Ｎｉでは、液相線温度は２６９．６５℃である。Ｎｉ添加量が０．２３％を超えると液相線温度は急に高くなり、図１に示していないが、０．３５％で液相線温度は３００℃になる。したがって、固相線温度が２６０℃以上かつ液相線温度が３００℃以下という要求に対しては、Ｎｉ添加量が０〜０．３５％であればよいことがわかる。なお、Ｎｉ添加量が０．０９％では液相線温度は、２７０．７０℃である。   Referring to FIG. 1, the solidus temperature is a constant 269.65 ° C. in the range of 0 to 0.4% of Ni addition, but the liquidus temperature is up to 0.23% of Ni addition amount. Decreases with increasing amount. The liquidus temperature is 271.35 ° C. for Bi alone without adding Ni. On the other hand, at 0.23% Ni, the liquidus temperature is 269.65 ° C. When the Ni addition amount exceeds 0.23%, the liquidus temperature suddenly increases, and although not shown in FIG. 1, the liquidus temperature becomes 300 ° C. at 0.35%. Therefore, it is understood that the Ni addition amount should be 0 to 0.35% for the requirement that the solidus temperature is 260 ° C. or higher and the liquidus temperature is 300 ° C. or lower. When the Ni addition amount is 0.09%, the liquidus temperature is 270.70 ° C.

次に、Ｎｉ添加がＢｉの延性に及ぼす影響について説明する。Ｂｉ−Ｎｉ系合金の延性の評価を３点曲げ試験装置を用いて行った。図２は、延性評価に用いた３点曲げ試験装置の一構成例を示す外観図である。図２に示すように、３点曲げ試験装置１０は、押金具７と、評価対象物を支持する２つの支持台８と、２つの支持台８が設置された土台９とを有する。   Next, the influence of Ni addition on the ductility of Bi will be described. Evaluation of the ductility of the Bi-Ni alloy was performed using a three-point bending test apparatus. FIG. 2 is an external view showing a configuration example of a three-point bending test apparatus used for ductility evaluation. As shown in FIG. 2, the three-point bending test apparatus 10 includes a metal fitting 7, two support bases 8 that support an evaluation object, and a base 9 on which the two support bases 8 are installed.

評価対象の試験片６として、比較のためのＢｉ単体と、Ｎｉ添加量の異なるＢｉ−Ｎｉ系合金とを準備した。Ｎｉ添加量の異なるＢｉ−Ｎｉ系合金の試験片６は７種類準備した。全ての試験片６の寸法を共通にした。具体的には、各試験片６の寸法は、幅２０ｍｍ、厚さ１０ｍｍ、長さ１５０ｍｍである。   As a test piece 6 to be evaluated, a Bi simple substance for comparison and a Bi—Ni alloy having a different Ni addition amount were prepared. Seven types of Bi-Ni alloy test pieces 6 having different Ni addition amounts were prepared. The dimensions of all the test pieces 6 were made common. Specifically, each test piece 6 has a width of 20 mm, a thickness of 10 mm, and a length of 150 mm.

図２に示す３点曲げ試験装置１０において、支持台８の支持間隔は１３０ｍｍであり、支持肩部の円柱半径は５ｍｍであり、押金具７の先端の円柱半径は５ｍｍである。試験室の室内の温度を２５℃に一定に保ち、各試験片６を同じ環境下で試験した。試験片６毎に、試験片６を２つの支持台８で支持されるように置き、押金具７を速度１０ｍｍ／ｍｉｎで試験片６の中央付近に降下させる３点曲げ試験を行った。３点曲げ試験では、試験片６に亀裂が入るまで押金具７を降下させた。   In the three-point bending test apparatus 10 shown in FIG. 2, the support interval of the support base 8 is 130 mm, the columnar radius of the support shoulder is 5 mm, and the columnar radius of the tip of the pressing metal 7 is 5 mm. The temperature inside the test room was kept constant at 25 ° C., and each test piece 6 was tested under the same environment. For each test piece 6, a three-point bending test was performed in which the test piece 6 was placed so as to be supported by the two support bases 8, and the pusher 7 was lowered near the center of the test piece 6 at a speed of 10 mm / min. In the three-point bending test, the metal fitting 7 was lowered until the test piece 6 was cracked.

図３は、評価対象の試験片について３点曲げ試験後の状態を示す写真である。図３には、Ｂｉ−Ｎｉ系合金について、７種類の試験片６のうち、代表的な４種類を示している。図３に示す４種類のＢｉ−Ｎｉ系合金は、Ｂｉ−０．０３５％Ｎｉ合金、Ｂｉ−０．０５３％Ｎｉ合金、Ｂｉ−０．１３％Ｎｉ合金、及びＢｉ−０．２１％Ｎｉ合金である。図３に示すように、Ｂｉ−０．０５３％Ｎｉ合金を除く４種類の試験片６には、亀裂が入っている。一方、Ｂｉ−０．０５３％Ｎｉ合金の試験片６は、大きくたわんでいるが、亀裂が入っていない。これは、試験片６の中央付近が土台９に接触するまで試験片６がたわんでも亀裂が入らず、亀裂が入るまで押金具７を降下させることができなかったためである。Ｂｉ−０．０５３％Ｎｉ合金は、他の４種類の試験片６と比べて、曲げたわみが大きく、延性が大きいことがわかる。   FIG. 3 is a photograph showing a state after a three-point bending test on the test piece to be evaluated. FIG. 3 shows four representative types of the seven types of test pieces 6 for the Bi—Ni-based alloy. The four types of Bi-Ni alloys shown in FIG. 3 are Bi-0.035% Ni alloy, Bi-0.053% Ni alloy, Bi-0.13% Ni alloy, and Bi-0.21% Ni alloy. It is. As shown in FIG. 3, the four types of test pieces 6 excluding the Bi-0.053% Ni alloy have cracks. On the other hand, the Bi-0.053% Ni alloy test piece 6 is largely bent, but is not cracked. This is because a crack does not occur even when the test piece 6 is bent until the vicinity of the center of the test piece 6 comes into contact with the base 9, and the pusher 7 cannot be lowered until the crack is formed. It can be seen that the Bi-0.053% Ni alloy has a larger bending deflection and a higher ductility than the other four types of test pieces 6.

図４は、ＢｉへのＮｉ添加量と曲げたわみとの関係を示すグラフである。図４の縦軸は、上述した３点曲げ試験において、試験片６に亀裂が入るまでの曲げたわみを示し、横軸はＢｉへのＮｉの添加量［質量％］を示す。矢印のあるプロットは、図２に示した３点曲げ試験装置１０の寸法上の制約から、亀裂が入るまでたわませることができなかったことを示す。図４に示すグラフから、ＢｉへのＮｉ添加量が増加するにつれて、合金の延性が向上し、Ｎｉ添加量が０．０５％〜０．０７％で合金の延性がピークを示し、それ以上Ｎｉ添加量が増加すると、合金の延性が低下することがわかる。   FIG. 4 is a graph showing the relationship between the amount of Ni added to Bi and the bending deflection. The vertical axis in FIG. 4 indicates the bending deflection until the test piece 6 is cracked in the above-described three-point bending test, and the horizontal axis indicates the addition amount [mass%] of Ni to Bi. A plot with an arrow indicates that the three-point bending test apparatus 10 shown in FIG. 2 cannot be deflected until it cracks due to dimensional constraints. From the graph shown in FIG. 4, as the amount of Ni added to Bi increases, the ductility of the alloy improves, and when the amount of Ni added is 0.05% to 0.07%, the ductility of the alloy shows a peak. It can be seen that as the amount added increases, the ductility of the alloy decreases.

Ｂｉ単体は、高い融点を示すが脆いため、熱疲労による劣化が生じ易かった。このようなＢｉ単体にＮｉを添加することで、上述したように、合金の延性が向上し、耐熱疲労性を向上させることができる。ダイボンド用はんだとして実績のある高鉛はんだの一例であるＰｂ−１０％Ｓｎ−２．５％Ａｇの伸び率が１５％に対し、Ｂｉ単体の伸び率は５％である。このことから、はんだに適用し得る、Ｂｉ単体へのＮｉ添加による延性改善の目安として、押込み長を３倍とした。Ｂｉ単体にＮｉを添加しない場合、押込み長が８ｍｍで折れることから、押込み長が３倍となる２４ｍｍになるＮｉ添加量は、０．０３％〜０．０９％であればよい。   Bi alone has a high melting point but is fragile, so that deterioration due to thermal fatigue is likely to occur. By adding Ni to such Bi alone, as described above, the ductility of the alloy can be improved and the thermal fatigue resistance can be improved. The elongation of Pb-10% Sn-2.5% Ag, which is an example of a high lead solder that has been proven as a solder for die bonding, is 15%, whereas the elongation of Bi alone is 5%. For this reason, the indentation length was tripled as a measure for improving ductility by adding Ni to Bi alone, which can be applied to solder. When Ni is not added to Bi alone, the indentation length is broken at 8 mm, and therefore the Ni addition amount to be 24 mm, which is three times the indentation length, may be 0.03% to 0.09%.

はんだ合金におけるＮｉの役目として、例えば、Ｓｎ−Ａｇ−Ｃｕ系合金において、はんだと銅基板との接合界面における金属間化合物の形成を抑制することは知られている。これに対して、今回、上述の３点曲げ試験及び評価結果で説明したように、ＮｉがＢｉ単体に延性を向上させる効果を生じさせることがわかった。以下では、Ｂｉ−Ｎｉ系合金が高温はんだとして適用し得るか、さらに評価した結果を説明する。   As a role of Ni in a solder alloy, for example, in a Sn—Ag—Cu-based alloy, it is known to suppress formation of an intermetallic compound at a joint interface between a solder and a copper substrate. On the other hand, as described in the above-described three-point bending test and evaluation results, it has been found that Ni causes an effect of improving ductility in Bi alone. Below, the result of having further evaluated whether a Bi-Ni-type alloy can be applied as a high temperature solder is demonstrated.

（Ｎｉを添加したＢｉ基合金の圧延）
本実施の形態１のはんだ合金は、ＢｉにＮｉを添加したＢｉ基合金に相当するが、Ｎｉを０．０３質量％〜０．０９質量％含有するものである。本実施の形態１のはんだ合金のうち、Ｎｉを０．０５質量％〜０．０７質量％含有する場合、延性がより大きくなり、塑性加工性の観点からより優れている。ここでは、Ｂｉ−０．０７％Ｎｉ合金について圧延評価の結果を説明する。 (Rolling Bi-based alloy with Ni added)
The solder alloy according to the first embodiment corresponds to a Bi-based alloy obtained by adding Ni to Bi, but contains 0.03% by mass to 0.09% by mass of Ni. In the solder alloy of the first embodiment, when Ni is contained in an amount of 0.05% by mass to 0.07% by mass, the ductility becomes larger and is more excellent from the viewpoint of plastic workability. Here, the results of the rolling evaluation for the Bi-0.07% Ni alloy will be described.

図５は、比較例となるＢｉ単体の冷間圧延後の外観形状を示す写真である。具体的には、図５は、Ｂｉ単体に対して、冷間圧延により０．５ｍｍ厚さのはんだテープ製造を試みたものを示す。図６は、本発明の実施の形態１に係るはんだ合金の冷間圧延後の外観形状を示す写真である。図６は、Ｂｉ−０．０７％Ｎｉ合金に対して、冷間圧延により厚さ０．３ｍｍの成形はんだを作製したものを示す。   FIG. 5 is a photograph showing the external shape after cold rolling of a single Bi as a comparative example. Specifically, FIG. 5 shows an attempt to produce a 0.5 mm thick solder tape by cold rolling for Bi alone. FIG. 6 is a photograph showing the external shape of the solder alloy according to Embodiment 1 of the present invention after cold rolling. FIG. 6 shows a Bi-0.07% Ni alloy produced by forming a formed solder having a thickness of 0.3 mm by cold rolling.

図５に示すように、Ｂｉは単体では非常に脆く、冷間圧延すると割れてしまうため、成形はんだにならない。一方、図６に示すように、Ｂｉ−０．０７％Ｎｉ合金は延性があり冷間圧延ができることがわかる。   As shown in FIG. 5, Bi is very brittle by itself and cracks when cold-rolled, so it does not become a molded solder. On the other hand, as shown in FIG. 6, it can be seen that the Bi-0.07% Ni alloy is ductile and can be cold rolled.

ここで、成形はんだの作製方法を詳しく説明する。約５ｍｍの厚さの鋳込み材を、圧下率５０％で冷間圧延を繰り返し、０．５ｍｍ厚さのテープ状にした。その後の冷間圧延では、０．１ｍｍずつテープの厚さを減少させ、厚さ０．３ｍｍのテープとした後、テープをカットして、厚さが０．３ｍｍで、一辺が４ｍｍの正方形の成形はんだを作製した。図６に示すように、本実施の形態１のはんだ合金は、Ｂｉ基合金であっても、圧延が可能であることが明らかである。なお、圧延について、はんだ合金がＢｉ−０．０７％Ｎｉ合金の場合で説明したが、Ｎｉ添加量が０．０３％〜０．０９％の範囲で、はんだとして使用できるものであった。   Here, a method for producing the molded solder will be described in detail. The cast material having a thickness of about 5 mm was repeatedly cold-rolled at a reduction rate of 50% to form a tape having a thickness of 0.5 mm. In the subsequent cold rolling, the thickness of the tape is reduced by 0.1 mm to obtain a tape having a thickness of 0.3 mm, and then the tape is cut into a square having a thickness of 0.3 mm and a side of 4 mm. Molded solder was produced. As shown in FIG. 6, it is apparent that the solder alloy of the first embodiment can be rolled even if it is a Bi-based alloy. In addition, about rolling, although demonstrated when the solder alloy was a Bi-0.07% Ni alloy, it could be used as a solder in the range of Ni addition amount 0.03% to 0.09%.

（Ｎｉ添加したＢｉ基合金の濡れ性向上）
本実施の形態１のはんだ合金について、濡れ性を評価した。濡れ性評価では、比較例としてＢｉ単体を用いた。濡れ性の評価には、濡れ広がり試験における濡れ広がり率を用いた。評価に用いた濡れ広がり率の定義を、図７を参照して説明する。図７は、はんだの濡れ広がり率の定義を説明するための模式図である。 (Improvement of wettability of Bi-based alloys with Ni added)
The wettability of the solder alloy according to the first embodiment was evaluated. In the wettability evaluation, Bi alone was used as a comparative example. For the evaluation of wettability, the wet spread rate in the wet spread test was used. The definition of the wetting spread rate used for the evaluation will be described with reference to FIG. FIG. 7 is a schematic diagram for explaining the definition of the solder spreading rate.

試験に使用されるはんだについて、溶融前の基板上のはんだを直径Ｄの球体と考える。直径Ｄの球体という形状から、はんだの量が決まる。球体と仮定したはんだを１０％の水素を含む窒素中で３２０℃の温度で溶融させると、はんだは、Ｎｉめっき板に濡れ広がる。溶融後に基板上に広がったはんだの高さをＨとすると、濡れ広がり率は、式（２）で定義される。濡れ広がり率に関連する直径Ｄ及び高さＨは、ＪＩＳ Ｚ３１９７：１９９９に準拠した方法で測定した。   Regarding the solder used in the test, the solder on the substrate before melting is considered as a sphere having a diameter D. The amount of solder is determined from the shape of a sphere of diameter D. When the solder assumed to be a sphere is melted at a temperature of 320 ° C. in nitrogen containing 10% hydrogen, the solder wets and spreads on the Ni-plated plate. Assuming that the height of the solder spread on the substrate after melting is H, the wetting spread rate is defined by equation (2). The diameter D and the height H related to the wet spreading rate were measured by a method based on JIS Z3197: 1999.

Figure 2019188456
Figure 2019188456

図８は、比較例となるＢｉ単体の濡れ広がりと実施の形態１のはんだ合金の濡れ広がりとを示す写真である。図８（ａ）がＢｉ単体の場合を示し、図８（ｂ）はＢｉ−０．０７％Ｎｉ合金の場合を示す。図８を参照すると、図８（ｂ）に示すＢｉ−０．０７％Ｎｉ合金の濡れ広がりの方が、図８（ａ）に示すＢｉ単体の濡れ広がりに比べて広がりが大きいことは、明らかである。   FIG. 8 is a photograph showing the wetting and spreading of Bi alone as a comparative example and the wetting and spreading of the solder alloy of the first embodiment. FIG. 8A shows the case of Bi alone, and FIG. 8B shows the case of Bi-0.07% Ni alloy. Referring to FIG. 8, it is clear that the Bi-0.07% Ni alloy wet spread shown in FIG. 8B is larger than the Bi single wet spread shown in FIG. 8A. It is.

Ｂｉ単体の濡れ広がり率は、直径Ｄ及び高さＨの測定値を式（２）に代入することで、５８％と算出される。一方、はんだ合金がＢｉ−０．０７％Ｎｉである場合、濡れ広がり率は、直径Ｄ及び高さＨの測定値を式（２）に代入することで、７４％と算出された。図８に示した外観形状だけでなく、濡れ性の評価値で比較しても、Ｂｉ単体よりもＢｉ−０．０７％Ｎｉが優れていることがわかった。ＢｉにＮｉを添加することで、Ｂｉ単体と比較して、濡れ性が改善する効果が得られる。なお、濡れ性について、はんだ合金がＢｉ−０．０７％Ｎｉ合金の場合で説明したが、Ｎｉ添加量が０．０３％〜０．０９％の範囲で、はんだとして使用できるものであった。   The wet spread rate of Bi alone is calculated as 58% by substituting the measured values of the diameter D and the height H into the equation (2). On the other hand, when the solder alloy is Bi-0.07% Ni, the wetting spread rate was calculated as 74% by substituting the measured values of the diameter D and the height H into the formula (2). When comparing not only the appearance shape shown in FIG. 8 but also the evaluation value of wettability, it was found that Bi-0.07% Ni was superior to Bi alone. By adding Ni to Bi, an effect of improving wettability can be obtained as compared with Bi alone. The wettability has been described in the case where the solder alloy is a Bi-0.07% Ni alloy. However, it was possible to use it as solder when the Ni addition amount was in the range of 0.03% to 0.09%.

（Ｎｉ添加したＢｉ基合金の電気抵抗の改善）
Ｂｉ単体は、融点が高い点では、Ｐｂフリー高温はんだの候補の１つとなり得るが、電気抵抗が従来のＰｂフリー高温はんだに比べて大きい。図９は、ＢｉへのＮｉ添加量と電気抵抗との関係を示すグラフである。 (Improvement of electrical resistance of Ni-added Bi-based alloy)
Bi alone can be one of the candidates for Pb-free high-temperature solder because of its high melting point, but its electrical resistance is higher than that of conventional Pb-free high-temperature solder. FIG. 9 is a graph showing the relationship between the amount of Ni added to Bi and the electrical resistance.

図９に示すように、Ｎｉ添加量が０％から増加するにつれて電気抵抗が減少し、Ｎｉ添加量が０．０６％付近で電気抵抗が最小になる。Ｎｉ添加量が０．０６％より大きくなると、電気抵抗が増大する傾向がある。図９に示すグラフから、Ｂｉ単体の電気抵抗が１．７μΩ・ｍに対し、Ｂｉに０．０３％〜０．０９％のＮｉ添加を行うと、１．２０〜１．３３μΩ・ｍとなる。そのため、Ｂｉ−０．０３〜０．０９％Ｎｉの電気抵抗はＢｉ単体に比べて２４〜３１％低下しており、電気抵抗が改善される。また、Ｂｉに０．０５％〜０．０７％のＮｉ添加では、電気抵抗は１．２０〜１．２３μΩ・ｍとなり、Ｂｉ単体に比べて３０〜３１％の改善がはかれる。   As shown in FIG. 9, the electrical resistance decreases as the Ni addition amount increases from 0%, and the electrical resistance is minimized when the Ni addition amount is around 0.06%. When the amount of Ni added is greater than 0.06%, the electrical resistance tends to increase. From the graph shown in FIG. 9, when the electric resistance of Bi alone is 1.7 μΩ · m and Ni is added in an amount of 0.03% to 0.09% to Bi, it becomes 1.20 to 1.33 μΩ · m. . Therefore, the electrical resistance of Bi-0.03 to 0.09% Ni is 24 to 31% lower than that of Bi alone, and the electrical resistance is improved. Moreover, when 0.05% to 0.07% Ni is added to Bi, the electric resistance is 1.20 to 1.23 μΩ · m, which is 30% to 31% improvement over Bi alone.

本実施の形態１のはんだ合金は、全体の質量％のうち、０．０３質量％〜０．０９質量％のＮｉと、全体からＮｉ及び不可避不純物を除いた残部であるＢｉとからなるものである。本実施の形態１によれば、Ｂｉ単体に比べて延性が向上する。Ｂｉ単体にＮｉを添加することは、Ｂｉの延性を向上させるという新たな効果をもたらすものである。また、本実施の形態１のはんだ合金は、高温はんだとしての融点の条件を満たす。さらに、本実施の形態１のはんだ合金は、はんだとしての濡れ性の条件を満たし、Ｂｉ単体に比べて電気抵抗も改善する。本実施の形態１では、固相線温度が２６０℃から３００℃の範囲で融点が高く、延性の大きいＰｂフリーはんだ合金を提供することができる。   The solder alloy according to the first embodiment is composed of 0.03% by mass to 0.09% by mass of Ni in the total mass%, and Bi which is the balance excluding Ni and inevitable impurities from the entire mass%. is there. According to the first embodiment, ductility is improved as compared with Bi alone. Adding Ni to Bi alone brings about a new effect of improving the ductility of Bi. Further, the solder alloy of the first embodiment satisfies the melting point condition as a high-temperature solder. Furthermore, the solder alloy according to the first embodiment satisfies the condition of wettability as a solder and improves the electric resistance as compared with Bi alone. In the first embodiment, it is possible to provide a Pb-free solder alloy having a high melting point and a high ductility when the solidus temperature is in the range of 260 ° C. to 300 ° C.

また、本実施の形態１のはんだ合金は、Ｎｉを０．０５質量％〜０．０７質量％含有してもよい。この場合、はんだ合金の延性がさらに向上するとともに、電気抵抗がさらに小さくなる。   Moreover, the solder alloy of the first embodiment may contain 0.05 mass% to 0.07 mass% of Ni. In this case, the ductility of the solder alloy is further improved and the electric resistance is further reduced.

実施の形態２．
実施の形態１で説明したはんだ合金の使用形態の一例として、はんだ合金の粉末とフラックスとを混錬したソルダペーストが考えられる。本実施の形態２は、実施の形態１で説明したはんだ合金をソルダペーストに適用したものである。 Embodiment 2. FIG.
As an example of the usage form of the solder alloy described in the first embodiment, a solder paste in which a solder alloy powder and a flux are kneaded can be considered. In the second embodiment, the solder alloy described in the first embodiment is applied to a solder paste.

本実施の形態２のソルダペーストは、Ｂｉ−０．０３％〜０．０７％Ｎｉ合金の粉末と、フラックスとが混錬されたものである。はんだ合金の粉末の粒径としては、粒径分布が５〜５０μｍの範囲にあるものが好ましく、粒径分布が２５〜４５μｍの範囲にあるものがさらに好ましい。   The solder paste according to the second embodiment is obtained by kneading Bi-0.03% to 0.07% Ni alloy powder and flux. The solder alloy powder preferably has a particle size distribution in the range of 5 to 50 μm, more preferably a particle size distribution in the range of 25 to 45 μm.

フラックスとしては、任意のフラックスを用いることができ、例えば、ロジン系フラックスを用いてもよい。好ましくは、４５〜５５質量部の重合ロジン、４１〜５１質量部のブチルカルビトール、０．５〜１質量部のシクロヘキシルアミンＨＢｒ塩、０．５〜１質量部のアジピン酸、及び２〜４質量部の水素添加ヒマシ油を組成とするフラックスを、はんだ合金粉末に組み合わせることは、濡れ性の改善により効果的である。このフラックス以外にも、４５〜５５質量部の混合ロジン（重合ロジン：水素添加ロジン＝１：３）、４１〜５１質量部のヘキシルジグリコール、０．５〜５質量部の２，３−ジブロモ−１，４−ブテンジオール、０．５〜１質量部のアジピン酸、及び２〜４質量部の水素添加ヒマシ油を組成とするフラックスを用いてもよい。フラックスとはんだ合金粉末との質量比は、８０：２０〜９０：１０とすることが好ましく、８５：１５〜９０：１０とすることがさらに好ましい。   Arbitrary flux can be used as a flux, For example, you may use a rosin-type flux. Preferably, 45-55 parts by weight polymerized rosin, 41-51 parts by weight butyl carbitol, 0.5-1 part by weight cyclohexylamine HBr salt, 0.5-1 part by weight adipic acid, and 2-4 It is more effective to improve the wettability to combine the flux composed of part by mass of hydrogenated castor oil with the solder alloy powder. In addition to this flux, 45 to 55 parts by mass of mixed rosin (polymerized rosin: hydrogenated rosin = 1: 3), 41 to 51 parts by mass of hexyl diglycol, 0.5 to 5 parts by mass of 2,3-dibromo A flux composed of -1,4-butenediol, 0.5 to 1 part by mass of adipic acid, and 2 to 4 parts by mass of hydrogenated castor oil may be used. The mass ratio of the flux to the solder alloy powder is preferably 80:20 to 90:10, and more preferably 85:15 to 90:10.

本実施の形態２のソルダペーストがＩＣなどの半導体装置に用いられる場合を説明する。図１０は、本発明の実施の形態２に係るソルダペーストを用いたパッケージ部品の製造から表面実装までの工程を示す図である。   A case where the solder paste of the second embodiment is used in a semiconductor device such as an IC will be described. FIG. 10 is a diagram showing steps from manufacture of a package component using the solder paste according to the second embodiment of the present invention to surface mounting.

図１０（ａ）に示すように、ダイパッド２１上に半導体チップ２２を搭載した後、本実施の形態２のソルダペースト２３でダイパッド２１と半導体チップ２２とを接合する。続いて、半導体チップ２２のパッドとリードフレーム２４とを接続するワイヤーボンディングを行った後、図１０（ｂ）に示すように、半導体チップ２２及びダイパッド２１を樹脂２５で覆い、パッケージ部品２６が作製される。   As shown in FIG. 10A, after mounting the semiconductor chip 22 on the die pad 21, the die pad 21 and the semiconductor chip 22 are joined with the solder paste 23 of the second embodiment. Subsequently, after wire bonding for connecting the pads of the semiconductor chip 22 and the lead frame 24 is performed, the semiconductor chip 22 and the die pad 21 are covered with a resin 25 as shown in FIG. Is done.

パッケージ部品２６は、半導体チップ２２と、半導体チップ２２を支持するダイパッド２１と、半導体チップ２２とダイパッド２１との間に設けられたはんだ合金２３ａと、半導体チップ２２及びダイパッド２１を覆う樹脂２５とを有する。その後、図１０（ｃ）に示すように、パッケージ部品２６をプリント基板２７の上に搭載し、ソルダペースト２８でリードフレーム２４と配線２９とを接合するリフローが行われる。このリフロー工程は、例えば、温度２６０℃のリフロー工程である。   The package component 26 includes a semiconductor chip 22, a die pad 21 that supports the semiconductor chip 22, a solder alloy 23 a provided between the semiconductor chip 22 and the die pad 21, and a resin 25 that covers the semiconductor chip 22 and the die pad 21. Have. Thereafter, as shown in FIG. 10C, the package component 26 is mounted on the printed circuit board 27, and reflow is performed to join the lead frame 24 and the wiring 29 with the solder paste 28. This reflow process is a reflow process at a temperature of 260 ° C., for example.

リードフレーム２４と配線２９とを接合するリフロー工程において、温度が２６０℃になっても、パッケージ部品２６内のはんだ合金２３ａの融点は２６０℃よりも高いため、再溶融しない。そのため、本実施の形態２では、耐リフロー性を確保し、階層はんだ付けの接合信頼性を確保することができる。   In the reflow process for joining the lead frame 24 and the wiring 29, even if the temperature reaches 260 ° C., the melting point of the solder alloy 23a in the package component 26 is higher than 260 ° C., and therefore does not remelt. Therefore, in this Embodiment 2, reflow resistance can be ensured and the joining reliability of hierarchical soldering can be ensured.

本実施の形態２のソルダペーストがパワーデバイスのダイボンド材に用いられる場合を説明する。図１１は、本発明の実施の形態２に係るソルダペーストをダイボンド材に用いた半導体装置の一構成例を示す側面図である。半導体装置３０は、例えば、パワーデバイスである。半導体装置３０は、半導体チップ１と、半導体チップ１を支持する絶縁基板３と、絶縁基板３と半導体チップ１との間に設けられたはんだ合金２とを有する。半導体チップ１は、パワー半導体チップである。絶縁基板３は、銅回路板３ａ及び３ｃと、銅回路板３ａ及び３ｃに挟まれたアルミナセラミックス板３ｂとを有する。図１１に示す半導体装置３０では、上部ダイボンド材として、本実施の形態２のソルダペーストが用いられている。はんだ合金２は本実施の形態２のソルダペーストに含まれるはんだ合金である。   The case where the solder paste of this Embodiment 2 is used for the die-bonding material of a power device is demonstrated. FIG. 11 is a side view showing a configuration example of a semiconductor device using the solder paste according to the second embodiment of the present invention as a die bond material. The semiconductor device 30 is, for example, a power device. The semiconductor device 30 includes a semiconductor chip 1, an insulating substrate 3 that supports the semiconductor chip 1, and a solder alloy 2 provided between the insulating substrate 3 and the semiconductor chip 1. The semiconductor chip 1 is a power semiconductor chip. The insulating substrate 3 has copper circuit boards 3a and 3c and an alumina ceramic board 3b sandwiched between the copper circuit boards 3a and 3c. In the semiconductor device 30 shown in FIG. 11, the solder paste of the second embodiment is used as the upper die bond material. Solder alloy 2 is a solder alloy contained in the solder paste of the second embodiment.

半導体装置３０の上部ダイボンド材に本実施の形態２のソルダペーストを用いることで、はんだ合金２は、延性が大きいため、半導体装置３０の動作と停止との繰り返しによる熱サイクルに起因する劣化が抑制される。その結果、従来のＰｂフリー高温はんだ合金に比べて、接合信頼性が向上する。   By using the solder paste of the second embodiment for the upper die bond material of the semiconductor device 30, the solder alloy 2 has high ductility, so that deterioration due to a thermal cycle due to repeated operation and stop of the semiconductor device 30 is suppressed. Is done. As a result, the bonding reliability is improved as compared with the conventional Pb-free high temperature solder alloy.

また、図１１に示すように、半導体装置３０において、半導体チップ１から発生する熱を放出する放熱板５が、絶縁基板３の裏面に設けられていてもよい。絶縁基板３と放熱板５とは、はんだ合金４で接合されている。図１１に示す半導体装置３０では、下部ダイボンド材として、本実施の形態２のソルダペーストが用いられてもよい。この場合、はんだ合金４は、本実施の形態２のソルダペーストに含まれるはんだ合金である。   In addition, as shown in FIG. 11, in the semiconductor device 30, a heat radiating plate 5 that releases heat generated from the semiconductor chip 1 may be provided on the back surface of the insulating substrate 3. The insulating substrate 3 and the heat sink 5 are joined with a solder alloy 4. In the semiconductor device 30 shown in FIG. 11, the solder paste of the second embodiment may be used as the lower die bond material. In this case, the solder alloy 4 is a solder alloy included in the solder paste of the second embodiment.

例えば、上部ダイボンド材に要求される融点が３００℃以上の高温である場合、下部ダイボンド材として選択されるはんだ合金４の融点が３００℃より低くなるように、本実施の形態２のソルダペーストを適用することができる。この場合、半導体チップ１及び絶縁基板３を接合した後、絶縁基板３及び放熱板５を接合する際、３００℃の高温で加熱しても、上部ダイボンド材が溶融しない。   For example, when the melting point required for the upper die bond material is a high temperature of 300 ° C. or higher, the solder paste of the second embodiment is used so that the melting point of the solder alloy 4 selected as the lower die bond material is lower than 300 ° C. Can be applied. In this case, after bonding the semiconductor chip 1 and the insulating substrate 3, the upper die-bonding material does not melt even when heated at a high temperature of 300 ° C. when bonding the insulating substrate 3 and the heat sink 5.

なお、半導体装置３０が、パワー半導体チップを有するパワーデバイスの場合で説明したが、半導体装置はパワーデバイスに限らない。半導体装置３０は、動作すると高温を発生する半導体チップが搭載されていれば、本実施の形態２のソルダペーストをダイボンド材に適用できる。   Although the semiconductor device 30 has been described as a power device having a power semiconductor chip, the semiconductor device is not limited to a power device. As long as the semiconductor device 30 is mounted with a semiconductor chip that generates a high temperature when it operates, the solder paste of the second embodiment can be applied to the die bond material.

実施の形態３．
実施の形態１で説明したＢｉ−０．０５％〜０．０７％Ｎｉ合金は、延性がより大きく、圧延可能であることから、はんだの使用形態として、実施の形態２で説明したソルダペーストだけでなく、成形はんだとすることができる。本実施の形態３は、実施の形態１で説明したはんだ合金を、成形はんだに適用したものである。 Embodiment 3 FIG.
Since the Bi-0.05% to 0.07% Ni alloy described in the first embodiment has higher ductility and can be rolled, only the solder paste described in the second embodiment is used as a solder usage pattern. Instead, it can be formed solder. In the third embodiment, the solder alloy described in the first embodiment is applied to molded solder.

本実施の形態３の成形はんだは、０．０５質量％〜０．０７質量％のＮｉと、Ｎｉ及び不可避不純物を除いた残部であるＢｉとで構成される。本実施の形態３による成形はんだとしては、板状、線状及びリング状等の形状が可能である。本実施の形態３による成形はんだは、用途に合わせて、一定の形状に成形されたものである。成形はんだの形状及び寸法は、限定されない。接合対象に適合するように、成形のはんだの形状及び寸法を適宜、選択すればよい。   The molded solder according to the third embodiment is composed of 0.05 mass% to 0.07 mass% of Ni and Bi which is the balance excluding Ni and inevitable impurities. The molded solder according to the third embodiment can have a plate shape, a line shape, a ring shape, or the like. The molded solder according to the third embodiment is formed into a certain shape according to the application. The shape and dimensions of the molded solder are not limited. What is necessary is just to select suitably the shape and dimension of the shaping | molding solder so that it may suit a joining object.

実施の形態１で説明したＢｉ−０．０５％〜０．０７％Ｎｉ合金を成形はんだとする場合、実施の形態２で説明したフラックスを接合対象部材に塗布し、その上に成形はんだを置いて、決められた温度プロファイルで接合すればよい。また、フラックスの体積は、成形はんだと同体積、又は成形はんだの１．２倍程度の体積になるように、フラックスを用いればよい。温度プロファイルの具体例として、１５０〜２２０℃、好ましくは１７０〜２００℃で１００〜１３０秒加熱する予備加熱工程の後、加熱ピーク温度を３５０℃以下として、２７０℃以上で４０〜１２０秒保持する加熱工程を行うことが考えられる。本実施の形態３のはんだ合金を、最適なフラックスと組み合わせ、上記温度プロファイルで接合することで、はんだ合金の濡れ性を著しく改善することができる。   When the Bi-0.05% to 0.07% Ni alloy described in the first embodiment is used as a molded solder, the flux described in the second embodiment is applied to a member to be joined, and the molded solder is placed thereon. Then, it is only necessary to bond with a predetermined temperature profile. Moreover, what is necessary is just to use a flux so that the volume of a flux may become the same volume as a molded solder, or about 1.2 times the volume of a molded solder. As a specific example of the temperature profile, after the preheating step of heating at 150 to 220 ° C., preferably 170 to 200 ° C. for 100 to 130 seconds, the heating peak temperature is set to 350 ° C. or lower and held at 270 ° C. or higher and held for 40 to 120 seconds. It is conceivable to perform a heating step. The wettability of the solder alloy can be remarkably improved by combining the solder alloy of the third embodiment with the optimum flux and joining with the above temperature profile.

また、本実施の形態３の成形はんだでは、フラックスを使用せずに、水素又はギ酸など活性雰囲気の環境下で接合することもできる。この場合、加熱温度をＢｉの固相線温度２７０℃以上とし、加熱ピーク温度を合金の液相線温度＋３０℃程度に設定する。加熱時間は少なくとも６０秒以上保持することで、良好な濡れ性が得られる。加熱ピーク温度に関しては、必ずしも液相線温度以上である必要はなく、純粋なＢｉにより近い成分の場合は、純粋なＢｉの固相線温度である２７０℃＋３０℃程度の加熱をすることで、活性雰囲気においても良好な接合が確保できる。   Further, the molded solder of the third embodiment can be joined in an active atmosphere environment such as hydrogen or formic acid without using a flux. In this case, the heating temperature is set to 270 ° C. or higher for the Bi solidus temperature, and the heating peak temperature is set to about the liquidus temperature of the alloy + 30 ° C. Good wettability can be obtained by maintaining the heating time for at least 60 seconds. With regard to the heating peak temperature, it is not always necessary to be higher than the liquidus temperature, and in the case of a component closer to pure Bi, by heating at about 270 ° C. + 30 ° C., which is the solidus temperature of pure Bi, Good bonding can be secured even in an active atmosphere.

また、本実施の形態３の成形はんだを、図１１に示した半導体装置３０の上部ダイボンド材及び下部ダイボンド材のうち、一方又は両方に適用することができる。成形はんだにおいては、フラックスを使用せず、水素又はギ酸など活性雰囲気の環境下で接合することが一般的であるが、フラックスを接合対象部材に塗布し、その上に成形はんだを置いて、決められた温度プロファイルで接合してもよい。   Further, the molded solder according to the third embodiment can be applied to one or both of the upper die bond material and the lower die bond material of the semiconductor device 30 shown in FIG. In the case of molded solder, it is common to bond in an active atmosphere environment such as hydrogen or formic acid without using flux. However, the flux is applied to the members to be bonded, and the molded solder is placed on it and determined. Bonding may be performed with a given temperature profile.

本発明のはんだ合金は、電子機器全般において、半導体チップ等のダイボンド接合部に適用することができる。本発明のはんだ合金は、例えば、ＩＣなどパッケージ部品に好適である。また、発熱の大きい部品、例えば、ＬＥＤ素子及びパワーダイオードなどパワー半導体デバイスのダイボンド接合部に、本発明のはんだ合金を適用することができる。さらに、プリント配線板などに搭載される電子部品全般におけるＩＣ素子などの内部接続のダイボンド接合部に、本発明のはんだ合金は好適である。応用される製品として、上記のＬＥＤ素子を用いた照明部品、インバータの駆動回路、及びパワーモジュールといわれる電力変換機などが対象として挙げられる。   The solder alloy of the present invention can be applied to die bond joints such as semiconductor chips in all electronic devices. The solder alloy of the present invention is suitable for package parts such as an IC. Also, the solder alloy of the present invention can be applied to components that generate large amounts of heat, for example, die-bonded joints of power semiconductor devices such as LED elements and power diodes. Furthermore, the solder alloy of the present invention is suitable for internal connection die-bond joints such as IC elements in all electronic components mounted on printed wiring boards and the like. Examples of products to be applied include lighting components using the above LED elements, inverter drive circuits, and power converters called power modules.

１ 半導体チップ、２ はんだ合金、３ 絶縁基板、３ａ 銅回路板、３ｂ アルミナセラミックス板、３ｃ 銅回路板、４ はんだ合金、５ 放熱板、６ 試験片、７ 押金具、８ 支持台、９ 土台、１０ ３点曲げ試験装置、２１ ダイパッド、２２ 半導体チップ、２３ ソルダペースト、２３ａ はんだ合金、２４ リードフレーム、２６ パッケージ部品、２７ プリント基板、２８ ソルダペースト、２９ 配線、３０ 半導体装置。   DESCRIPTION OF SYMBOLS 1 Semiconductor chip, 2 Solder alloy, 3 Insulation board, 3a Copper circuit board, 3b Alumina ceramic board, 3c Copper circuit board, 4 Solder alloy, 5 Heat sink, 6 Test piece, 7 Pressing bracket, 8 Support base, 9 Base, 10 3 point bending test equipment, 21 die pad, 22 semiconductor chip, 23 solder paste, 23a solder alloy, 24 lead frame, 26 package component, 27 printed circuit board, 28 solder paste, 29 wiring, 30 semiconductor device.

Claims (7)

全体の質量％のうち、０．０３質量％〜０．０９質量％のニッケルと、
全体から前記ニッケル及び不可避不純物を除いた残部であるビスマスと、
からなるはんだ合金。 Of the total mass%, 0.03 mass% to 0.09 mass% nickel,
Bismuth which is the balance excluding the nickel and inevitable impurities from the whole,
Solder alloy consisting of 前記ニッケルを０．０５質量％〜０．０７質量％含有する、請求項１に記載のはんだ合金。   The solder alloy according to claim 1, wherein the nickel is contained in an amount of 0.05 mass% to 0.07 mass%. 請求項１又は２に記載のはんだ合金の粉末と、
フラックスと、
を有するソルダペースト。 The solder alloy powder according to claim 1 or 2,
With flux,
Solder paste having 請求項１又は２に記載のはんだ合金が一定の形状に成形された成形はんだ。   A molded solder in which the solder alloy according to claim 1 or 2 is molded into a fixed shape. 半導体チップと、
前記半導体チップを支持するダイパッドと、
前記半導体チップと前記ダイパッドとの間に設けられた、請求項１又は２に記載のはんだ合金と、
前記半導体チップ及び前記ダイパッドを覆う樹脂と、
を有する半導体装置。 A semiconductor chip;
A die pad for supporting the semiconductor chip;
The solder alloy according to claim 1 or 2, provided between the semiconductor chip and the die pad;
A resin covering the semiconductor chip and the die pad;
A semiconductor device. 半導体チップと、
前記半導体チップを支持する絶縁基板と、
前記絶縁基板と前記半導体チップとの間に設けられた、請求項１又は２に記載のはんだ合金と、
を有する半導体装置。 A semiconductor chip;
An insulating substrate for supporting the semiconductor chip;
The solder alloy according to claim 1 or 2, provided between the insulating substrate and the semiconductor chip,
A semiconductor device. 半導体チップを支持する絶縁基板と、
前記半導体チップから発生する熱を放出する放熱板と、
前記絶縁基板と前記放熱板との間に設けられた、請求項１又は２に記載のはんだ合金と、
を有する半導体装置。 An insulating substrate that supports the semiconductor chip;
A heat sink that releases heat generated from the semiconductor chip; and
The solder alloy according to claim 1 or 2, provided between the insulating substrate and the heat sink,
A semiconductor device.
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Publication number Priority date Publication date Assignee Title
WO2021153447A1 (en) * 2020-01-30 2021-08-05 ローム株式会社 Semiconductor device
WO2024048887A1 (en) * 2022-09-01 2024-03-07 서울과학기술대학교 산학협력단 Method for manufacturing sinter bonding film, and method for manufacturing power semiconductor package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021153447A1 (en) * 2020-01-30 2021-08-05 ローム株式会社 Semiconductor device
WO2024048887A1 (en) * 2022-09-01 2024-03-07 서울과학기술대학교 산학협력단 Method for manufacturing sinter bonding film, and method for manufacturing power semiconductor package

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