JP2019087692A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2019087692A
JP2019087692A JP2017216534A JP2017216534A JP2019087692A JP 2019087692 A JP2019087692 A JP 2019087692A JP 2017216534 A JP2017216534 A JP 2017216534A JP 2017216534 A JP2017216534 A JP 2017216534A JP 2019087692 A JP2019087692 A JP 2019087692A
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lead frame
sealing resin
resin body
semiconductor device
linear expansion
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JP6922674B2 (en
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加藤　彰
Akira Kato
彰 加藤
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Toyota Motor Corp
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

To provide a semiconductor device which can restrain a junction and can reduce distortion of the junction.SOLUTION: A semiconductor device 1 includes a lead frame 3, a semiconductor element 4 bonded to the lead frame 3 through a junction 21, and a sealing resin body 5 covering the lead frame 3 and the semiconductor element 4. The lead frame 3 is provided with a recess 31, the junction 21 is arranged on a bottom surface 31a of the recess 31, a sealing resin body 5 formed with a filling portion 51 that contains a polymer resin and a filler and fills the recess 31 so as to cover a side face 21a of the junction 21, and the filler is contained in at least the filling portion 51 so that a coefficient of linear expansion of the filling portion 51 is larger than a coefficient of linear expansion of the lead frame 3.SELECTED DRAWING: Figure 1

Description

本発明は、リードフレームと、リードフレームに接合部を介して接合された半導体素子と、リードフレームと半導体素子とを覆う封止樹脂体と、を少なくとも備えた半導体装置に関する。   The present invention relates to a semiconductor device provided with at least a lead frame, a semiconductor element joined to the lead frame via a joint, and a sealing resin body covering the lead frame and the semiconductor element.

この種の技術としては、たとえば、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）等の半導体素子とリードフレームとを接合部を介して接合した接合体を、封止樹脂体で封止した半導体装置が知られている。この半導体装置では、熱伝導性の改善など所望の物性を得るために、封止樹脂体にフィラーを含ませることがある。   As this type of technology, for example, a semiconductor device is known in which a junction body in which a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) and a lead frame are joined via a junction is sealed with a sealing resin body. There is. In this semiconductor device, a filler may be included in the sealing resin body in order to obtain desired physical properties such as improvement in thermal conductivity.

このような半導体装置として、特許文献１には、フィラーを含ませた封止樹脂体で、リードフレームと、リードフレームに接合部を介して接合された半導体素子と、を覆っている半導体装置が開示されている。この半導体装置では、封止樹脂体の線膨張係数を半導体素子、リードフレーム、および接合部の線膨張係数に近づけることで、これらの線膨張係数の差から発生する、封止樹脂体とこれらの部材との応力を低減することができる。   As such a semiconductor device, Patent Document 1 discloses a semiconductor device in which a lead frame and a semiconductor element joined to the lead frame through a junction are covered with a sealing resin body containing a filler. It is disclosed. In this semiconductor device, the sealing resin body generated from the difference between the linear expansion coefficients of the sealing resin body and the semiconductor element, the lead frame, and the joint by making the linear expansion coefficient of the sealing resin body approach those of these Stress with members can be reduced.

特開２００４−１１１４３５号公報Japanese Patent Laid-Open No. 2004-111435

しかしながら、特許文献１に記載の半導体装置では、例えば、繰り返される半導体素子の温度変化に起因して半導体素子とリードフレームとの接合部の一部が封止樹脂体から剥離する場合がある。この場合、接合部と封止樹脂体とが密着していない状態では、接合部の線膨張係数は、半導体素子の線膨張係数より大きいため、半導体素子の高温時に、半導体素子と接合部との間に熱応力が発生する。この結果、接合部には、ひずみが発生し、接合部に割れが入る可能性がある。   However, in the semiconductor device described in Patent Document 1, for example, part of the bonding portion between the semiconductor element and the lead frame may be peeled off from the sealing resin body due to repeated temperature change of the semiconductor element. In this case, in a state where the junction and the sealing resin body are not in close contact with each other, the linear expansion coefficient of the junction is larger than the linear expansion coefficient of the semiconductor element. Thermal stress occurs between them. As a result, distortion occurs in the joint, and the joint may be cracked.

本発明は上記点に鑑みてなされたものであり、本発明では、熱応力により発生する接合部のひずみを低減することができる半導体装置を提供する。   The present invention has been made in view of the above points, and the present invention provides a semiconductor device capable of reducing the strain of a bonding portion generated by thermal stress.

上記課題を解決するために、発明者が、鋭意検討を重ねた結果、半導体素子が高温になった際に、接合部周辺の封止樹脂体を膨張させて、封止樹脂体で接合部の側面を圧縮することにより、接合部と封止樹脂体との密着度合いによらず接合部を拘束して接合部のひずみを低減することができると考えた。   In order to solve the above problems, as a result of intensive investigations by the inventor, when the semiconductor element becomes high temperature, the sealing resin body in the vicinity of the bonding portion is expanded to form the bonding resin portion by the sealing resin body. By compressing the side surface, it was considered that the distortion of the joint can be reduced by constraining the joint regardless of the degree of adhesion between the joint and the sealing resin body.

本発明は、このような考えに基づいてなされたものであり、本発明の半導体装置は、リードフレームと、前記リードフレームに接合部を介して接合された半導体素子と、前記リードフレームと前記半導体素子とを覆う封止樹脂体と、を備えたものである。前記リードフレームには、凹部が設けられ、前記凹部の底面上には、前記接合部が配置され、前記封止樹脂体は、高分子樹脂およびフィラーを含み、かつ、前記接合部の側面を覆うように前記凹部に充填されている充填部分を形成しており、少なくとも前記充填部分には、前記充填部分の線膨張係数が前記リードフレームの線膨張係数より大きくなるように、前記フィラーが含まれていることを特徴とする。   The present invention has been made based on such a concept, and the semiconductor device of the present invention comprises a lead frame, a semiconductor element joined to the lead frame via a junction, the lead frame, and the semiconductor And a sealing resin body covering the element. The lead frame is provided with a recess, the bonding portion is disposed on the bottom surface of the recess, the sealing resin body includes a polymer resin and a filler, and covers the side surface of the bonding portion. And the filler is included so that the linear expansion coefficient of the filling portion is larger than the linear expansion coefficient of the lead frame. It is characterized by

本発明によれば、接合部は、リードフレームの凹部の底面上に配置されている。接合部の側面は、高分子樹脂およびフィラーを含む封止樹脂体の充填部分により覆われている。充填部分には、充填部分の線膨張係数がリードフレームの線膨張係数より大きくなるように、フィラーが含まれている。これにより、半導体素子の高温時に、その熱が周辺の封止樹脂体に伝導した場合、凹部内で充填部分が膨張しようとするため、接合部の側面は充填部分により圧縮される。この結果、接合部が充填部分により拘束され、接合部のひずみを抑制することができる。凹部の開口部から底面までの深さは、接合部の厚み以上であることが望ましい。   According to the invention, the joint is arranged on the bottom of the recess of the lead frame. The side surface of the joint is covered by the filling portion of the sealing resin body containing the polymer resin and the filler. The filling portion contains a filler such that the linear expansion coefficient of the filling portion is larger than the linear expansion coefficient of the lead frame. As a result, when the heat is conducted to the surrounding sealing resin body at high temperature of the semiconductor element, the filling portion tends to expand in the recess, and the side surface of the bonding portion is compressed by the filling portion. As a result, the joint portion is restrained by the filling portion, and distortion of the joint portion can be suppressed. The depth from the opening to the bottom of the recess is preferably equal to or greater than the thickness of the joint.

ここで、本明細書において「リードフレーム」とは、文字通りのリードフレームのほか、ダイパッド、回路基板や応力緩和基板等の基板、純Ａｌからなる基板とＡｌＮ（窒化アルミニウム）からなる基板を積層してなるＤＢＡ（絶縁基板）、ヒートシンクなども包含されるものである。   Here, in the present specification, “lead frame” refers to a die pad, a circuit board, a substrate such as a stress relaxation substrate, a substrate made of pure Al, and a substrate made of AlN (aluminum nitride) in addition to a literally lead frame. Also included are DBA (insulating substrate), a heat sink, and the like.

（ａ）は、第１実施形態に係る半導体装置の模式的断面図であり、（ｂ）は、（ａ）の半導体装置に係る半導体素子とリードフレームとを接合する接合部近傍の模式的な拡大断面図である。(A) is a typical sectional view of a semiconductor device concerning a 1st embodiment, (b) is a typical figure near the joined part which joins a semiconductor device and a lead frame concerning a semiconductor device of (a) It is an expanded sectional view. 第１実施形態の変形例に係る半導体素子とリードフレームとを接合する接合部近傍の模式的な拡大断面図である。It is a typical expanded sectional view near the joined part which joins a semiconductor device and a lead frame concerning a modification of a 1st embodiment. 第２実施形態に係る半導体素子とリードフレームとを接合する接合部近傍の模式的な拡大断面図である。It is a typical expanded sectional view near the joined part which joins a semiconductor device and a lead frame concerning a 2nd embodiment. 第２実施形態の変形例に係る半導体素子とリードフレームとを接合する接合部近傍の模式的な拡大断面図である。It is a typical expanded sectional view near the joined part which joins a semiconductor device and a lead frame concerning a modification of a 2nd embodiment. （ａ）は、従来の半導体装置の模式的断面図であり、（ｂ）は、剥離部が形成された（ａ）の半導体装置に係る半導体素子とリードフレームとを接合する接合部近傍の模式的な拡大断面構造図である。(A) is a schematic cross-sectional view of a conventional semiconductor device, and (b) is a schematic view in the vicinity of a bonding portion connecting a semiconductor element and a lead frame according to the semiconductor device of (a) in which a peeling portion is formed. It is an enlarged sectional structural view.

以下に、図１〜４を参照して、本発明の２つの実施形態とこれらの変形例について説明する。   Hereinafter, two embodiments of the present invention and their modifications will be described with reference to FIGS.

＜第１実施形態＞
図１（ａ）は、第１実施形態に係る半導体装置１の模式的断面図であり、図１（ｂ）は、図１（ａ）の半導体装置１に係る半導体素子４とリードフレーム３とを接合する接合部２１近傍の模式的な拡大断面図である。 First Embodiment
FIG. 1A is a schematic cross-sectional view of the semiconductor device 1 according to the first embodiment, and FIG. 1B is a semiconductor element 4 and a lead frame 3 according to the semiconductor device 1 of FIG. It is a typical expanded sectional view near the joined part 21 which joins two.

本実施形態に係る半導体装置１は、両面冷却型半導体装置として利用されるものである。図１（ａ）に示す形態では、半導体装置１は、半導体素子４のコレクタ側に配置された１つのリードフレーム３とエミッタ側に配置された１つのリードフレーム７との間に、半導体素子４を備えた積層部１１が２つ並列に配置されている。２つの積層部１１は同じ構造を有しているため、以下に、１つの積層部１１とリードフレーム３、７とを参照して、本実施形態の半導体装置１の部材について説明をする。   The semiconductor device 1 according to the present embodiment is used as a double-sided cooling type semiconductor device. In the mode shown in FIG. 1A, the semiconductor device 1 includes the semiconductor element 4 between the one lead frame 3 disposed on the collector side of the semiconductor element 4 and the one lead frame 7 disposed on the emitter side. The two stacked units 11 each having the same number are arranged in parallel. Since the two stacked parts 11 have the same structure, the members of the semiconductor device 1 of the present embodiment will be described below with reference to one stacked part 11 and the lead frames 3 and 7.

本実施形態の半導体装置１は、リードフレーム３と、リードフレーム３に接合部２１を介して接合された半導体素子４と、リードフレーム３および半導体素子４を覆う封止樹脂体５と、を少なくとも備えている。   The semiconductor device 1 of the present embodiment includes at least a lead frame 3, a semiconductor element 4 joined to the lead frame 3 via a bonding portion 21, and a sealing resin body 5 covering the lead frame 3 and the semiconductor element 4. Have.

さらに、本実施形態の半導体装置１では、スペーサーとなるブロック６およびリードフレーム７を備えている。半導体素子４には、ブロック６と、リードフレーム７とが順に配置されており、半導体素子４とブロック６とは、接合部２２を介して接合され、ブロック６とリードフレーム７とは、接合部２３を介して接合されている。封止樹脂体５は、封止樹脂体５との密着性を高めるプライマ層（不図示）を介して、積層部１１（半導体素子４、ブロック６、および接合部２１〜２３）の表面およびリードフレーム３，７の対向する表面を覆っている。   Furthermore, in the semiconductor device 1 of the present embodiment, the block 6 serving as a spacer and the lead frame 7 are provided. In the semiconductor element 4, the block 6 and the lead frame 7 are arranged in order, the semiconductor element 4 and the block 6 are joined via the joint portion 22, and the block 6 and the lead frame 7 are jointed It is joined via 23. The sealing resin body 5 has a surface and leads of the laminated portion 11 (the semiconductor element 4, the block 6, and the bonding portions 21 to 23) via a primer layer (not shown) for enhancing adhesion with the sealing resin body 5. It covers the opposite surfaces of frames 3 and 7.

リードフレーム３，７は、Ａｌやその合金、Ｃｕやその合金などからなってもよいが、これらを基材として、リードフレーム３，７の表面に、Ｎｉめっき層が形成され、Ｎｉめっき層の表面にＡｕめっき層が形成されていてもよい。   The lead frames 3 and 7 may be made of Al or an alloy thereof, Cu or an alloy thereof, or the like. A Ni plating layer is formed on the surface of the lead frames 3 and 7 using these as a base material. An Au plating layer may be formed on the surface.

半導体素子４としては、Ｓｉ素子が挙げることができる。接合部２１は、Ｐｂ系はんだ、Ｐｂフリーはんだのいずれであってもよいが、Ｐｂフリーはんだであることが好ましい。このようなＰｂフリーはんだとしては、Ｓｎ−Ａｇ系はんだ、Ｓｎ−Ｃｕ系はんだ、Ｓｎ−Ａｇ−Ｃｕ系はんだ、Ｓｎ−Ｚｎ系はんだ、Ｓｎ−Ｓｂ系はんだなどを挙げることができる。同様に、接合部２２，２３は、接合部２１と同様の材料を使用してよい。なお、ブロック６は、半導体装置１の高さを調整するものであり、材料としては、例えば、Ｃｕなどを挙げることができる。   An example of the semiconductor element 4 is a Si element. The bonding portion 21 may be either Pb-based solder or Pb-free solder, but is preferably Pb-free solder. Examples of such Pb-free solder include Sn-Ag based solder, Sn-Cu based solder, Sn-Ag-Cu based solder, Sn-Zn based solder, and Sn-Sb based solder. Similarly, the joints 22 and 23 may use the same material as the joint 21. The block 6 is for adjusting the height of the semiconductor device 1, and examples of the material include Cu and the like.

封止樹脂体５は、高分子樹脂およびフィラーを含む。高分子樹脂は封止樹脂体５の基材となるものであり、高分子樹脂として、エポキシ系熱硬化性樹脂を用いることができる。フィラーは、封止樹脂体５に所望の物性を付与するものであり、フィラーとして、シリカ、アルミナ、および酸化マグネシウムなどの破砕状または球状のフィラーの少なくとも１種類以上を用いることができる。   The sealing resin body 5 contains a polymer resin and a filler. The polymer resin is to be a base material of the sealing resin body 5, and an epoxy thermosetting resin can be used as the polymer resin. The filler imparts desired physical properties to the sealing resin body 5, and as the filler, at least one or more kinds of crushed or spherical fillers such as silica, alumina, and magnesium oxide can be used.

なお、プライマ層（不図示）の材料としては、たとえば、ポリアミド樹脂、ポリアミドイミド樹脂、およびウレタン樹脂などを挙げることができる。   In addition, as a material of a primer layer (not shown), a polyamide resin, a polyamide imide resin, a urethane resin etc. can be mentioned, for example.

本実施形態では、従来とは異なり、図１（ｂ）に示すように、リードフレーム３には、凹部３１が設けられている。凹部３１は、底面３１ａと、開口部３１ｂと、側面３１ｃとで形成される空間である。凹部３１の底面３１ａ上には、接合部２１が配置され、凹部３１の開口部３１ｂから底面３１ａまでの深さＤは、接合部２１の厚みＨ以上である。これにより、凹部３１は、凹部３１の側面３１ｃで接合部２１の側面２１ａを囲むようにして、接合部２１を凹部３１に収めることができる。   In the present embodiment, unlike the prior art, as shown in FIG. 1B, the lead frame 3 is provided with a recess 31. The recess 31 is a space formed by the bottom surface 31 a, the opening 31 b, and the side surface 31 c. The bonding portion 21 is disposed on the bottom surface 31 a of the recess 31, and the depth D from the opening 31 b of the recess 31 to the bottom surface 31 a is equal to or greater than the thickness H of the bonding portion 21. As a result, the recessed portion 31 can store the bonding portion 21 in the recessed portion 31 such that the side surface 31 c of the recessed portion 31 surrounds the side surface 21 a of the bonding portion 21.

また、封止樹脂体５は、接合部２１の側面２１ａを覆うように凹部３１に充填されている充填部分５１を形成している。さらに、少なくとも充填部分５１には、充填部分５１の線膨張係数がリードフレーム３の線膨張係数より大きくなるように、フィラーが含まれている。これにより、半導体素子４が高温に発熱した場合、充填部分５１の熱膨張量が、リードフレーム３のものより大きくなる。   Further, the sealing resin body 5 forms a filling portion 51 which is filled in the recess 31 so as to cover the side surface 21 a of the bonding portion 21. Furthermore, at least the filling portion 51 contains a filler such that the linear expansion coefficient of the filling portion 51 is larger than the linear expansion coefficient of the lead frame 3. Thereby, when the semiconductor element 4 generates heat at high temperature, the thermal expansion amount of the filling portion 51 becomes larger than that of the lead frame 3.

ここで、本明細書では、充填部分５１の線膨張係数とは、高分子樹脂とフィラーとを含む充填部分５１の見かけの線膨張係数をいう。また、リードフレーム３の線膨張係数とは、リードフレーム３を構成する基材の線膨張係数をいう。   Here, in the present specification, the linear expansion coefficient of the filling portion 51 refers to the apparent linear expansion coefficient of the filling portion 51 including the polymer resin and the filler. Further, the linear expansion coefficient of the lead frame 3 refers to the linear expansion coefficient of the base material constituting the lead frame 3.

例えば、リードフレーム３が銅（線膨張係数１６〜１８ｐｐｍ／Ｋ）で構成されている場合、充填部分５１の線膨張係数は、線膨張係数２８〜３７ｐｐｍ／Ｋの範囲にあることが好ましい。このような充填部分５１の線膨張係数の範囲は、封止樹脂体５に添加するフィラーの種類および含有量を調整することにより、決定することができる。なお、本実施形態では、後述する第２実施形態とは異なり、充填部分５１を含む封止樹脂体５に含まれるフィラーの種類および含有量は同じである。   For example, when the lead frame 3 is made of copper (linear expansion coefficient 16 to 18 ppm / K), the linear expansion coefficient of the filling portion 51 is preferably in the range of 28 to 37 ppm / K. The range of the linear expansion coefficient of the filling portion 51 can be determined by adjusting the type and content of the filler added to the sealing resin body 5. In the present embodiment, unlike the second embodiment described later, the kind and content of the filler contained in the sealing resin body 5 including the filling portion 51 are the same.

ここで、図５（ａ）および（ｂ）を参照して、従来の半導体装置１について説明する。図５（ａ）は、従来の半導体装置１の模式的断面図であり、図５（ｂ）は、剥離部８が形成された（ａ）の半導体装置１に係る半導体素子４とリードフレーム３とを接合する接合部２１近傍の模式的な拡大断面図である。なお、本実施形態と同じ部材および部分に関しては、同じ符号を付してその詳細な説明は省略する。   Here, a conventional semiconductor device 1 will be described with reference to FIGS. 5 (a) and 5 (b). FIG. 5A is a schematic cross-sectional view of the conventional semiconductor device 1, and FIG. 5B is a semiconductor element 4 and a lead frame 3 according to the semiconductor device 1 of FIG. 5A in which the peeling portion 8 is formed. And a schematic enlarged cross-sectional view in the vicinity of the joint portion 21 joining the two. The same members and parts as those of the present embodiment are designated by the same reference numerals and their detailed description will be omitted.

従来では、図５（ａ）に示すように、半導体装置１は、本実施形態とは異なり、平板状のリードフレーム３に接合部２１が配置されている。また、半導体素子４、リードフレーム３、および、接合部２１と、封止樹脂体５との応力を低減するように、封止樹脂体５は、封止樹脂体５の線膨張係数が、半導体素子４、リードフレーム３、および接合部２１の線膨張係数に近づくようにフィラーを含んでいる。なお、半導体素子４の線膨張係数は、リードフレーム３よりも小さいため、封止樹脂体５の線膨張係数を、これらの部材の線膨張係数に近づけた場合、フィラーを含む封止樹脂体５の線膨張係数は、リードフレーム３の線膨張係数よりも、小さくなる傾向なる。   Conventionally, as shown in FIG. 5A, in the semiconductor device 1, unlike the present embodiment, the joint portion 21 is disposed on the flat lead frame 3. Further, the sealing resin body 5 has a coefficient of linear expansion coefficient of the sealing resin body 5 so as to reduce the stress between the semiconductor element 4, the lead frame 3, the bonding portion 21 and the sealing resin body 5. A filler is included so as to approach the linear expansion coefficients of the element 4, the lead frame 3, and the joint 21. Since the linear expansion coefficient of the semiconductor element 4 is smaller than that of the lead frame 3, the sealing resin body 5 containing a filler when the linear expansion coefficient of the sealing resin body 5 is made close to the linear expansion coefficient of these members. Of the linear expansion coefficient of the lead frame 3 tends to be smaller than that of the lead frame 3.

このような従来の半導体装置１では、例えば、半導体素子４の繰り返される温度変化により、図５（ｂ）に示すように、接合部２１の一部が封止樹脂体５から剥離した剥離部８が形成される場合がある。一般的に、半導体素子４の線膨張係数（数ｐｐｍ／Ｋ）より接合部２１の線膨張係数（２０ｐｐｍ／Ｋ以上）のほうが大きい。そのため、剥離部８が形成した状態など、封止樹脂体５と接合部２１とが良好に密着していない状態では、半導体素子４が発熱により高温になると、接合部２１が半導体素子４に対して膨張しようとする。この結果、接合部２１のひずみが大きくなり、半導体装置１の信頼性が低下する。   In such a conventional semiconductor device 1, for example, due to repeated temperature change of the semiconductor element 4, as shown in FIG. 5B, the peeling portion 8 in which a part of the bonding portion 21 is peeled from the sealing resin body 5 May be formed. Generally, the linear expansion coefficient (20 ppm / K or more) of the junction 21 is larger than the linear expansion coefficient (several ppm / K) of the semiconductor element 4. Therefore, in a state where the sealing resin body 5 and the bonding portion 21 are not in close contact with each other, such as in a state in which the peeling portion 8 is formed, the bonding portion 21 is against the semiconductor element 4 when the semiconductor element 4 is heated to a high temperature. Try to expand. As a result, distortion of the bonding portion 21 is increased, and the reliability of the semiconductor device 1 is reduced.

一方、図１（ｂ）に示すように、本実施形態によれば、凹部３１内に収まるように配置された接合部２１の側面２１ａが、封止樹脂体５のうち凹部３１内に充填された充填部分５１により覆われている。充填部分５１には、充填部分５１の線膨張係数がリードフレーム３の線膨張係数より大きくなるように、フィラーが含まれている。   On the other hand, as shown in FIG. 1 (b), according to the present embodiment, the side surface 21 a of the bonding portion 21 arranged to be contained in the recess 31 is filled in the recess 31 of the sealing resin body 5. It is covered by the filling portion 51. The filling portion 51 contains a filler such that the linear expansion coefficient of the filling portion 51 is larger than the linear expansion coefficient of the lead frame 3.

これにより、半導体素子４の高温時に、その発熱した熱が周辺の封止樹脂体５に伝導すると、凹部３１の容積よりも充填部分５１が大きく膨張しようとするため、接合部２１の側面２１ａには圧縮応力が加わる（図１（ｂ）矢印Ｐを参照）。この結果、封止樹脂体５と接合部２１とが良好な密着性を確保することができない場合であっても、半導体素子４の発熱時に、接合部２１は充填部分５１により拘束されるため、接合部２１のひずみを抑制することができる。   Thereby, when the heat generated by the semiconductor element 4 is conducted to the surrounding sealing resin body 5 when the semiconductor element 4 is at a high temperature, the filling portion 51 tends to expand more than the volume of the recess 31. Is subjected to compressive stress (see arrow P in FIG. 1 (b)). As a result, even when the sealing resin body 5 and the bonding portion 21 can not ensure good adhesion, the bonding portion 21 is restrained by the filling portion 51 when the semiconductor element 4 generates heat, The distortion of the joint portion 21 can be suppressed.

次に、本実施形態の半導体装置１の製造方法の概略を以下に説明する。
まず、凹部３１の形成工程を行う。この工程では、リードフレーム３を準備し、リードフレーム３の半導体素子４を搭載する面に、所定の大きさの開口部３１ｂを有し、かつリードフレーム３の厚さ方向に深さＤを有するように、凹部３１を２個並列して形成する。このような凹部３１，３１は、機械加工で形成することができる。 Next, an outline of a method of manufacturing the semiconductor device 1 of the present embodiment will be described below.
First, the step of forming the recess 31 is performed. In this step, the lead frame 3 is prepared, and an opening 31 b of a predetermined size is provided on the surface of the lead frame 3 on which the semiconductor element 4 is mounted, and the depth D is in the thickness direction of the lead frame 3. Thus, two recesses 31 are formed in parallel. Such recesses 31, 31 can be formed by machining.

上述した形成工程の次に、接合工程を行う。この工程では、凹部３１，３１の底面３１ａ，３１ａ上に接合部２１，２１を介して半導体素子４，４を接合する。この接合では、各半導体素子４が各凹部３１内に収まるように、各接合部２１の厚みＨを各凹部３１の深さＤ以下にする。次いで、半導体素子４，４の上に接合部２２，２２を介してブロック６，６を搭載した後、ブロック６，６の上に１つのリードフレーム７を、接合部２３，２３を介して接合する。これにより、リードフレーム３とリードフレーム７との間に二つの積層部１１が形成される。   Next to the above-described formation process, a bonding process is performed. In this process, the semiconductor elements 4 and 4 are bonded to the bottom surfaces 31 a of the concave portions 31 and 31 via the bonding portions 21 and 21. In this bonding, the thickness H of each bonding portion 21 is made equal to or less than the depth D of each recess 31 so that each semiconductor element 4 is contained in each recess 31. Next, after mounting the blocks 6 and 6 on the semiconductor elements 4 and 4 via the bonding portions 22 and 22, one lead frame 7 is bonded on the blocks 6 and 6 via the bonding portions 23 and 23. Do. Thus, two stacked portions 11 are formed between the lead frame 3 and the lead frame 7.

このような接合工程の後に、プライマ層（不図示）を形成する工程を行う。この工程では、リードフレーム３，７、各接合部２１〜２３、各半導体素子４、各ブロック６の表面に、例えばスピンコートにより溶液状のプライマを塗布して、乾燥させて、プライマ層を形成する。   After such a bonding step, a step of forming a primer layer (not shown) is performed. In this step, a primer in the form of a solution is applied by spin coating, for example, on the surfaces of the lead frames 3 and 7, the junctions 21 to 23, the semiconductor elements 4 and the blocks 6, and dried to form a primer layer. Do.

次に、封止工程を行う。この工程では、リードフレーム３と半導体素子４とを覆うように封止樹脂体５を成形する。具体的には、封止樹脂体５の線膨張係数がリードフレーム３の線膨張係数より大きくなるように、エポキシ樹脂など高分子樹脂およびフィラーを含む組成物を予め調製しておく。次いで、プライマ層（不図示）を介して、リードフレーム３，７、各接合部２１〜２３、各半導体素子４、各ブロック６の表面を覆うように、調製した組成物をポッティングし、これを硬化させる。   Next, a sealing process is performed. In this step, the sealing resin body 5 is molded so as to cover the lead frame 3 and the semiconductor element 4. Specifically, a composition containing a polymer resin such as an epoxy resin and a filler is prepared in advance so that the linear expansion coefficient of the sealing resin body 5 is larger than the linear expansion coefficient of the lead frame 3. Next, the prepared composition is potted so as to cover the surfaces of the lead frames 3 and 7, the junctions 21 to 23, the semiconductor elements 4 and the blocks 6 through the primer layer (not shown), and Cure.

これにより、プライマ層（不図示）を介して、リードフレーム３，７、各接合部２１〜２３、各半導体素子４、各ブロック６の表面を覆うように封止樹脂体５が成形される。ここで、本実施形態では、接合部２１が凹部３１内に配置されているため、接合部２１の側面２１ａを覆うように凹部３１の側面３１ｃと接合部２１の側面２１ａとの間に充填された封止樹脂体５の充填部分５１が成形される。   Thus, the sealing resin body 5 is formed to cover the surfaces of the lead frames 3 and 7, the bonding portions 21 to 23, the semiconductor elements 4, and the blocks 6 via the primer layer (not shown). Here, in the present embodiment, since the bonding portion 21 is disposed in the recess 31, the bonding portion 21 is filled between the side surface 31 c of the recess 31 and the side surface 21 a of the bonding portion 21 so as to cover the side surface 21 a of the bonding portion 21. The filled portion 51 of the sealing resin body 5 is formed.

最後に、外装処理工程を行う。この工程では、封止樹脂体５が成形された半導体装置１に対して、切削などの外装処理を施し、所定の形状にする。これにより、図１（ａ）および（ｂ）に示す本実施形態の半導体装置１を取得することができる。   Finally, an exterior treatment process is performed. In this step, the semiconductor device 1 in which the sealing resin body 5 is formed is subjected to an exterior treatment such as cutting to form a predetermined shape. Thereby, the semiconductor device 1 of the present embodiment shown in FIGS. 1A and 1B can be obtained.

＜第１実施形態の変形例＞
図２は、第１実施形態の変形例に係る半導体素子４とリードフレーム３とを接合する接合部２１近傍の模式的な拡大断面図である。図２に示すように、本変形例では、半導体装置１のリードフレーム３の構造が上述した実施形態のものとは異なる。よって、以下に相違点について主に説明し、上述した実施形態と同じ部材および部分に関しては、同じ符号を付してその詳細な説明は省略する。 Modification of First Embodiment
FIG. 2 is a schematic enlarged cross-sectional view in the vicinity of a bonding portion 21 bonding the semiconductor element 4 and the lead frame 3 according to a modification of the first embodiment. As shown in FIG. 2, in the present modification, the structure of the lead frame 3 of the semiconductor device 1 is different from that of the embodiment described above. Therefore, the differences will be mainly described below, and the same members and parts as those of the above-described embodiment are denoted by the same reference numerals, and the detailed description thereof will be omitted.

本変形例では、リードフレーム３は、リードフレーム本体３３とリードフレーム本体３３上に接合部２１の側面２１ａを囲むように配置された枠部３２とで構成されている。ここでは、凹部３１は、リードフレーム本体３３の上面と枠部３２の内側壁面とで形成され、枠部３２の高さが凹部３１の開口部３１ｂから底面３１ａまでの深さＤに相当する。   In the present modification, the lead frame 3 is configured of a lead frame main body 33 and a frame portion 32 disposed on the lead frame main body 33 so as to surround the side surface 21 a of the joint portion 21. Here, the recess 31 is formed by the upper surface of the lead frame main body 33 and the inner wall surface of the frame 32, and the height of the frame 32 corresponds to the depth D from the opening 31b of the recess 31 to the bottom 31a.

本変形例の半導体装置１の製造方法では、上述した製造方法の凹部３１を形成する工程において、リードフレーム本体３３上の所定の位置に枠部３２を二個並列して凹部３１を形成する。このような枠部３２，３２は、機械加工で形成することができる。この点以外は上述した製造方法と同様にして本変形例の半導体装置１を製造することができる。   In the method of manufacturing the semiconductor device 1 of this modification, in the step of forming the recess 31 of the above-described manufacturing method, two recesses 32 are formed in parallel at predetermined positions on the lead frame main body 33. Such frame parts 32 and 32 can be formed by machining. The semiconductor device 1 of the present modification can be manufactured in the same manner as the manufacturing method described above except this point.

このように、構成された半導体装置１であっても、上述した第１実施形態に係る半導体装置１と同様の効果を奏することは勿論のことである。   Of course, even with the semiconductor device 1 configured as described above, the same effects as the semiconductor device 1 according to the above-described first embodiment can be obtained.

＜第２実施形態＞
図３は、第２実施形態に係る半導体素子４とリードフレーム３とを接合する接合部２１近傍の模式的な拡大断面図である。第２実施形態に係る半導体装置１が第１実施形態のものと相違する点は、充填部分５１のみに、充填部分５１の線膨張係数をリードフレーム３の線膨張係数より大きくなるようにフィラーが含まれている点である。よって、以下に相違点を主に説明し、その他の詳細な説明は省略する。 Second Embodiment
FIG. 3 is a schematic enlarged cross-sectional view in the vicinity of a bonding portion 21 bonding the semiconductor element 4 and the lead frame 3 according to the second embodiment. The semiconductor device 1 according to the second embodiment is different from that of the first embodiment in that the filler is provided only in the filling portion 51 so that the linear expansion coefficient of the filling portion 51 is larger than the linear expansion coefficient of the lead frame 3. It is an included point. Therefore, the differences will be mainly described below, and the other detailed description will be omitted.

図３に示すように、第２実施形態では、封止樹脂体５は、充填部分（第１封止樹脂体）５１と、充填部分５１以外の部分（第２封止樹脂体）５２と、で構成されている。第１封止樹脂体５１のみに、第１封止樹脂体５１の線膨張係数をリードフレーム３の線膨張係数より大きくなるようにフィラーが含まれている。   As shown in FIG. 3, in the second embodiment, the sealing resin body 5 includes a filling portion (first sealing resin body) 51 and a portion (second sealing resin body) 52 other than the filling portion 51. It consists of The filler is included only in the first sealing resin body 51 so that the linear expansion coefficient of the first sealing resin body 51 is larger than the linear expansion coefficient of the lead frame 3.

なお、第２封止樹脂体５２は、フィラーを含まない、または、第２封止樹脂体５２には、第１封止樹脂体５１の線膨張係数をリードフレーム３の線膨張係数以下となるように、フィラーが含まれていてもよい。たとえば、第２封止樹脂体５２には、第１封止樹脂体５１とは異なる物性を発揮するようにフィラーが含まれていてもよい。異なる物性としては、封止樹脂体５全体の反りの抑制や封止樹脂体５の強度の向上などが挙げることができる。たとえば、第１封止樹脂体５１と第２封止樹脂体５２とに含有するフィラーは同じ材料および同じ材料からなるフィラーであり、第２封止樹脂体５２のフィラーの含有率を、第１封止樹脂体５１のフィラーの含有率よりも高くしてもよい。   The second sealing resin body 52 does not contain a filler, or, in the second sealing resin body 52, the linear expansion coefficient of the first sealing resin body 51 is equal to or less than the linear expansion coefficient of the lead frame 3. As such, a filler may be included. For example, the second sealing resin body 52 may contain a filler so as to exert physical properties different from those of the first sealing resin body 51. As a physical property which differs, suppression of the curvature of the sealing resin body 5 whole, improvement of the intensity | strength of the sealing resin body 5, etc. can be mentioned. For example, the filler contained in the first sealing resin body 51 and the second sealing resin body 52 is a filler made of the same material and the same material, and the content of the filler of the second sealing resin body 52 is It may be higher than the filler content of the sealing resin body 51.

第２実施形態の半導体装置１の製造方法では、第１実施形態に係る製造方法の封止工程において、第１封止樹脂体５１に相当する樹脂を各凹部３１内にポッティングした後、これを硬化させて、各第１封止樹脂体５１を成形する。   In the method of manufacturing the semiconductor device 1 of the second embodiment, after potting a resin corresponding to the first sealing resin body 51 in each recess 31 in the sealing step of the manufacturing method according to the first embodiment, this is performed. After curing, each first sealing resin body 51 is molded.

次いで、成型した各第１封止樹脂体５１と、プライマ層が形成されたリードフレーム３，７、各接合部２２，２３、各半導体素子４、および各ブロック６との表面を覆うように第２封止樹脂体５２に相当する樹脂をポッティングし、これを硬化させる。これにより、第２封止樹脂体５２が成形される。このような第１封止樹脂体５１および第２封止樹脂体５２の形成以外は、上述した第１実施形態の半導体装置１の製造方法と同様である。   Next, the surfaces of the molded first sealing resin body 51, the lead frames 3 and 7 on which the primer layer is formed, the bonding portions 22 and 23, the semiconductor elements 4 and the blocks 6 are covered. (2) Potting a resin corresponding to the sealing resin body 52 and curing it. Thereby, the second sealing resin body 52 is formed. Except for the formation of the first sealing resin body 51 and the second sealing resin body 52, the method is the same as the method of manufacturing the semiconductor device 1 of the first embodiment described above.

本実施形態によれば、特性の異なる２種類の第１および第２封止樹脂体５１，５２を備えることにより、第１封止樹脂体５１で、第１実施形態の如く、接合部２１を拘束してひずみを防止する効果を発揮しながら、さらに、第２封止樹脂体５２で、ひずみ防止効果とは異なる所望の効果を発揮することができる。   According to the present embodiment, by providing the two types of first and second sealing resin bodies 51 and 52 having different characteristics, the bonding portion 21 is formed by the first sealing resin body 51 as in the first embodiment. The second sealing resin body 52 can further exhibit a desired effect different from the strain preventing effect while exhibiting the effect of constraining and preventing the strain.

＜第２実施形態の変形例＞
図４は、第２実施形態の変形例に係る半導体素子４とリードフレーム３とを接合する接合部２１近傍の模式的な拡大断面構造を説明する図である。本変形例では、リードフレーム３が上述した第１実施形態の変形例と同様の構成を有する点が、第２実施形態のものとは異なる。よって、以下に第２実施形態との相違点を主に説明し、その他の詳細な説明は省略する。 Modification of Second Embodiment
FIG. 4 is a view for explaining a schematic enlarged cross-sectional structure in the vicinity of a bonding portion 21 for bonding the semiconductor element 4 and the lead frame 3 according to a modification of the second embodiment. The present modification is different from the second embodiment in that the lead frame 3 has the same configuration as that of the modification of the first embodiment described above. Therefore, differences with the second embodiment will be mainly described below, and the other detailed description will be omitted.

図４に示す本変形例では、第１実施形態の変形例の如く、リードフレーム３は、リードフレーム本体３３と枠部３２とで構成されている。凹部３１は、リードフレーム本体３３の上面と枠部３２の内側壁面とで形成され、枠部３２の高さが凹部３１の開口部３１ｂから底面３１ａまでの深さＤに対応する。   In the present modification shown in FIG. 4, as in the modification of the first embodiment, the lead frame 3 is composed of the lead frame main body 33 and the frame portion 32. The recess 31 is formed by the upper surface of the lead frame main body 33 and the inner wall surface of the frame 32, and the height of the frame 32 corresponds to the depth D from the opening 31 b of the recess 31 to the bottom 31 a.

本変形例の半導体装置１の製造方法では、上述した第１実施形態の変形例に係る製造方法の如く、第１実施形態の製造方法に係る凹部３１の形成工程において、リードフレーム本体３３上の所定の位置に枠部３２を二個並列して凹部３１，３１を形成する。このような枠部３２，３２は、機械加工で形成することができる。この点以外は上述の第２実施形態の製造方法と同様にして、本変形例の半導体装置１を製造することができる。このような構成を有する本変形例であっても、第２実施形態と同様の効果を奏することは勿論のことである。   In the method of manufacturing the semiconductor device 1 of the present modification, as in the manufacturing method according to the modification of the first embodiment described above, in the step of forming the recess 31 according to the manufacturing method of the first embodiment, Two frame portions 32 are juxtaposed at predetermined positions to form concave portions 31 and 31. Such frame parts 32 and 32 can be formed by machining. The semiconductor device 1 of this modification can be manufactured in the same manner as the manufacturing method of the second embodiment described above except this point. It is a matter of course that the same effect as that of the second embodiment can be obtained even with this modification having such a configuration.

以上、本発明の一実施形態について詳述したが、本発明は、前記の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の精神を逸脱しない範囲で、種々の設計変更を行うことができるものである。   As mentioned above, although one embodiment of the present invention was explained in full detail, the present invention is not limited to the above-mentioned embodiment, It is a range which does not deviate from the spirit of the present invention indicated in a claim. It is possible to make design changes.

たとえば、上述した実施形態およびこれらの変形例ではリードフレーム３に充填部分５１が充填された凹部３１設けたが、リードフレーム７に上述した実施形態およびこれらの変形例の如く、充填部分５１が充填された凹部３１を設けてもよい。   For example, although the recess 31 in which the filling portion 51 is filled is provided in the lead frame 3 in the embodiment and the modifications described above, the filling portion 51 is filled in the lead frame 7 as in the embodiment and the modifications thereof. The recessed portion 31 may be provided.

１：半導体装置、３：リードフレーム、２１：接合部、２１ａ：接合部の側面、４：半導体素子、５：封止樹脂体、３１：凹部、３１ａ：底面、３１ｂ：開口部、５１：充填部分、Ｄ：開口部から底面までの深さ、Ｈ：接合部の厚み   1: Semiconductor device, 3: Lead frame, 21: junction, 21a: side of junction, 4: semiconductor element, 5: sealing resin body, 31: recess, 31a: bottom, 31b: opening, 51: filling Part, D: Depth from opening to bottom, H: Thickness of joint

Claims (1)

リードフレームと、前記リードフレームに接合部を介して接合された半導体素子と、前記リードフレームと前記半導体素子とを覆う封止樹脂体と、を備えた半導体装置であって、
前記リードフレームには、凹部が設けられ、
前記凹部の底面上には、前記接合部が配置され、
前記封止樹脂体は、高分子樹脂およびフィラーを含み、かつ、前記接合部の側面を覆うように前記凹部に充填されている充填部分を形成しており、
少なくとも前記充填部分には、前記充填部分の線膨張係数が前記リードフレームの線膨張係数より大きくなるように、前記フィラーが含まれていることを特徴とする半導体装置。 A semiconductor device comprising: a lead frame; a semiconductor element joined to the lead frame via a joint; and a sealing resin body covering the lead frame and the semiconductor element,
The lead frame is provided with a recess,
The joint is disposed on the bottom of the recess,
The sealing resin body includes a polymer resin and a filler, and forms a filling portion filled in the recess so as to cover the side surface of the bonding portion.
The semiconductor device according to claim 1, wherein the filler is contained in at least the filling portion such that a linear expansion coefficient of the filling portion is larger than a linear expansion coefficient of the lead frame.
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JP2012079962A (en) * 2010-10-04 2012-04-19 Mitsubishi Electric Corp Semiconductor device and method of manufacturing semiconductor device
JP2014232811A (en) * 2013-05-29 2014-12-11 ルネサスエレクトロニクス株式会社 Semiconductor device and method for manufacturing the same
JP2016149448A (en) * 2015-02-12 2016-08-18 株式会社豊田中央研究所 Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0987522A (en) * 1995-09-19 1997-03-31 Sanken Electric Co Ltd Semiconductor sealing material
JP2002261187A (en) * 2000-12-28 2002-09-13 Hitachi Ltd Semiconductor device
JP2004179552A (en) * 2002-11-28 2004-06-24 Nec Corp Mounting structure and mounting method for semiconductor device, and reworking method
JP2008091408A (en) * 2006-09-29 2008-04-17 Sharp Corp Semiconductor device, and its manufacturing method
JP2012079962A (en) * 2010-10-04 2012-04-19 Mitsubishi Electric Corp Semiconductor device and method of manufacturing semiconductor device
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