JP2019047043A - Stacked semiconductor device, semiconductor device substrate, and manufacturing method thereof - Google Patents

Stacked semiconductor device, semiconductor device substrate, and manufacturing method thereof Download PDF

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JP2019047043A
JP2019047043A JP2017170672A JP2017170672A JP2019047043A JP 2019047043 A JP2019047043 A JP 2019047043A JP 2017170672 A JP2017170672 A JP 2017170672A JP 2017170672 A JP2017170672 A JP 2017170672A JP 2019047043 A JP2019047043 A JP 2019047043A
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semiconductor element
electrode
bonding
insulating layer
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井口　義則
Yoshinori Iguchi
義則 井口
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers

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Abstract

To provide a stacked semiconductor device in which defects due to misalignment of junctions are reduced and sufficient insulation of an insulating film in the vicinity of a junction surface is ensured.SOLUTION: A stacked semiconductor device 10 formed by bonding the surfaces of two semiconductor device substrates 1 to each other includes an insulator 60 in which insulating films covering the surface of each of the semiconductor element substrates 1 are joined to each other and an electrode 70 in which columnar electrodes exposed on the surface are joined to each other. A void 80 is formed in the insulator 60, and the electrode 70 penetrates the void 80 by forming a recess surrounding the electrode on the surface of the semiconductor element substrate 1, and the side surfaces of the electrode 70 sandwiches the void 80 to face the insulator 60, thereby being in non-contact with the insulator 60.SELECTED DRAWING: Figure 2

Description

本発明は、半導体素子と表面に露出した電極を形成した基板同士を接合して電気的に接続された３次元構造を有する積層型半導体素子に関する。   The present invention relates to a stacked semiconductor device having a three-dimensional structure in which a substrate on which a semiconductor device and an electrode exposed on the surface are formed is joined and electrically connected.

半導体集積回路のいっそうの大規模化、高密度化を実現するために、半導体回路を３次元的に積層した、積層型半導体素子が開発されている。積層方向に配置した半導体素子同士を電気的に接続するために、半導体素子をそれぞれ形成した複数枚のウェハまたはチップ（半導体素子基板）を、それぞれの接合面に露出させた電極同士で接合するが、電極だけでなくその周囲の絶縁膜同士でも接合するハイブリッド接合技術が知られている（非特許文献１参照）。ハイブリッド接合による積層型半導体素子（以下、適宜、接合型半導体素子と称する）は、一例として、図１に示すように、半導体素子構造２を表層に形成した２枚のＳｉ基板２１，２２を、それぞれの表側を対面させて（Ｆａｃｅ−ｔｏ−Ｆａｃｅ）、Ｓｉ基板２１，２２の各半導体素子構造２の端子に接続する配線３，３間を、柱状の電極（柱状電極）７０で接続した構造である。Ｓｉ基板２１，２２間の図１に空白で表される領域には、ＳｉＯ2，ＳｉＯＣ等の絶縁体が設けられ、配線３，３およびそれらの間を接続する柱状電極７０が、この絶縁体を貫通している。 In order to realize a larger scale and higher density of semiconductor integrated circuits, stacked semiconductor elements in which semiconductor circuits are three-dimensionally stacked have been developed. In order to electrically connect the semiconductor elements arranged in the stacking direction, a plurality of wafers or chips (semiconductor element substrates) on which the semiconductor elements are respectively formed are bonded by electrodes exposed on their bonding surfaces. There is known a hybrid bonding technique in which not only electrodes but also insulating films around them are bonded (see Non-Patent Document 1). As shown in FIG. 1, as an example, as shown in FIG. 1, a stacked semiconductor device by hybrid junction (hereinafter appropriately referred to as a junction-type semiconductor device) includes two Si substrates 21 and 22 having a semiconductor device structure 2 formed on the surface thereof. A structure in which pillar-shaped electrodes (columnar electrodes) 70 connect the wires 3 and 3 connected to the terminals of the semiconductor device structures 2 of the Si substrates 21 and 22 with their front sides facing each other (Face-to-Face) It is. An insulator such as SiO 2 or SiOC is provided in a region between the Si substrates 21 and 22 which is shown as a blank in FIG. 1, and the wires 3 and 3 and the columnar electrodes 70 connecting them are the insulators. Through.

図３０に示すように、Ｓｉ基板２１，２２（図中、符号「２０」を付して表す）はそれぞれ、その上に、半導体素子構造２に接続する配線３と、半導体素子構造２上を被覆して配線３間を絶縁する絶縁層４と、絶縁層４上に積層される絶縁層５，６１と、一部の配線３の上面に接続して表面に露出する柱状の電極７Ｃと、を備え、表面を平滑化して半導体素子基板１０１に製造される。そして、一組（２枚）の半導体素子基板１０１，１０１のそれぞれの表面（接合面）を対面させて、電極７Ｃ，７Ｃ同士を接合すると同時に、絶縁層６１，６１同士も接合するハイブリッド接合によって、接合型半導体素子１１０が得られる。図３１に接合面近傍を示すように、接合型半導体素子１１０において、半導体素子基板１０１，１０１のそれぞれの絶縁層６１，６１は表面同士で接合されて一体の絶縁体６０となり、電極７Ｃ，７Ｃは柱状電極７０となる。   As shown in FIG. 30, the Si substrates 21 and 22 (represented by reference numeral "20" in the figure) respectively have the wiring 3 connected to the semiconductor element structure 2 and the semiconductor element structure 2 above. An insulating layer 4 for covering to insulate between the wirings 3, insulating layers 5 and 61 stacked on the insulating layer 4, and a columnar electrode 7C connected to the upper surface of a part of the wirings 3 and exposed on the surface The semiconductor device substrate 101 is manufactured by smoothing the surface. The respective surfaces (bonding surfaces) of one set of (two) semiconductor element substrates 101 face each other to join the electrodes 7C and 7C with each other, and at the same time join the insulating layers 61 and 61 with each other. The junction type semiconductor device 110 is obtained. As shown in FIG. 31 in the vicinity of the bonding surface, in the bonding type semiconductor element 110, the respective insulating layers 61, 61 of the semiconductor element substrates 101, 101 are bonded together at their surfaces to form an integral insulator 60, and the electrodes 7C, 7C. Becomes the columnar electrode 70.

半導体素子基板１０１の表面を被覆する絶縁層６１に用いられるＳｉＯ2，ＳｉＯＣは、絶縁材料の中で特に絶縁性に優れ、また、ＣＭＰ（化学機械研磨：Chemical Mechanical Polishing）法により、接合に好適な表面粗さに平滑化し易い。一方、電極７Ｃに用いられるＣｕは、電極材料の中でも導電性に優れることから、半導体素子の配線の微細化に伴い多く適用されるようになったが、ＳｉやＳｉＯ2等に拡散し易い。そこで、Ｃｕで形成される配線は、一般に、ＳｉＯ2，ＳｉＯＣからなる絶縁層へのＣｕの熱拡散や相互反応による電流のリーク等の信頼性低下を防止するために、Ｔａ，Ｔｉ，ＴｉＮ等からなる数〜数十ｎｍ程度の膜厚のバリア膜（バリアメタル膜）で被覆される。したがって、図３１に示すように、接合型半導体素子１１０は、その接合面（図中、一点鎖線で表す）近傍において、電極７ＣのＣｕからなるコア部（プラグ）７２の側面にバリア膜７１が形成されている。このようなバリア膜付きの電極７Ｃは、例えば、ダマシン法により形成される。詳しくは、成膜した絶縁層６１，５をエッチングして電極７Ｃの形状の孔を配線３上に形成した後に、スパッタ法等によりバリア膜７１、シード層（Ｃｕ膜）を順次成膜し、次に、電解めっきでＣｕを絶縁層６１，５の孔に埋め込む。そして、ＣＭＰ法で表面を研削、研磨して、金属膜（７２，７１）に被覆されていた絶縁層６１を露出させ、電極７Ｃと共に表面を平坦、平滑化する。このような方法によるため、電極７Ｃは、底面もバリア膜７１で被覆され、一方、表面にはＣｕからなるプラグ７２が露出する。なお、絶縁層５は、Ｓｉ窒化物やＳｉＣ等からなり、Ｃｕに拡散され難いので、下の配線３から絶縁層６１へのＣｕの拡散を遮蔽する拡散防止絶縁膜であり、また、ＳｉＯ2等からなる絶縁層６１のエッチングストッパ膜になる。 Among the insulating materials, SiO 2 and SiOC used for the insulating layer 61 covering the surface of the semiconductor element substrate 101 are particularly excellent in the insulating property, and are suitable for bonding by the CMP (Chemical Mechanical Polishing) method. It is easy to smooth to a smooth surface roughness. On the other hand, Cu used for the electrode 7C is widely applied as the wiring of the semiconductor element becomes finer because it is excellent in conductivity among electrode materials, but it easily diffuses to Si, SiO 2 or the like. Therefore, in order to prevent the deterioration of the reliability such as the leak of the current due to the thermal diffusion or mutual reaction of Cu to the insulating layer consisting of SiO 2 and SiOC, the wiring formed of Cu is generally Ta, Ti, TiN, etc. And a barrier film (barrier metal film) having a thickness of several to several tens of nm. Therefore, as shown in FIG. 31, in the junction-type semiconductor device 110, the barrier film 71 is formed on the side surface of the core portion (plug) 72 made of Cu of the electrode 7C in the vicinity of the junction surface (represented by a dashed dotted line in the diagram). It is formed. Such an electrode 7C with a barrier film is formed, for example, by a damascene method. Specifically, the formed insulating layers 61 and 5 are etched to form holes in the shape of the electrode 7C on the wiring 3, and then a barrier film 71 and a seed layer (Cu film) are sequentially formed by sputtering or the like. Next, Cu is embedded in the holes of the insulating layers 61 and 5 by electrolytic plating. Then, the surface is ground and polished by the CMP method to expose the insulating layer 61 covered with the metal film (72, 71) and to flatten and smooth the surface together with the electrode 7C. By this method, the bottom of the electrode 7C is also covered with the barrier film 71, while the plug 72 made of Cu is exposed on the surface. The insulating layer 5 is made of Si nitride, SiC or the like, so hard to be diffused in Cu, the diffusion preventing insulating film for shielding the diffusion of Cu from the bottom of the wiring 3 to the insulating layer 61, also, SiO 2 And an etching stopper film of the insulating layer 61.

ここで、ウェハやチップ（半導体素子基板１０１）の接合は、接合装置の位置合わせ精度の限界等により、接合面において、電極の露出面同士を常に完全に一致させて接合することは現実には不可能であり、図３１に示すように、接合された電極７Ｃ，７Ｃ間に位置ずれが生じる。この位置ずれ（電極７Ｃ，７Ｃの各中心間の距離）が、図中、左側に示すように電極７Ｃの側面におけるバリア膜７１の膜厚未満の距離ｓ1で、接合面を挟んだバリア膜７１，７１同士の接触長さが一定以上であれば問題ないが、右側に示すように位置ずれがバリア膜７１の膜厚以上の距離ｓ2になると、一方の半導体素子基板１０１の電極７Ｃのプラグ７２と他方の半導体素子基板１０１の絶縁層６１とが接触するので、絶縁層６１へプラグ７２からＣｕが拡散して信頼性が低下することになる。バリア膜７１はＣｕよりも導電性に劣るので厚膜化するほど電極７Ｃの抵抗が増大し、電極７Ｃの径との関係等から厚膜化に限界があり、このようなバリア膜７１の膜厚未満に位置合わせ誤差を抑制することは極めて困難である。 Here, in the bonding of a wafer or a chip (semiconductor element substrate 101), it is a reality that the exposed surfaces of the electrodes are always perfectly matched and bonded at the bonding surface due to the limit of the alignment accuracy of the bonding apparatus. It is impossible, and as shown in FIG. 31, misalignment occurs between the joined electrodes 7C and 7C. As shown on the left side in the figure, this positional deviation (the distance between the centers of the electrodes 7C and 7C) is a barrier film having a bonding surface sandwiched by a distance s 1 less than the film thickness of the barrier film 71 on the side surface of the electrode 7C. 71 contact length of each other no problem if the predetermined or more, but if positional deviation as shown on the right side is the film thickness over a distance s 2 of the barrier film 71, the one semiconductor element electrode 7C of the substrate 101 Since the plug 72 and the insulating layer 61 of the other semiconductor element substrate 101 are in contact with each other, Cu diffuses from the plug 72 into the insulating layer 61 to lower the reliability. Since the barrier film 71 is inferior in conductivity to Cu, the resistance of the electrode 7C increases as the film thickness is increased, and there is a limit to the film thickness increase from the relationship with the diameter of the electrode 7C, etc. It is extremely difficult to suppress registration errors below the thickness.

そこで、接合の位置ずれに起因する不良を回避し得る接合型半導体素子として、接合面近傍における絶縁体（絶縁膜）に、Ｃｕが拡散し難い材料を設ける技術が開示されている。例えば特許文献１には、接合前における表面（接合面）全体にＴｉ，Ｔａ等の金属膜を成膜し、接合後に熱処理を施して、ＳｉＯ2等の絶縁膜上における金属膜をこの絶縁膜と反応させて絶縁性の金属酸化物とした接合型半導体素子が記載されている。 Therefore, as a junction-type semiconductor element capable of avoiding defects due to misalignment of the junction, a technique is disclosed in which a material to which Cu is not easily diffused is provided in an insulator (insulation film) in the vicinity of the junction surface. For example, in Patent Document 1, a metal film of Ti, Ta or the like is formed on the entire surface (bonding surface) before bonding, and heat treatment is performed after bonding to form a metal film on an insulating film of SiO 2 or the like. A junction-type semiconductor device is described which is made to react with it to form an insulating metal oxide.

特開２０１３−１６８４１９号公報JP, 2013-168419, A

後藤正英，萩原啓，井口義則，大竹浩著，「画素並列信号処理を行う撮像デバイスの実現に向けた３次元集積回路の作製」，ＮＨＫ技研Ｒ＆Ｄ，Ｎｏ．１５３，ｐ．２２−２８，２０１５年９月Goto Masahide, Kuwahara Kei, Iguchi Yoshinori and Otake Hiroshi, "Fabrication of three-dimensional integrated circuit for realization of imaging device performing pixel parallel signal processing", NHK Giken R & D, No. 153, p. 22-28, September 2015

特許文献１に記載された接合型半導体素子の接合面に形成される金属酸化物の絶縁膜は、ＳｉＯ2に対するＣｕの拡散防止膜とするために、ある程度の膜厚（酸化前の金属膜において１０ｎｍ以上）を要するとされる。しかし、このような膜厚の金属膜を、接触しているＳｉＯ2中のＯのみによって完全には酸化させ難く、また、酸化しても、ＴｉＯ2等の金属酸化物はＳｉ窒化物等よりもさらに絶縁性に劣るため、電流のリークの虞がある。 The insulating film of metal oxide formed on the bonding surface of the junction-type semiconductor device described in Patent Document 1 has a certain thickness (a metal film before oxidation) in order to serve as a diffusion preventing film of Cu to SiO 2 (10 nm or more). However, it is difficult to completely oxidize a metal film of such a thickness by only O in the contacting SiO 2 , and even if it is oxidized, metal oxides such as TiO 2 are better than Si nitride etc. In addition, there is a possibility that current leaks because the insulation property is further inferior.

本発明は前記問題点に鑑み創案されたもので、接合の位置ずれに起因する不良を低減すると共に、接合面近傍における絶縁膜の十分な絶縁性が確保される接合型半導体素子を提供することを課題とする。   The present invention has been made in view of the above problems, and provides a junction type semiconductor device capable of reducing defects caused by displacement of junction and ensuring sufficient insulation of an insulating film in the vicinity of a junction surface. As an issue.

すなわち、本発明に係る積層型半導体素子は、積層方向に沿った柱状電極で層間を接続し、積層方向における前記柱状電極が設けられた領域で、前記柱状電極の側面と絶縁体とが空隙を挟んで対向している構成とした。   That is, in the stacked semiconductor device according to the present invention, the interlayers are connected by the columnar electrodes extending in the stacking direction, and the side surfaces of the columnar electrodes and the insulator are voids in the region where the columnar electrodes are provided in the stacking direction. It was set as the structure which has pinched | faced and opposed.

かかる構成により、積層型半導体素子は、接合面に設けたＳｉＯ2のような絶縁体に電極が非接触であり、電極のＣｕが絶縁体中へ拡散することがない。 According to this configuration, in the stacked semiconductor element, the electrode is not in contact with the insulator such as SiO 2 provided on the bonding surface, and Cu of the electrode does not diffuse into the insulator.

本発明に係る半導体素子基板は、半導体素子が形成された基板と、前記半導体素子に電気的に接続した柱状電極と、前記柱状電極を露出させて前記基板上を被覆する絶縁体とを備え、前記柱状電極を囲む凹みを上面に有し、前記絶縁体が前記柱状電極と非接触な構成とした。   A semiconductor device substrate according to the present invention includes a substrate on which a semiconductor device is formed, a columnar electrode electrically connected to the semiconductor device, and an insulator which exposes the columnar electrode and covers the substrate. A recess surrounding the columnar electrode is provided on the upper surface, and the insulator is not in contact with the columnar electrode.

かかる構成により、半導体素子基板は、ハイブリッド接合された際に、接合面に形成されている凹みの範囲内であれば位置ずれを生じても、一方の電極が他方の絶縁体に接触することのない積層型半導体素子を構成する。   According to such a configuration, when the semiconductor element substrate is hybrid-bonded, even if misalignment occurs within the range of the recess formed in the bonding surface, one of the electrodes contacts the other insulator. To form a stacked semiconductor device.

本発明に係る半導体素子基板の製造方法は、上面に柱状電極が露出した半導体素子基板の製造方法であって、半導体素子が形成された基板上に、絶縁膜を成膜する絶縁膜成膜工程と、柱状電極が形成される領域を空けたマスクを形成するマスク工程と、前記絶縁膜をエッチングする絶縁膜エッチング工程と、電極材料を成膜して、前記マスクの空いた領域に柱状電極を形成する電極成膜工程と、前記マスクを除去するリフトオフ工程とを行い、前記絶縁膜エッチング工程は、等方性エッチングを行い、前記絶縁膜を、少なくともその上面において、前記柱状電極が形成される領域を超えて除去する手順とした。   A method of manufacturing a semiconductor element substrate according to the present invention is a method of manufacturing a semiconductor element substrate in which columnar electrodes are exposed on the upper surface, and an insulating film forming step of forming an insulating film on a substrate on which semiconductor elements are formed. And a mask process for forming a mask in which a region in which the columnar electrode is formed is formed, an insulating film etching process for etching the insulating film, and depositing an electrode material, and forming the columnar electrode in the vacant region of the mask An electrode film forming process to be formed and a lift-off process to remove the mask are performed, and the insulating film etching process performs isotropic etching to form the columnar electrode at least on the upper surface of the insulating film. The procedure was to remove over the area.

本発明に係る別の半導体素子基板の製造方法は、半導体素子が形成された基板上に、柱状電極が形成される領域を空けた絶縁膜を形成する絶縁膜形成工程と、電極材料を成膜して、前記基板上の前記絶縁膜の空いた領域に柱状電極を形成する電極形成工程とを行って、最上層に設けられた絶縁膜および前記絶縁膜を貫通して露出する柱状電極を形成した後に、前記柱状電極が露出している領域の周囲を少なくとも空けたマスクを形成するマスク工程と、前記絶縁膜を、その厚さ以下をエッチングする絶縁膜エッチング工程と、前記マスクを除去するマスク除去工程と、を行う手順とした。   Another method of manufacturing a semiconductor element substrate according to the present invention includes an insulating film forming step of forming an insulating film having an area in which a columnar electrode is formed on a substrate on which a semiconductor element is formed; And an electrode forming step of forming a columnar electrode in a region where the insulating film is open on the substrate, thereby forming an insulating film provided on the uppermost layer and a columnar electrode exposed through the insulating film. A mask step of forming a mask at least at the periphery of the exposed region of the columnar electrode, an insulating film etching step of etching the insulating film less than its thickness, and a mask for removing the mask And the removal step.

かかる手順により、上面同士でハイブリッド接合された際に、一方の電極が他方の絶縁体に接触することのない積層型半導体素子を構成する半導体素子基板を製造することができる。   According to this procedure, it is possible to manufacture a semiconductor element substrate that constitutes a stacked semiconductor element in which one electrode is not in contact with the other insulator when the upper surfaces are hybrid-bonded.

本発明に係る積層型半導体素子の製造方法は、前記のいずれかの半導体素子基板の製造方法を行って、それぞれの上面における電極の配置が対称な２つの半導体素子基板を製造する半導体素子基板製造工程と、前記２つの半導体素子基板の上面同士を前記電極および絶縁体のそれぞれで接合する接合工程と、を行う手順とした。   In the method of manufacturing a stacked semiconductor device according to the present invention, a method of manufacturing a semiconductor device substrate is performed by performing any one of the methods of manufacturing a semiconductor device substrate described above to manufacture two semiconductor device substrates in which the arrangement of electrodes on their upper surfaces is symmetrical. It is set as the procedure of performing a process and the joining process which joins the upper surfaces of the said 2 semiconductor element board | substrates by each of the said electrode and insulator.

かかる手順により、上面同士でハイブリッド接合する際にある程度の位置ずれを生じても、電極が絶縁体に接触していない積層型半導体素子が得られる。   According to this procedure, even if positional deviation occurs to some extent when hybrid bonding is performed on the upper surfaces, a stacked semiconductor device in which the electrodes are not in contact with the insulator can be obtained.

本発明に係る積層型半導体素子によれば、ハイブリッド接合された際の位置ずれに起因する不良が低減される。本発明に係る半導体素子基板によれば、２つをハイブリッド接合して積層型半導体素子に製造する際の、接合作業が容易となる。本発明に係る半導体素子基板の製造方法によれば、前記半導体素子基板を、従来の製造方法に対して工程を多く増やすことなく製造することができる。本発明に係る積層型半導体素子の製造方法によれば、ハイブリッド接合される際の位置ずれの許容範囲が大きく、接合作業が容易となる。   According to the stacked semiconductor device of the present invention, defects due to misalignment when hybrid bonding is reduced. According to the semiconductor element substrate according to the present invention, the bonding operation is facilitated when the two are hybrid-bonded to produce a stacked semiconductor element. According to the method of manufacturing a semiconductor element substrate according to the present invention, the semiconductor element substrate can be manufactured without increasing the number of steps compared to the conventional manufacturing method. According to the method of manufacturing a stacked semiconductor device according to the present invention, the allowable range of positional deviation at the time of hybrid bonding is large, and the bonding operation becomes easy.

積層型半導体素子の概念を説明する模式図である。It is a schematic diagram explaining the concept of a laminated semiconductor element. 本発明の第１実施形態に係る積層型半導体素子の構造を説明する部分断面図である。It is a fragmentary sectional view explaining the structure of the lamination type semiconductor device concerning a 1st embodiment of the present invention. 図２に示す積層型半導体素子を構成する接合前の半導体素子基板の構造を説明する部分断面図である。It is a fragmentary sectional view explaining the structure of the semiconductor element substrate before joining which comprises the laminated type semiconductor element shown in FIG. 本発明に係る積層型半導体素子の製造方法を説明するフローチャートである。It is a flowchart explaining the manufacturing method of the lamination type semiconductor element concerning the present invention. 本発明の第１実施形態に係る半導体素子基板の製造方法を説明するフローチャートである。It is a flowchart explaining the manufacturing method of the semiconductor element substrate concerning a 1st embodiment of the present invention. 本発明の第１実施形態に係る半導体素子基板の製造方法を説明する模式図であり、（ａ）は配線形成工程、（ｂ）はマスク工程、（ｃ）は絶縁膜等方性エッチング工程、（ｄ）は拡散防止絶縁膜エッチング工程のそれぞれにおける部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on 1st Embodiment of this invention, (a) is a wiring formation process, (b) is a mask process, (c) is an insulating film isotropic etching process, (D) is a fragmentary sectional view in each of a diffusion prevention insulating film etching process. 本発明の第１実施形態に係る半導体素子基板の製造方法を説明する模式図であり、電極成膜工程における部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on 1st Embodiment of this invention, and is a fragmentary sectional view in an electrode film-forming process. 図２に示す積層型半導体素子を構成する変形例に係る接合前の半導体素子基板の構造を説明する接合面近傍の部分断面図である。FIG. 13 is a partial cross-sectional view in the vicinity of a bonding surface for describing the structure of a semiconductor element substrate before bonding according to a modified example of the stacked semiconductor element shown in FIG. 2; 本発明の第２実施形態に係る積層型半導体素子の構造を説明する接合面近傍の部分断面図である。It is a fragmentary sectional view of the bonded surface vicinity explaining the structure of the laminated semiconductor element concerning a 2nd embodiment of the present invention. 図９に示す積層型半導体素子を構成する接合前の半導体素子基板の構造を説明する接合面近傍の部分断面図である。FIG. 10 is a partial cross-sectional view in the vicinity of a bonding surface for describing the structure of a semiconductor element substrate before bonding which constitutes the stacked semiconductor element shown in FIG. 9; 本発明の第２実施形態に係る半導体素子基板の製造方法を説明するフローチャートである。It is a flowchart explaining the manufacturing method of the semiconductor element substrate concerning a 2nd embodiment of the present invention. 本発明の第２実施形態に係る半導体素子基板の製造方法を説明する模式図であり、（ａ）は絶縁膜等方性エッチング工程、（ｂ）は絶縁膜エッチング工程、（ｃ）は拡散防止絶縁膜エッチング工程のそれぞれにおける部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on 2nd Embodiment of this invention, (a) is an insulating film isotropic etching process, (b) is an insulating film etching process, (c) is a diffusion prevention. It is a fragmentary sectional view in each of an insulating film etching process. 本発明の第２実施形態に係る半導体素子基板の製造方法を説明する模式図であり、電極成膜工程における部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on 2nd Embodiment of this invention, and is a fragmentary sectional view in an electrode film-forming process. 本発明の第３実施形態に係る積層型半導体素子の構造を説明する接合面近傍の部分断面図である。It is a fragmentary sectional view of the junction side vicinity explaining the structure of the lamination type semiconductor element concerning a 3rd embodiment of the present invention. 図１４に示す積層型半導体素子を構成する接合前の半導体素子基板の構造を説明する接合面近傍の部分断面図である。FIG. 15 is a partial cross-sectional view in the vicinity of a bonding surface for describing the structure of a semiconductor element substrate before bonding which constitutes the stacked semiconductor element shown in FIG. 14; 本発明の第３実施形態に係る半導体素子基板の製造方法を説明するフローチャートである。It is a flowchart explaining the manufacturing method of the semiconductor element substrate concerning a 3rd embodiment of the present invention. 本発明の第３実施形態に係る半導体素子基板の製造方法を説明する模式図であり、（ａ）はマスク工程、（ｂ）はマスク除去工程、（ｃ）はバリア膜成膜工程およびシード成膜工程、（ｄ）は電極成膜工程のそれぞれにおける部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on 3rd Embodiment of this invention, (a) is a mask process, (b) is a mask removal process, (c) is a barrier film film formation process, and seed formation A film process and (d) are partial sectional views in each of the electrode film forming process. 本発明の第３実施形態に係る半導体素子基板の製造方法を説明する模式図であり、（ａ）は平滑化工程、（ｂ）はマスク工程、（ｃ）は絶縁膜エッチング工程のそれぞれにおける部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on 3rd Embodiment of this invention, (a) is a smoothing process, (b) is a mask process, (c) is the part in each of an insulating film etching process. FIG. 図１４に示す積層型半導体素子を構成する変形例に係る接合前の半導体素子基板の構造を説明する接合面近傍の部分断面図である。FIG. 15 is a partial cross-sectional view in the vicinity of a bonding surface for describing the structure of a semiconductor element substrate before bonding according to a modification of the stacked semiconductor element shown in FIG. 14; 本発明の第３実施形態の変形例に係る半導体素子基板の製造方法を説明する模式図であり、絶縁膜エッチング工程における部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on the modification of 3rd Embodiment of this invention, and is a fragmentary sectional view in an insulating film etching process. 本発明の第４実施形態に係る積層型半導体素子の構造を説明する接合面近傍の部分断面図である。It is a fragmentary sectional view of the bonded surface vicinity explaining the structure of the lamination type semiconductor element concerning a 4th embodiment of the present invention. 図２１に示す積層型半導体素子を構成する接合前の半導体素子基板の構造を説明する接合面近傍の部分断面図である。FIG. 22 is a partial cross-sectional view in the vicinity of a bonding surface for describing the structure of a semiconductor element substrate before bonding which forms the stacked semiconductor element shown in FIG. 21; 本発明の第５実施形態に係る積層型半導体素子の構造を説明する部分断面図である。It is a fragmentary sectional view explaining the structure of the lamination type semiconductor element concerning a 5th embodiment of the present invention. 図２３に示す積層型半導体素子を構成する接合前の半導体素子基板の構造を説明する接合面近傍の部分断面図である。FIG. 24 is a partial cross-sectional view in the vicinity of a bonding surface for describing the structure of a semiconductor element substrate before bonding which constitutes the stacked semiconductor element shown in FIG. 23; 本発明の第５実施形態に係る半導体素子基板の製造方法を説明するフローチャートである。It is a flowchart explaining the manufacturing method of the semiconductor element substrate concerning a 5th embodiment of the present invention. 本発明の第５実施形態に係る半導体素子基板の製造方法を説明する模式図であり、部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on 5th Embodiment of this invention, and is a fragmentary sectional view. 本発明の第５実施形態に係る半導体素子基板の製造方法を説明する模式図であり、部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on 5th Embodiment of this invention, and is a fragmentary sectional view. 本発明の第５実施形態の変形例に係る半導体素子基板の製造方法を説明するフローチャートである。It is a flowchart explaining the manufacturing method of the semiconductor element substrate concerning the modification of a 5th embodiment of the present invention. 本発明の第５実施形態の変形例に係る半導体素子基板の製造方法を説明する模式図であり、部分断面図である。It is a schematic diagram explaining the manufacturing method of the semiconductor element substrate which concerns on the modification of 5th Embodiment of this invention, and is a fragmentary sectional view. 従来の積層型半導体素子を構成する接合前の半導体素子基板の構造を説明する部分断面図である。It is a fragmentary sectional view explaining the structure of the semiconductor element substrate before joining which constitutes the conventional lamination type semiconductor element. 従来の積層型半導体素子の構造を説明する接合面近傍の部分断面図である。FIG. 14 is a partial cross-sectional view in the vicinity of a bonding surface for describing the structure of a conventional stacked semiconductor device.

本発明に係る接合型半導体素子（積層型半導体素子）を実現するための形態について、図を参照して説明する。本明細書において、積層型半導体素子とは、半導体素子構造を２層以上に備え、異なる層の半導体素子構造同士が電気的に接続された３次元回路構造を有する半導体素子を指す。特に、半導体素子構造を形成した２枚の基板の各表面に露出させた配線間で接合することにより接続したものを、接合型半導体素子と称する。図面に示す接合型半導体素子およびその要素は、説明を明確にするために、大きさや位置関係等を誇張していることがあり、また、形状や構造を単純化していることがある。   An embodiment for realizing a junction-type semiconductor device (stacked semiconductor device) according to the present invention will be described with reference to the drawings. In this specification, a stacked semiconductor device refers to a semiconductor device having a three-dimensional circuit structure in which semiconductor device structures are provided in two or more layers and semiconductor device structures in different layers are electrically connected to each other. In particular, those connected by bonding between the wirings exposed on the surfaces of the two substrates on which the semiconductor device structure is formed are referred to as bonded semiconductor devices. The junction-type semiconductor device and its elements shown in the drawings may have exaggerated in size, positional relationship, etc. for the sake of clarity, and may have simplified shapes and structures.

（接合型半導体素子）
本発明に係る接合型半導体素子１０は、図１に示すように、２枚のＳｉ基板２１，２２を、それぞれの半導体素子構造２を形成した側（表側）同士を対面させて備える。このような接合型半導体素子１０は、図２に示すように、Ｓｉ基板２１を備える半導体素子基板１１と、Ｓｉ基板２２を備える半導体素子基板１２とを、Ｓｉ基板２１，２２の半導体素子構造２を形成した側（表側）同士を対面させて接合（Ｆａｃｅ−ｔｏ−Ｆａｃｅ接合）して得られる。したがって、上側のＳｉ基板２２およびこれを備える半導体素子基板１２は、上下に裏返して図示される。また、半導体素子基板１１，１２の接合面を、図２に一点鎖線で表す。接合型半導体素子１０は、Ｓｉ基板２１，２２のそれぞれに形成された半導体素子構造２，２同士を電気的に接続するために、Ｓｉ基板２１，２２間に、前記半導体素子構造２，２の各端子に接続する配線３，３と、配線３，３間を接続する柱状電極７０と、間隙（図１に空白で表される領域）を一部を除いて充填する絶縁体と、をさらに備える。配線３等のＳｉ基板２１，２２以外の部品も、以下に説明するように半導体素子基板１１，１２に設けられる。 (Junction type semiconductor device)
As shown in FIG. 1, the junction-type semiconductor device 10 according to the present invention is provided with two Si substrates 21 and 22 with the sides (front side) on which the respective semiconductor device structures 2 are formed facing each other. As shown in FIG. 2, such a junction-type semiconductor device 10 includes a semiconductor device substrate 11 provided with a Si substrate 21 and a semiconductor device substrate 12 provided with a Si substrate 22. It is obtained by bringing the sides (front side) on which they are formed face to face and bonding (Face-to-Face bonding). Therefore, the upper Si substrate 22 and the semiconductor element substrate 12 provided with the upper Si substrate 22 are illustrated upside down. Further, the bonding surfaces of the semiconductor element substrates 11 and 12 are represented by dashed-dotted lines in FIG. The junction-type semiconductor device 10 is provided between the Si substrates 21 and 22 in order to electrically connect the semiconductor device structures 2 and 2 formed on the Si substrates 21 and 22, respectively. Wirings 3 and 3 connected to the respective terminals, a columnar electrode 70 connecting the wirings 3 and 3, and an insulator for filling a gap (a region represented by a blank in FIG. 1) except for a part thereof are further added Prepare. Parts other than the Si substrates 21 and 22 such as the wires 3 are also provided on the semiconductor element substrates 11 and 12 as described below.

接合型半導体素子１０を構成するために、半導体素子基板１１は、図３に示すように、Ｓｉ基板２１（図中、符号「２０」を付して表す）上に、絶縁層４、拡散防止絶縁膜５、絶縁層（絶縁体）６１を順次積層して備え、半導体素子構造２の端子に接続する配線３と、配線３に接続して表面に露出する接合電極（柱状電極）７をさらに備える。同様に、半導体素子基板１２は、Ｓｉ基板２２上に、絶縁層４、拡散防止絶縁膜５、絶縁層６１、配線３、および接合電極７を備える。接合型半導体素子１０において、半導体素子基板１１，１２のそれぞれの絶縁層６１，６１は表面同士で接合されて一体の絶縁体６０となり、接合電極７，７は柱状電極７０となる。したがって、接合型半導体素子１０の絶縁体は、Ｓｉ基板２１，２２のそれぞれの側から順に設けられた絶縁層４、拡散防止絶縁膜５、ならびに拡散防止絶縁膜５，５間の絶縁体６０で構成される。そのために、半導体素子基板１１，１２は、平面視で、互いに接合電極７が左右対称に配置されている。接合型半導体素子１０は、このような構造により、異なるＳｉ基板２１，２２のそれぞれに形成された半導体素子構造２，２が、対面させて重ねられたＳｉ基板２１，２２の間に設けられた絶縁体６０を上下に貫通する柱状電極７０で電気的に接続される。半導体素子基板１１と半導体素子基板１２は概ね同じ構造であり、特定しない場合に半導体素子基板１と称し、それぞれに設けられたＳｉ基板２１，２２をＳｉ基板２０と称する。   In order to form the junction-type semiconductor device 10, as shown in FIG. 3, the semiconductor device substrate 11 has the insulating layer 4 and the diffusion prevention on the Si substrate 21 (indicated by reference numeral 20 in the figure). An insulating film 5 and an insulating layer (insulator) 61 are sequentially stacked and provided, and a wire 3 connected to a terminal of the semiconductor element structure 2 and a bonding electrode (columnar electrode) 7 connected to the wire 3 and exposed on the surface are further provided. Prepare. Similarly, the semiconductor element substrate 12 includes the insulating layer 4, the diffusion preventing insulating film 5, the insulating layer 61, the wiring 3, and the bonding electrode 7 on the Si substrate 22. In the junction-type semiconductor device 10, the respective insulating layers 61, 61 of the semiconductor device substrates 11, 12 are joined together at their surfaces to form an integral insulator 60, and the junction electrodes 7, 7 become columnar electrodes 70. Therefore, the insulator of the junction-type semiconductor device 10 is the insulator 60 provided between the sides of the Si substrates 21 and 22 in order, the diffusion preventing insulating film 5, and the insulator 60 between the diffusion preventing insulating films 5 and 5. Configured Therefore, in the semiconductor element substrates 11 and 12, the bonding electrodes 7 are arranged symmetrically in a plan view. In the junction-type semiconductor device 10, the semiconductor device structures 2 and 2 formed on the different Si substrates 21 and 22 are provided between the Si substrates 21 and 22 facing each other with the above-described structure. It is electrically connected by the columnar electrode 70 which penetrates the insulator 60 up and down. The semiconductor element substrate 11 and the semiconductor element substrate 12 have substantially the same structure, and when not specified, they are referred to as the semiconductor element substrate 1, and the Si substrates 21 and 22 provided thereon are referred to as the Si substrate 20.

本明細書では、半導体素子構造２を、Ｓｉ基板２１，２２の表層に形成されたＳＯＩ（Silicon on Insulator）ＭＯＳＦＥＴ（金属酸化膜半導体電界効果トランジスタ）とする。さらに、図１に示す部分において、Ｓｉ基板２１にｎ型ＭＯＳ（ＮＭＯＳ）のみを、Ｓｉ基板２２にｐ型ＭＯＳ（ＰＭＯＳ）のみをそれぞれ示しているが、１枚のＳｉ基板２０に１種類の半導体素子構造２を備えることを規定するものではない。すなわち、これらは半導体素子の概念を簡潔かつ模式的に示したものであって、特定の機能を有するものに限定されない。さらに、図１では簡潔に説明するために、Ｓｉ基板２１，２２のそれぞれの半導体素子構造２を上下対称となる構造とし、それぞれの端子（ソース、ドレイン、ゲート）に接続する配線を絶縁層４において単層の配線構造の配線３として、ドレイン同士の２箇所、ゲート同士の１箇所をそれぞれ柱状電極７０で直接に接続している。しかし、半導体素子基板１１，１２のそれぞれが多層配線構造を備えてもよく、多層配線とすることで、半導体素子基板１１，１２間を接続する柱状電極７０（接合電極７）の数を抑え、接合電極７を大径化、大ピッチとして、接合における位置ずれの許容範囲を大きくすることができる。接合装置の位置合わせ精度等にもよるが、接合電極７の表面における径（または幅）Ｗは１μｍ程度以上であることが好ましい。以下、本発明に係る接合型半導体素子の実施形態を詳細に説明する。   In the present specification, the semiconductor element structure 2 is an SOI (Silicon on Insulator) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed on the surface layer of the Si substrates 21 and 22. Furthermore, in the portion shown in FIG. 1, only the n-type MOS (NMOS) is shown on the Si substrate 21 and only the p-type MOS (PMOS) is shown on the Si substrate 22. The provision of the semiconductor element structure 2 is not stipulated. That is, these simply and schematically show the concept of a semiconductor device, and are not limited to those having a specific function. Furthermore, in FIG. 1, in order to be described briefly, the semiconductor element structures 2 of the Si substrates 21 and 22 are vertically symmetrical, and the wiring connected to the respective terminals (source, drain, gate) is the insulating layer 4 In the wiring 3 of the single layer wiring structure, two places between drains and one place between gates are directly connected by a columnar electrode 70, respectively. However, each of the semiconductor element substrates 11 and 12 may have a multilayer wiring structure, and the number of columnar electrodes 70 (junction electrodes 7) connecting between the semiconductor element substrates 11 and 12 can be reduced by forming the multilayer wiring. By making the bonding electrode 7 larger in diameter and larger in pitch, the allowable range of positional deviation in bonding can be made larger. The diameter (or width) W on the surface of the bonding electrode 7 is preferably about 1 μm or more, although it depends on the alignment accuracy of the bonding device. Hereinafter, embodiments of the junction-type semiconductor device according to the present invention will be described in detail.

〔第１実施形態〕
図２に示すように、本発明の第１実施形態に係る接合型半導体素子１０は、絶縁体６０を上下に貫通する空隙８０を有し、さらにこの空隙８０を、絶縁体６０の上側の拡散防止絶縁膜５から下側の拡散防止絶縁膜５までの高さ位置に設けられた柱状電極７０が上下に貫通している。言い換えると、空隙８０を挟んで柱状電極７０の側面と絶縁体６０が対向していて、そのため、柱状電極７０に絶縁体６０が接触しない。このような空隙８０が設けられるように、絶縁体６０に柱状電極７０の径よりも大口径の空洞が形成されている。また、絶縁体６０ならびにその上下それぞれの拡散防止絶縁膜５および絶縁層４を一体の絶縁体とみなすと、接合型半導体素子１０は、この絶縁体の接合面を含む一部の領域に、空隙８０を有するといえる。空隙８０は、真空、またはＡｒ等の不活性気体が封入されている。なお、図２には、２本の柱状電極７０とそれぞれに貫通される空隙８０を示し、接合型半導体素子１０が接合されていることを表すために、柱状電極７０および空隙８０（絶縁体６０）の１つ（図中、右側）が接合面で段差を有しているが、理想的には別の１つ（図中、左側）のように段差がなく、柱状電極７０は柱体であり、空隙８０は断面形状が横長の略長円（１／２円弧が略１／２楕円弧）である。 First Embodiment
As shown in FIG. 2, the junction-type semiconductor device 10 according to the first embodiment of the present invention has an air gap 80 penetrating the insulator 60 up and down, and the air gap 80 is further diffused on the upper side of the insulator 60. A columnar electrode 70 provided at a height position from the preventing insulating film 5 to the lower diffusion preventing insulating film 5 vertically penetrates. In other words, the side surface of the columnar electrode 70 and the insulator 60 are opposed to each other with the air gap 80 interposed therebetween, so that the insulator 60 does not contact the columnar electrode 70. A cavity having a larger diameter than the diameter of the columnar electrode 70 is formed in the insulator 60 so as to provide such an air gap 80. When the insulator 60 and the upper and lower diffusion preventing insulating films 5 and the insulating layer 4 are regarded as an integral insulator, the junction-type semiconductor device 10 has a void in a partial region including the junction surface of the insulator. It can be said that it has 80. The air gap 80 is filled with vacuum or an inert gas such as Ar. Note that FIG. 2 shows the two columnar electrodes 70 and the air gaps 80 penetrated respectively, and in order to indicate that the junction type semiconductor element 10 is joined, the columnar electrodes 70 and the air gaps 80 (insulator 60 (Right side in the figure) has a step on the bonding surface, but ideally there is no step as in the other one (left side in the figure), and the columnar electrode 70 is a columnar body. The air gap 80 is a substantially elongated circle whose cross-sectional shape is horizontally long (a half arc is a substantially half elliptical arc).

本発明の第１実施形態に係る接合型半導体素子１０を構成する半導体素子基板（本発明の第１実施形態に係る半導体素子基板）１は、図２および図３に示すように、表層に半導体素子構造２を形成されたＳｉ基板２０と、半導体素子構造２に接続する配線３と、Ｓｉ基板２０上を被覆して配線３間を絶縁する絶縁層４と、絶縁層４上に積層された拡散防止絶縁膜５と、拡散防止絶縁膜５に積層されて最表面に形成される絶縁層６１と、一部の配線３の上面に接続して表面に露出する柱状の接合電極７と、を備える。また、半導体素子基板１は、上から見て接合電極７を囲む環状の凹み（ポケット）８が形成されるように、表面に広がって開口した穴が絶縁層６１に形成され、それぞれの穴の底面の中央から柱状の接合電極７が垂直に突設されている。凹み８の表面における開口幅は外径が（Ｗ＋２Ｇ）、内径が接合電極７の径と同じＷ、また、深さ（絶縁層６１の表面からの最大深さ）はＤで表される（Ｇ＞０）。以下、本実施形態に係る接合型半導体素子を構成する各要素について、詳細に説明する。   The semiconductor element substrate (the semiconductor element substrate 1 according to the first embodiment of the present invention) 1 constituting the junction-type semiconductor element 10 according to the first embodiment of the present invention is a semiconductor on the surface as shown in FIGS. An Si substrate 20 on which an element structure 2 is formed, an interconnection 3 connected to the semiconductor element structure 2, an insulating layer 4 covering the Si substrate 20 to insulate the interconnections 3, and an insulating layer 4 stacked A diffusion preventing insulating film 5, an insulating layer 61 stacked on the diffusion preventing insulating film 5 and formed on the outermost surface, and a columnar junction electrode 7 connected to the upper surface of a part of the wires 3 and exposed on the surface Prepare. Further, in the semiconductor element substrate 1, holes which are spread and opened on the surface are formed in the insulating layer 61 so that an annular recess (pocket) 8 surrounding the bonding electrode 7 as viewed from above is formed. Columnar bonding electrodes 7 are vertically protruded from the center of the bottom surface. The opening width at the surface of the recess 8 is represented by W with the outer diameter (W + 2G), the inner diameter being the same as the diameter of the junction electrode 7, and the depth (maximum depth from the surface of the insulating layer 61) by D (G > 0). Hereafter, each element which comprises the junction-type semiconductor element which concerns on this embodiment is demonstrated in detail.

（Ｓｉ基板）
Ｓｉ基板２０は、半導体素子構造２を設けられるための土台であり、特に本実施形態においては、半導体素子構造２がＳＯＩ ＭＯＳＦＥＴで表層に形成される。そのために、Ｓｉ基板２０は、単結晶シリコン基板（Ｓｉ−ｓｕｂ）を材料とすることが好ましく、例えばｐ型Ｓｉ基板であってもよい。図１および図２に示すように、Ｓｉ基板２１，２２は、表層の活性層（Ｓｉ）の下に、埋込み酸化膜であるＢＯＸ（Buried Oxide）層（図中「ＢＯＸ」）が形成されている。さらに、Ｓｉ基板２１には、表層の活性層に形成されたｎ+拡散層（図中「ｎ+」）からなるソースおよびドレイン、ならびに、ソースとドレインの間のボディ（図中「ｐ」）上に表面の薄い酸化膜を挟んで成膜されたｐｏｌｙ−Ｓｉ膜からなるゲート２ｇにより、ＮＭＯＳが半導体素子構造２として形成されている。一方、Ｓｉ基板２２には、表層の活性層に形成されたｐ+拡散層（図中「ｐ+」）からなるソースおよびドレイン、ならびに、ボディ（図中「ｎ」）上のゲート２ｇからなるＰＭＯＳが半導体素子構造２として形成されている。また、Ｓｉ基板２１，２２は、活性層のＭＯＳＦＥＴを形成される領域（アクティブ領域）外がＳｉＯ2で分離されている（図中、空白で表す）。 (Si substrate)
The Si substrate 20 is a base on which the semiconductor element structure 2 is provided, and in the present embodiment, in particular, the semiconductor element structure 2 is formed on the surface of the SOI MOSFET. Therefore, the Si substrate 20 is preferably made of a single crystal silicon substrate (Si-sub), and may be, for example, a p-type Si substrate. As shown in FIGS. 1 and 2, the Si substrates 21 and 22 have a BOX (Buried Oxide) layer ("BOX" in the figure), which is a buried oxide film, formed under the active layer (Si) of the surface layer. There is. Furthermore, in the Si substrate 21, a source and a drain made of an n + diffusion layer (“n + ” in the figure) formed in the active layer of the surface layer, and a body between the source and the drain (“p” in the figure) An NMOS is formed as a semiconductor element structure 2 by a gate 2g made of a poly-Si film formed on the upper side with a thin oxide film on the surface. On the other hand, the Si substrate 22 comprises a source and a drain made of ap + diffusion layer ("p + " in the figure) formed in the active layer of the surface layer, and a gate 2g on the body ("n" in the figure) The PMOS is formed as the semiconductor element structure 2. In addition, the Si substrates 21 and 22 are separated by SiO 2 outside the region (active region) in which the MOSFET of the active layer is formed (represented by a blank in the figure).

（配線）
配線３は、半導体素子構造２の端子（ソース、ドレイン、ゲート）に接続するコンタクト部３ｃ、ならびにコンタクト部３ｃ上に接続する、１枚の半導体素子基板１に形成されたコンタクト部３ｃ同士を接続する配線部３ｉ（３ｉ1，３ｉ2）およびビア３ｖ、ならびにさらにその上に形成される接合電極７に接続するパッド部３ｐを備える。パッド部３ｐは、平面視で、接合電極７よりも大きく、全周にわたって外側に張り出すような形状に形成される。また、パッド部３ｐの上面が、接合電極７の上面の所定の表面粗さに対応して平滑に形成されている。 (wiring)
The wiring 3 connects the contact portions 3c connected to the terminals (source, drain, gate) of the semiconductor element structure 2, and the contact portions 3c formed on one semiconductor element substrate 1 connected on the contact portions 3c. wiring portion 3i of (3i 1, 3i 2) and vias 3 v, and further comprising a pad portion 3p to be connected to the bonding electrode 7 formed thereon. The pad portion 3 p is larger than the bonding electrode 7 in a plan view, and is formed in a shape projecting outward over the entire circumference. Further, the upper surface of the pad portion 3 p is formed to be smooth corresponding to the predetermined surface roughness of the upper surface of the bonding electrode 7.

配線３は、Ｃｕ，Ａｌ，Ｔａ，Ｃｒ，Ｗ，Ａｇ，Ａｕ，Ｐｔ，Ｐｄ等の金属やその合金のような一般的な金属電極材料で形成され、これらの材料から要求される導電性等に応じて選択され、また、層等によって異なる材料を適用されてもよい。さらに配線３は、前記材料および絶縁層４の材料によっては必要に応じて、絶縁層４への金属の拡散を防止するためのバリア膜（バリアメタル膜）を被覆する。本実施形態において、配線３は、少なくとも配線部３ｉ2およびパッド部３ｐが、ＣｕまたはＣｕ合金（以下、まとめてＣｕ）からなるコア部３２と、その底面（下面）および側面を被覆するバリア膜３１とを備え、上面はコア部３２が露出している。バリア膜３１は、コア部３２からＣｕをＳｉＯ2からなる絶縁層４へ拡散させないために設けられる。バリア膜３１は、Ｔａ，ＴａＮ，Ｔｉ，ＴｉＮ，ＴｉＷ等が適用され、さらにこれらの金属膜を２種類以上積層した多層膜としてもよく、また、コア部３２の側にＲｕ膜を積層した、例えばＲｕ／Ｔｉの２層膜としてもよい。バリア膜３１は、主に最薄となり易い側面において、Ｃｕの拡散を防止することのできる膜厚に形成され、材料にもよるが、少なくとも数〜十数ｎｍ程度とすることが好ましい。バリア膜３１は一方、膜厚が厚いと低抵抗のコア部３２の占める割合が低下し、配線３の導電性が低下するので、不要に厚くないことが好ましい。 The wiring 3 is formed of a general metal electrode material such as a metal such as Cu, Al, Ta, Cr, W, Ag, Au, Pt, Pd, etc. or an alloy thereof, and the conductivity etc required of these materials Depending on the layer, different materials may be applied depending on the layer or the like. Furthermore, the wiring 3 covers a barrier film (barrier metal film) for preventing metal diffusion to the insulating layer 4 as necessary depending on the material and the material of the insulating layer 4. In the present embodiment, at least the wiring portion 3i 2 and the pad portion 3p of the wiring 3 cover the core portion 32 made of Cu or Cu alloy (hereinafter collectively referred to as Cu), and the barrier film covering the bottom surface (lower surface) and side surfaces. And the core portion 32 is exposed on the top surface. The barrier film 31 is provided in order not to diffuse Cu from the core portion 32 to the insulating layer 4 made of SiO 2 . The barrier film 31 may be made of Ta, TaN, Ti, TiN, TiW or the like, and may be a multilayer film in which two or more of these metal films are stacked, and a Ru film is stacked on the core portion 32 side. For example, a Ru / Ti two-layer film may be used. The barrier film 31 is formed to a film thickness that can prevent the diffusion of Cu mainly on the side surface that tends to be the thinnest, and although depending on the material, it is preferable to set it to at least several to several tens nm. On the other hand, the barrier film 31 is preferably not unnecessarily thick because the ratio occupied by the low resistance core portion 32 decreases when the film thickness is large, and the conductivity of the wiring 3 decreases.

（接合電極）
接合電極７は、配線３のパッド部３ｐの上面に接触して接続し、半導体素子基板１の表面（上面）に露出する柱状の電極で、別の半導体素子基板１の接合電極７と接合するために設けられる。接合電極７は、金属電極材料の中でも導電性に優れ、ハイブリッド接合における接合方法に好適なＣｕまたはＣｕ合金（以下、まとめてＣｕ）で形成されたプラグ７２からなる。接合電極７は、形状が円柱や角柱等で、平面視形状は特に規定されず、別の半導体素子基板１の接合電極７と接合された際に、位置ずれ込みで必要な導通が確保される形状および寸法に設計される。また、接合電極７は、後記の絶縁層６１と同様に、ハイブリッド接合における接合方法に好適な平滑な表面（上面）であることが好ましい。さらに、接合電極７は、表面の高さ位置が絶縁層６１と一致、または絶縁層６１の表面から僅かに突出するように、厚さ（高さ）ＨPLGを、拡散防止絶縁膜５と絶縁層６１の合計の厚さＨと共に設計し、絶縁層６１の表面からの接合電極７の突出高さΔＨPLGが、ΔＨPLG＝ＨPLG−Ｈとなるので、ＨPLG≧Ｈとする。接合電極７を突出させる場合には、接合方法にもよるが、ΔＨPLG＝５〜１０ｎｍの範囲とすることが好ましい。半導体素子基板１においてはさらに、接合電極７は、側面で支持されていない部分での高さ（厚さ）（ＨPLG−(Ｈ−Ｄ)）についてアスペクト比が高過ぎないことが好ましく、径（幅）Ｗにもよるが、アスペクト比１以下であることが好ましい（(ＨPLG−Ｈ＋Ｄ)／Ｗ≦１）。半導体素子基板１において、接合電極７は、側面で絶縁層６１等の他の部材に支持されていないので、アスペクト比が高いと倒れる等の不良を生じる虞があるからである。なお、接合電極７は、配線３との密着性をよくするために、Ｒｕ等の金属膜からなる厚さ１〜１０ｎｍの下地膜を設けてもよい（図示せず）。 (Junction electrode)
The junction electrode 7 is in contact with and connected to the upper surface of the pad portion 3 p of the wiring 3, and is a columnar electrode exposed on the surface (upper surface) of the semiconductor element substrate 1 and joined to the junction electrode 7 of another semiconductor element substrate 1. Provided for The bonding electrode 7 is composed of a plug 72 which is excellent in conductivity among metal electrode materials and is formed of Cu or a Cu alloy (hereinafter collectively referred to as Cu) suitable for a bonding method in hybrid bonding. The shape of the bonding electrode 7 is a cylinder, a prism or the like, and the shape in plan view is not particularly defined. When bonding to the bonding electrode 7 of another semiconductor element substrate 1, a shape that ensures necessary conduction by misalignment. And designed to dimensions. Further, like the insulating layer 61 described later, the bonding electrode 7 is preferably a smooth surface (upper surface) suitable for the bonding method in the hybrid bonding. Further, the bonding electrode 7 has a thickness (height) H PLG so that the height position of the surface coincides with the insulating layer 61 or slightly protrudes from the surface of the insulating layer 61, and the insulating film 5 with the diffusion prevention insulating film Since the protrusion height ΔH PLG of the junction electrode 7 from the surface of the insulating layer 61 is ΔH PLG = H PLG −H, the design is made along with the total thickness H of the layer 61, so that H PLG HH. In the case where the bonding electrode 7 is made to protrude, although depending on the bonding method, it is preferable to set ΔH PLG = 5 to 10 nm. Furthermore, in the semiconductor element substrate 1, the junction electrode 7 preferably has an aspect ratio not too high for the height (thickness) (H PLG − (H−D)) of the portion not supported by the side surface, and the diameter (Width) Although it depends on W, an aspect ratio of 1 or less is preferable ((H PLG -H + D) / W ≦ 1). In the semiconductor element substrate 1, the bonding electrode 7 is not supported by another member such as the insulating layer 61 at the side surface, so that there is a possibility that a defect such as falling occurs if the aspect ratio is high. The bonding electrode 7 may be provided with a base film having a thickness of 1 to 10 nm made of a metal film such as Ru (not shown) in order to improve adhesion to the wiring 3.

（絶縁層）
絶縁層４は、Ｓｉ基板２０上を被覆して、半導体素子構造２や配線３，３間を互いに絶縁するために設けられる。絶縁層４は、例えばＳｉＯ2，Ａｌ2Ｏ3，ＭｇＯ等の酸化膜や、Ｓｉ窒化物（Ｓｉ3Ｎ4等、適宜ＳｉＮと表す）、ＳｉＣ（シリコンカーバイド）、ＳｉＯＣ（炭素添加シリコン酸化物）、ＳｉＣＮ（窒素添加シリコンカーバイド）、ＳｉＯＮ（窒素添加シリコン酸化物）、ＳｉＣＯ（ＳｉＣが基の低酸化物）のようなＳｉ化合物、ＭｇＦ2等の、半導体素子において公知の絶縁材料を適用することができ、これらの材料から要求される絶縁性等に応じて選択される。ＳｉＯ2には、ＢＰＳＧ（Boron Phosphorus Silicon Glass）、ＰＳＧ（Phosphorus Silicon Glass）、Ｆ（フッ素）をドープしたもの、多孔質ＳｉＯ2等も含まれる。絶縁層４は、単一の材料でなくてよく、層や領域によって異なる絶縁材料で形成されてもよい。特に、配線３をダマシン法で形成する等、表面を平坦化する場合には、ＣＭＰ法に対応したＳｉＯ2等を少なくとも最上層（キャップ層）に設ける。 (Insulating layer)
The insulating layer 4 is provided to cover the Si substrate 20 and insulate the semiconductor element structure 2 and the wires 3 from each other. The insulating layer 4 is, for example, an oxide film such as SiO 2 , Al 2 O 3 or MgO, Si nitride (Si 3 N 4 or the like, suitably referred to as SiN), SiC (silicon carbide), SiOC (carbon-doped silicon oxide) Known insulating materials in semiconductor devices, such as Si compounds such as SiCN (nitrogen-doped silicon carbide), SiON (nitrogen-doped silicon oxide), SiCO (low oxide based on SiC), MgF 2, etc. It can be selected according to the insulation required from these materials. Examples of SiO 2 include BPSG (Boron Phosphorus Silicon Glass), PSG (Phosphorus Silicon Glass), one doped with F (fluorine), porous SiO 2 and the like. The insulating layer 4 may not be a single material, and may be formed of different insulating materials depending on layers or regions. In particular, when the surface is flattened, for example, by forming the wiring 3 by a damascene method, SiO 2 or the like corresponding to the CMP method is provided at least in the uppermost layer (cap layer).

拡散防止絶縁膜５は、配線３の上面に露出したコア部３２からＣｕを最上層の絶縁層６１へ拡散させないために、絶縁層６１の下に設けられる。また、拡散防止絶縁膜５は、製造時に、絶縁層６１に対するエッチングストッパ膜になる。そのために、拡散防止絶縁膜５は、Ｃｕのバリア効果を有し、また、絶縁層６１を構成する絶縁材料（例えばＳｉＯ2）のエッチング選択比を高くする絶縁材料から選択され、具体的には、ＳｉＮ，ＳｉＣ，ＳｉＣＮ，ＳｉＣＯ等が適用される。拡散防止絶縁膜５は、Ｃｕの拡散を防止することのできる膜厚に形成され、材料にもよるが、少なくとも１０〜数十ｎｍ程度の厚さとすることが好ましい。 The diffusion preventing insulating film 5 is provided under the insulating layer 61 in order not to diffuse Cu from the core portion 32 exposed on the upper surface of the wiring 3 to the insulating layer 61 of the uppermost layer. Further, the diffusion preventing insulating film 5 serves as an etching stopper film for the insulating layer 61 at the time of manufacture. Therefore, the diffusion preventing insulating film 5 is selected from insulating materials which have a barrier effect of Cu and increase the etching selectivity of the insulating material (for example, SiO 2 ) constituting the insulating layer 61, specifically, SiN, SiC, SiCN, SiCO, etc. are applied. The diffusion preventing insulating film 5 is formed to a film thickness capable of preventing the diffusion of Cu, and although depending on the material, the thickness is preferably at least about 10 to several tens of nm.

半導体素子基板１は、ハイブリッド接合に好適となるように表面が平滑であり、接合方法にもよるが、具体的には、算術平均粗さＲａが１ｎｍ以下であることが好ましい。そのために、半導体素子基板１の最上層を構成する絶縁層６１は、ＣＭＰ法等で表面を平滑に加工し易い絶縁材料を適用し、このような材料としてＳｉＯ2，ＳｉＯＣ等の、Ｓｉ酸化物またはこれを基とするＳｉ化合物で形成され、厚さが１μｍ程度以上であることが好ましい。 The surface of the semiconductor element substrate 1 is smooth so as to be suitable for hybrid bonding, and although depending on the bonding method, specifically, the arithmetic average roughness Ra is preferably 1 nm or less. For this purpose, the insulating layer 61 constituting the uppermost layer of the semiconductor element substrate 1 uses an insulating material which can be easily processed to a smooth surface by a CMP method or the like, and Si oxide such as SiO 2 or SiOC as such a material Alternatively, it is preferably formed of a Si compound based thereon, and the thickness is preferably about 1 μm or more.

絶縁層６１は、接合電極７と接触しないように、接合電極７を上下に貫通させる、接合電極７の径（幅）Ｗよりも大きな孔が形成されている。絶縁層６１のこのような孔により、半導体素子基板１は、平面視で接合電極７を囲む、開口幅（外径）（Ｗ＋２Ｇ）、深さＤの凹み８を表面に形成される。凹み８は、深さＤが絶縁層６１の厚さと一致し、絶縁層６１に形成された孔の内面と接合電極７の側面とを外側と内側の側面とし、拡散防止絶縁膜５の上面を底面として構成される。本実施形態において、絶縁層６１は、上方へ広がって開口するように、断面視で接合電極７の側面に略１／４円弧（楕円弧を含む）を描く形状の孔が形成され、表面で幅（径）（Ｗ＋２Ｇ）開口し、下面で幅（Ｗ＋２ＧB）開口する孔が形成されている。絶縁層６１は、接合電極７に完全に非接触となるように、下面（凹み８の底面）において最小となる間隙ＧB（＜Ｇ）がＧB＞０に設計される（Ｇ＞ＧB＞０）。間隙ＧBは、０超であれば特に規定されないが、１０ｎｍ以上に設計されることが好ましい。凹み８を構成する絶縁層６１のこのような形状の孔は、後記製造方法にて説明するように、ウェットエッチング等の等方性エッチングで成形される。等方性エッチングは、深さ（厚さ）方向と共に面内方向にもエッチングが進行するエッチングであり、面内方向のエッチング（サイドエッチング）量に対する厚さ方向の比（エッチングファクター）ｘが比較的１に近い。絶縁層６１の等方性エッチングは、径Ｗの領域を空けたマスクを用いるため、Ｇ＞Ｄ／ｘとなり、また、ＧB≒√[Ｇ2−(Ｄ／ｘ)2]となる。 The insulating layer 61 is formed with a hole larger than the diameter (width) W of the bonding electrode 7 that vertically penetrates the bonding electrode 7 so as not to be in contact with the bonding electrode 7. With such a hole of the insulating layer 61, the semiconductor element substrate 1 is formed on the surface with a recess 8 having an opening width (outer diameter) (W + 2G) and a depth D surrounding the bonding electrode 7 in plan view. The depth D of the recess 8 matches the thickness of the insulating layer 61, and the inner surface of the hole formed in the insulating layer 61 and the side surface of the bonding electrode 7 are the outer and inner side surfaces, and the upper surface of the diffusion preventing insulating film 5 is It is configured as the bottom. In the present embodiment, the insulating layer 61 is formed with a hole having a shape that draws a substantially 1⁄4 arc (including an elliptic arc) on the side surface of the bonding electrode 7 in cross section so that the insulating layer 61 opens upward. A (diameter) (W + 2 G) opening is formed, and a hole (width + (2 + 2 G B )) opening is formed on the lower surface. In the insulating layer 61, the gap G B (<G) which is the smallest at the lower surface (bottom surface of the recess 8) is designed to be G B > 0 so that the bonding electrode 7 is completely not in contact (G> G B > 0). Gap G B is not particularly limited as long as greater than zero, it is preferably designed more than 10 nm. The hole of such a shape of the insulating layer 61 which constitutes the recess 8 is formed by isotropic etching such as wet etching as described later in the manufacturing method. Isotropic etching is etching in which etching proceeds in the in-plane direction as well as in the depth (thickness) direction, and the ratio (etching factor) x in the thickness direction to the amount of etching (side etching) in the in-plane direction is compared. Close to one. In the isotropic etching of the insulating layer 61, G> D / x is obtained because a mask having a region of a diameter W is used, and G B √ {square root over (G 2 )-(D / x) 2 ].

半導体素子基板１は、接合電極７の周囲に絶縁層６１のない凹み８を表面に形成されていることにより、絶縁層６１が、接合電極７に接触せず、かつ位置ずれを有して接合される別の半導体素子基板１の接合電極７に接触することがない。そのために、凹み８による絶縁層６１と接合電極７との間隙は、絶縁層６１の表面から少なくとも深さΔＨPLGまでの範囲において、接合型半導体素子１０の接合における位置ずれの許容される最大値ｓMAX超となるように、√[Ｇ2−(ΔＨPLG／ｘ)2]＞ｓMAXに設計される。このマージン（√[Ｇ2−(ΔＨPLG／ｘ)2]−ｓMAX（≒Ｇ−ｓMAX））は、０超であれば特に規定されないが、接合時の接合電極７の変形等を加味して、２０ｎｍ以上に設計されることが好ましく、５０ｎｍ以上に設計されることがより好ましい。位置ずれの最大値ｓMAXは、接合した接合電極７，７同士で必要な導通が確保される範囲に設定され、例えば、接合電極７が円柱で、接合面積が約１／２となる、径Ｗの０．４倍とする（ｓMAX＝０．４Ｗ）。この場合、前記したように絶縁層６１の表面からの接合電極７の突出高さΔＨPLGが十分に小さい（ΔＨPLG≦１０ｎｍ）ので、Ｗ＝１μｍとして、マージンに１００ｎｍを含めてＧ≧０．５Ｗに設定することができる。 The semiconductor element substrate 1 is formed by forming the recess 8 without the insulating layer 61 around the bonding electrode 7 on the surface, so that the insulating layer 61 does not contact the bonding electrode 7 and bonding is performed with positional deviation. It does not contact the bonding electrode 7 of another semiconductor element substrate 1. Therefore, the gap between the insulating layer 61 and the junction electrode 7 due to the recess 8 is at the maximum value of the misalignment of the junction of the junction-type semiconductor device 10 in the range from the surface of the insulating layer 61 to at least the depth ΔH PLG. s MAX so that greater, √ - is designed to [G 2 (ΔH PLG / x ) 2]> s MAX. This margin (√ [G 2 − (ΔH PLG / x) 2 ] −s MAX (≒ G−s MAX )) is not particularly defined as long as it is more than 0, but the deformation of bonding electrode 7 at bonding is added Preferably, it is designed to be 20 nm or more, more preferably 50 nm or more. The maximum value s MAX of the positional deviation is set to a range in which the required continuity is secured between the joined junction electrodes 7, 7, for example, a diameter such that the junction area is approximately 1⁄2 when the junction electrode 7 is a cylinder It is 0.4 times W (s MAX = 0.4 W). In this case, as described above, since the protrusion height ΔH PLG of the junction electrode 7 from the surface of the insulating layer 61 is sufficiently small (ΔH PLG ≦ 10 nm), G00 including 100 nm in the margin with W = 1 μm. It can be set to 5 W.

絶縁層６１の表面での接合電極７との間隙Ｇの上限（開口幅（Ｗ＋２Ｇ）の上限）は特に規定されないが、絶縁層６１の孔（凹み８）が接合電極７の径Ｗに対してより広く開口していると、接合型半導体素子１０の接合面積が減少し、接合強度が低下して、接合面で剥離する虞が生じる。具体的には、接合の位置ずれがない（ｓ＝０）場合において、半導体素子基板１の全体の面積の１／２以上で接合されていることが好ましい。すなわち、非接合面積である、すべての凹み８の開口面積の合計が、半導体素子基板１の面積Ａの１／２以下となるように設計されることが好ましい。例えば、半導体素子基板１の接合電極７がＮ個ですべて同一の寸法の底面の面積ＳPLGの柱体であるとすれば、凹み８もＮ個で同一の開口面積ＳPOCKであるから、非接合面積は（Ｎ×(ＳPOCK−ＳPLG)）となる。また、接合の位置ずれがない場合において、絶縁層６１のみの接合面積（Ａ−Ｎ×ＳPOCK）が非接合面積（Ｎ×(ＳPOCK−ＳPLG)）以上となることがより好ましく、位置ずれが最大値ｓMAXにおいても同様の関係となることがさらに好ましい。前記したように、Ｇ＞Ｄ／ｘであるから、絶縁層６１が過剰に厚いと、凹み８の深さＤと共に間隙Ｇが不要に大きくなって、接合型半導体素子１０の接合面積が確保できない。 The upper limit (upper limit of the opening width (W + 2 G)) of the gap G with the bonding electrode 7 on the surface of the insulating layer 61 is not particularly specified, but the hole (recess 8) of the insulating layer 61 is relative to the diameter W of the bonding electrode 7 If the opening is wider, the bonding area of the junction-type semiconductor device 10 is reduced, the bonding strength is reduced, and there is a possibility that the bonding surface may be peeled off. Specifically, in the case where there is no positional displacement of the junction (s = 0), it is preferable that the junction be performed at 1/2 or more of the entire area of the semiconductor element substrate 1. That is, it is preferable to design so that the sum of the opening area of all the dents 8 which is a non-junction area is 1/2 or less of the area A of the semiconductor element substrate 1. For example, assuming that N bonding electrodes 7 of the semiconductor element substrate 1 are pillars of the area S PLG of the bottom surface of the same dimension, since the recesses 8 are also the same opening area S POCK of N, The junction area is (N × (S POCK −S PLG )). Further, it is more preferable that the bonding area (A-N × S POCK ) of only the insulating layer 61 be equal to or more than the non-bonding area (N × (S POCK −S PLG )) when there is no misalignment of bonding. It is further preferable that the deviation be in the same relation at the maximum value s MAX . As described above, since G> D / x, if the insulating layer 61 is excessively thick, the gap G becomes unnecessarily large together with the depth D of the recess 8, and the junction area of the junction-type semiconductor device 10 can not be secured. .

また、間隙Ｇが過剰に大きい、すなわち接合電極７の径Ｗに対して著しく大きく開口した孔を絶縁層６１に形成しようとすると、半導体素子基板１の後記する製造方法において、絶縁層６１のウェットエッチングによるエッチング量が多くなる。その結果、エッチャント（エッチング液）が絶縁層６１とその上のマスク（レジストマスク）の界面に浸入して、孔の周囲で表面が不要にエッチングされて浅く凹む虞がある。また、隣り合う接合電極７，７のピッチが狭い場合に、絶縁層６１のウェットエッチングにおいて、絶縁層６１の、接合電極７，７のそれぞれの周囲の孔同士がエッチング中に連結して、この部分で回り込んだエッチャントによってさらに深くエッチングが進行するため、凹み８が一部の接合電極７において異なった形状となる。   If it is attempted to form in the insulating layer 61 a hole having an excessively large gap G, that is, an opening that is extremely large with respect to the diameter W of the bonding electrode 7, the insulating layer 61 is wetted in the manufacturing method described later. The etching amount by etching increases. As a result, an etchant (etching solution) may intrude into the interface between the insulating layer 61 and the mask (resist mask) thereon, and the surface may be unnecessarily etched around the hole to be shallowly recessed. In addition, when the pitch of the adjacent bonding electrodes 7 is narrow, holes in the periphery of the bonding electrodes 7 of the insulating layer 61 are connected during etching in the wet etching of the insulating layer 61. Since the etching progresses deeper by the etchant that wraps around at a portion, the recess 8 has a different shape in some of the bonding electrodes 7.

なお、表面同士で接合されて一つの接合型半導体素子１０を構成する半導体素子基板１１，１２は、前記したように、平面視で、互いに接合電極７が左右対称に配置されていればよく、接合電極７の配置を除いたその他の構造は前記の範囲内であれば一致していなくてもよい。例えば表面の凹み８の表面における間隙Ｇは、それぞれが位置ずれの最大値ｓMAXよりも大きければよく、したがって、凹み８の深さＤ（絶縁層６１の厚さ）や接合電極７の厚さＨPLGおよび突出高さΔＨPLGも異なっていてよい。 Incidentally, as described above, in the semiconductor element substrates 11 and 12 which are joined to each other to constitute one junction type semiconductor element 10, the junction electrodes 7 may be arranged symmetrically in plan view as described above, The other structures excluding the arrangement of the bonding electrode 7 may not be identical within the above range. For example, the gap G on the surface of the recess 8 on the surface may be larger than the maximum value s MAX of the misalignment, so the depth D of the recess 8 (the thickness of the insulating layer 61) and the thickness of the bonding electrode 7 H PLG and protrusion height ΔH PLG may also be different.

〔接合型半導体素子の製造方法〕
本発明の第１実施形態に係る接合型半導体素子および半導体素子基板の製造方法について、図４〜図７を参照して説明する。なお、図６においては、加工前の膜についても加工後の要素と同じ符号を付して表す。本実施形態に係る接合型半導体素子１０は、２枚の半導体素子基板１（１１，１２）を製造する半導体素子製造工程Ｓ１、およびこれらを表面（上面）同士で接合する接合工程Ｓ２を行って得られる。半導体素子製造工程Ｓ１は、Ｓｉ基板２０上に、半導体素子構造２とこれに接続する配線３、および絶縁層４を形成する半導体素子・配線形成工程Ｓ１０と、表面を被覆する絶縁層６１と表面に露出する接合電極７を形成する接合部形成工程Ｓ２０と、を行う。 [Method of manufacturing junction type semiconductor device]
A method of manufacturing the junction-type semiconductor device and the semiconductor device substrate according to the first embodiment of the present invention will be described with reference to FIGS. 4 to 7. In FIG. 6, the film before processing is represented by the same reference numeral as the element after processing. In the junction-type semiconductor device 10 according to the present embodiment, a semiconductor device manufacturing process S1 of manufacturing two semiconductor device substrates 1 (11, 12) and a bonding process S2 of bonding these on the surface (upper surface) are performed. can get. In the semiconductor element manufacturing step S1, a semiconductor element structure 2 and a wiring 3 connected to the semiconductor element structure 2 on the Si substrate 20, and a semiconductor element / wiring forming step S10 for forming an insulating layer 4; And a bonding portion forming step S20 of forming the bonding electrode 7 exposed to the surface.

〔半導体素子基板の製造方法〕
半導体素子・配線形成工程Ｓ１０は、Ｓｉ基板２０の表層に半導体素子構造２を形成する半導体素子形成工程Ｓ１１と、配線３および絶縁層４を形成する配線形成工程Ｓ１２と、を行い、それぞれ公知の方法を適用することができ、以下にその一例を示す。 [Method of Manufacturing Semiconductor Device Substrate]
The semiconductor element / wiring formation step S10 includes a semiconductor element formation step S11 for forming the semiconductor element structure 2 on the surface of the Si substrate 20 and a wiring formation step S12 for forming the wiring 3 and the insulating layer 4. The method can be applied, an example of which is given below.

（半導体素子形成工程）
Ｓｉ基板に、酸素イオンを注入して所定の深さ位置にＢＯＸ層を形成し、その上（表層）を活性層とする。次に、活性層のアクティブ領域とする領域外にＳｉＯ2を埋め込む（素子分離）。また、活性層に、必要に応じて、ＰＭＯＳを形成する領域にｎ型不純物イオンを、ＮＭＯＳを形成する領域にｐ型不純物イオンを、それぞれ注入する（チャネルドープ）。そして、表面に薄い酸化膜（ＳｉＯ2膜）を形成し、その上にｐｏｌｙ−Ｓｉ膜でゲートを形成する。ｎ型不純物イオンを注入してｎ+拡散層を形成し、ｐ型不純物イオンを注入してｐ+拡散層を形成して、半導体素子構造２（ＮＭＯＳ，ＰＭＯＳ）を形成したＳｉ基板２１，２２とする。 (Semiconductor element formation process)
Oxygen ions are implanted into the Si substrate to form a BOX layer at a predetermined depth position, and the upper layer (surface layer) is used as an active layer. Next, SiO 2 is embedded outside the region to be the active region of the active layer (element isolation). In addition, n-type impurity ions are implanted into the active layer, and p-type impurity ions are implanted into the region forming the NMOS (channel doping), respectively, as necessary. Then, a thin oxide film (SiO 2 film) is formed on the surface, and a poly-Si film is formed thereon. Si substrates 21 and 22 having semiconductor element structure 2 (NMOS, PMOS) formed by implanting n-type impurity ions to form an n + diffusion layer and implanting p-type impurity ions to form ap + diffusion layer I assume.

（配線形成工程）
Ｓｉ基板２０（２１，２２）上に絶縁層４の下層部分を構成する絶縁膜を成膜し、この絶縁膜をエッチングして、ｎ+拡散層、ｐ+拡散層、およびゲート（ｐｏｌｙ−Ｓｉ膜）のそれぞれの上における箇所にホール（孔）を形成する。Ｗ等の金属電極材料を成膜して、絶縁層４のホールに埋め込んで、コンタクト部３ｃを形成する。この上にさらに絶縁層４の中間層部分を構成する絶縁膜を成膜し、コンタクト部３ｃの形成と同様に、配線部３ｉ1を、その形状のトレンチ（溝）を形成して金属電極材料を埋め込んで形成する。さらに絶縁層４の最上層部分を構成する絶縁膜を成膜し、ビア３ｖ、配線部３ｉ2およびパッド部３ｐを、同様に形成する。また、Ｃｕめっき膜からなるコア部３２とこれを被覆するバリア膜３１とを設けるためには、ダマシン法で形成することができる。絶縁膜に形成したホール、トレンチ内にバリア膜３１をスパッタ法等で成膜し、引き続いて、コア部３２の一部となるシード層をバリア膜３１上にスパッタ法等で成膜してから、残部をめっきで埋め込む。その後、ＣＭＰ法により、表面の金属膜を研削して絶縁層４を露出させて平坦化する。平坦化の際に、露出させたパッド部３ｐの表面を平滑化することが好ましい。これにより、Ｓｉ基板２０上に、図６（ａ）に示すように、絶縁層４が被覆され、その表面にパッド部３ｐのコア部３２が露出した配線３が形成される。なお、３層以上の多層配線構造を形成する場合には、さらに絶縁膜を成膜して、この絶縁膜に配線部３ｉ上のホールおよびその上のトレンチを形成して金属電極材料を埋め込むという一連の工程を繰り返す。 (Wiring formation process)
An insulating film forming the lower layer portion of the insulating layer 4 is formed on the Si substrate 20 (21, 22), and the insulating film is etched to form an n + diffusion layer, a p + diffusion layer, and a gate (poly-Si Form a hole at a point on each of the membranes). A metal electrode material such as W is deposited and buried in the hole of the insulating layer 4 to form the contact portion 3c. An insulating film constituting an intermediate layer portion of the insulating layer 4 is further formed thereon, and, similarly to the formation of the contact portion 3c, the wiring portion 3i 1 is formed into a trench (groove) of the shape to form a metal electrode material. Embed to form. Further, an insulating film constituting the uppermost layer portion of the insulating layer 4 is formed, and the via 3v, the wiring portion 3i 2 and the pad portion 3p are similarly formed. The core portion 32 made of a Cu plating film and the barrier film 31 covering the core portion 32 can be formed by a damascene method. A barrier film 31 is formed by sputtering or the like in a hole or trench formed in an insulating film, and subsequently, a seed layer to be a part of the core portion 32 is formed by sputtering on the barrier film 31. Embed the remaining part by plating. Thereafter, the metal film on the surface is ground by CMP method to expose and planarize the insulating layer 4. At the time of planarization, it is preferable to smooth the surface of the exposed pad portion 3p. As a result, as shown in FIG. 6A, the insulating layer 4 is covered on the Si substrate 20, and the wiring 3 in which the core portion 32 of the pad portion 3p is exposed is formed on the surface. When a multilayer wiring structure of three or more layers is to be formed, an insulating film is further formed, and holes and upper trenches on the wiring portion 3i are formed in the insulating film to embed the metal electrode material. Repeat the series of steps.

接合部形成工程Ｓ２０は、拡散防止絶縁膜５を構成する絶縁膜を成膜する拡散防止絶縁膜成膜工程Ｓ２１と、絶縁層６１を構成する絶縁膜を成膜する絶縁膜成膜工程Ｓ２２と、絶縁膜の表面を研磨して平滑化する平滑化工程Ｓ２３と、接合電極７が形成される領域を空けたレジストマスクＰＲ１を形成するマスク工程Ｓ３３と、等方性エッチングで絶縁層６１を成形する絶縁膜等方性エッチング工程Ｓ２４と、エッチングで拡散防止絶縁膜５を成形する拡散防止絶縁膜エッチング工程Ｓ２６と、Ｃｕを成膜して接合電極７（プラグ７２）を形成する電極成膜工程Ｓ３４と、レジストマスクＰＲ１を除去するマスク除去工程（リフトオフ工程）Ｓ３５と、を行う。   The bonding portion forming step S20 includes a diffusion preventing insulating film forming step S21 of forming an insulating film forming the diffusion preventing insulating film 5, and an insulating film forming step S22 of forming an insulating film forming the insulating layer 61. Forming insulating layer 61 by isotropic etching and a smoothing step S23 for polishing and smoothing the surface of the insulating film, a mask step S33 for forming a resist mask PR1 with a region where junction electrode 7 is formed, and Insulating film isotropic etching step S24, diffusion preventing insulating film etching step S26 for forming the diffusion preventing insulating film 5 by etching, and electrode film forming step for forming the bonding electrode 7 (plug 72) by forming Cu. Step S34 and a mask removing step (lift-off step) S35 for removing the resist mask PR1 are performed.

（絶縁膜成膜工程、平滑化工程、マスク工程）
配線３および絶縁層４を形成したＳｉ基板２０上に、拡散防止絶縁膜５を構成するＳｉＮ膜を厚さ（Ｈ−Ｄ）に成膜し（Ｓ２１）、引き続いて、絶縁層６１を構成するＳｉＯ2膜を厚さＤ超に成膜する（Ｓ２２）。次に、このＳｉＯ2膜の表面をＣＭＰ法で研磨して厚さＤ（拡散防止絶縁膜５と絶縁層６１の合計厚さＨ）とし（図６（ｂ）参照）、かつ所定の表面粗さに平滑化する（Ｓ２３）。そして、表面を平滑化したＳｉＯ2膜上に、図６（ｂ）に示すように、接合電極７が形成される径Ｗの領域を空けたレジストマスクＰＲ１を形成する（Ｓ３３）。 (Insulating film deposition process, smoothing process, mask process)
On the Si substrate 20 on which the wiring 3 and the insulating layer 4 are formed, a SiN film constituting the diffusion preventing insulating film 5 is formed to a thickness (H-D) (S21), and subsequently, the insulating layer 61 is formed. A SiO 2 film is formed to a thickness D or more (S22). Next, the surface of this SiO 2 film is polished by CMP to obtain a thickness D (total thickness H of diffusion preventing insulating film 5 and insulating layer 61) (see FIG. 6 (b)) and a predetermined surface roughness. Smooth (S23). Then, as shown in FIG. 6B, a resist mask PR1 is formed on the SiO 2 film whose surface is smoothed, with an area of a diameter W where the bonding electrode 7 is formed (S33).

（絶縁膜等方性エッチング工程）
ＳｉＯ2膜に、等方性エッチングで、図６（ｃ）に示すように所定の寸法の貫通孔を開けて、絶縁層６１に成形する（Ｓ２４）。等方性エッチングは、深さ（厚さ）方向と共に面内方向にもエッチングが進行するエッチングであり、面内方向のエッチング（サイドエッチング）量に対する厚さ方向の比（エッチングファクター）ｘは特に規定されない。等方性エッチングは、拡散防止絶縁膜５を構成するＳｉＮに対して選択比の高いウェットエッチングを適用することが好ましく、ここでは絶縁層６１がＳｉＯ2からなるので、ＨＦ（フッ酸）溶液を使用する。あるいは、ドライエッチングであるガス・プラズマエッチングを適用することもできる。等方性エッチングにより、レジストマスクＰＲ１の空いた領域の直下に、絶縁層６１が、径（Ｗ＋２ＧB）の領域で完全に除去されてかつ表面（上）に広がって径（Ｗ＋２Ｇ）開口した孔を形成され、ＳｉＮ膜（拡散防止絶縁膜５）が露出する。すなわち、表面（レジストマスクＰＲ１の下）に、広がって開口した深さＤの穴が形成される。 (Insulating film isotropic etching process)
Through holes having predetermined dimensions are opened in the SiO 2 film by isotropic etching as shown in FIG. 6C, and the insulating layer 61 is formed (S24). Isotropic etching is etching in which etching proceeds in the in-plane direction as well as in the depth (thickness) direction, and the ratio (etching factor) x in the thickness direction to the amount of etching (side etching) in the in-plane direction is particularly important. Not specified The isotropic etching is preferably performed by wet etching having a high selection ratio to SiN constituting the diffusion preventing insulating film 5, and in this case, since the insulating layer 61 is made of SiO 2 , an HF (hydrofluoric acid) solution is used. use. Alternatively, gas plasma etching which is dry etching can be applied. A hole in which the insulating layer 61 is completely removed in the area of diameter (W + 2 G B ) and is spread on the surface (upper side) and the diameter (W + 2 G) is opened just under the open area of the resist mask PR 1 by isotropic etching. The SiN film (the diffusion preventing insulating film 5) is exposed. That is, on the surface (under the resist mask PR1), a hole having a spread and opened depth D is formed.

（拡散防止絶縁膜エッチング工程）
ＳｉＮ膜に、異方性エッチングで、図６（ｄ）に示すように径Ｗの貫通孔の空いた拡散防止絶縁膜５に成形する（Ｓ２６）。異方性エッチングは、拡散防止絶縁膜５を構成する絶縁材料に対応する公知の方法を適用することができ、さらに前記絶縁材料の下の配線３のパッド部３ｐ（コア部３２）を構成する金属電極材料に対する選択比の高いことが好ましく、例えば反応性イオンエッチング（ＲＩＥ）が挙げられる。パッド部３ｐをエッチングストッパ膜とすることにより、レジストマスクＰＲ１の空いた領域の直下の領域で、拡散防止絶縁膜５が完全に除去されて配線３（パッド部３ｐ）が露出し、平坦なエッチング面が得られる。 (Diffusion prevention insulating film etching process)
As shown in FIG. 6D, the SiN film is formed into the diffusion preventing insulating film 5 in which the through holes having the diameter W are opened as shown in FIG. 6D (S26). The anisotropic etching can apply the well-known method corresponding to the insulating material which comprises the diffusion prevention insulating film 5, and also comprises the pad part 3p (core part 32) of the wiring 3 under the said insulating material. A high selectivity to metal electrode materials is preferred, such as reactive ion etching (RIE). By using pad portion 3p as an etching stopper film, diffusion preventing insulating film 5 is completely removed in the region immediately below the vacant region of resist mask PR1, and wiring 3 (pad portion 3p) is exposed and flat etching is performed. A face is obtained.

（電極成膜工程、マスク除去工程）
Ｃｕを成膜して、図７に示すように、レジストマスクＰＲ１の空いた領域の直下で、パッド部３ｐ上に厚さＨPLGに堆積させて接合電極７（プラグ７２）を形成する（Ｓ３４）。Ｃｕの成膜方法は、Ｃｕが絶縁層６１の孔の側面に付着しないように、膜材料の直進性が高い方法を選択し、例えば真空蒸着法が適用される。その後、レジストマスクＰＲ１をその上のＣｕ膜ごと除去して（Ｓ３５）、半導体素子基板１が得られる。 (Electrode deposition process, mask removal process)
Cu is formed into a film, and as shown in FIG. 7, the bonding electrode 7 (plug 72) is formed on the pad portion 3p to a thickness H PLG immediately below the vacant region of the resist mask PR1 (S34) ). As a film forming method of Cu, a method in which the rectilinearity of the film material is high is selected so that Cu does not adhere to the side surface of the hole of the insulating layer 61. For example, a vacuum evaporation method is applied. Thereafter, the resist mask PR1 is removed together with the Cu film thereon (S35), and the semiconductor element substrate 1 is obtained.

このように、絶縁層６１を等方性エッチングで加工することにより、接合電極７を形成するためのレジストマスクＰＲ１で、接合電極７よりも大きな径の孔が絶縁層６１に形成され、接合電極７を囲う環状の凹み８を表面に形成された半導体素子基板１が得られる。また、同一のレジストマスクＰＲ１により、接合電極７と絶縁層６１の孔の位置関係がずれることなく、絶縁層６１と接合電極７との間隙が面方向において一定の距離となり、絶縁層６１が的確に接合電極７から離間して形成され、また、製造過程においても非接触である。また、絶縁層６１の下に拡散防止絶縁膜５を設けた２層構造とすることで、Ｃｕを備えた配線３上にＳｉＯ2からなる絶縁層６１を被覆することができる。さらにＳｉＯ2膜の等方性エッチングでＳｉＮ膜（拡散防止絶縁膜５）がエッチングストッパ膜となるので、絶縁層６１の表面の孔径（Ｗ＋２Ｇ）を接合電極７の径Ｗに対してより大きく、すなわち間隙Ｇを大きく設計しても、絶縁層６１の厚さＤを超えて深く穴が形成されることがない。 Thus, by processing the insulating layer 61 by isotropic etching, a hole having a diameter larger than that of the bonding electrode 7 is formed in the insulating layer 61 with the resist mask PR1 for forming the bonding electrode 7, and the bonding electrode A semiconductor element substrate 1 having an annular recess 8 surrounding 7 is formed on the surface. Further, the gap between the insulating layer 61 and the bonding electrode 7 becomes a fixed distance in the surface direction without shifting the positional relationship between the bonding electrode 7 and the hole of the insulating layer 61 by the same resist mask PR1, and the insulating layer 61 is accurate. It is formed separately from the bonding electrode 7 and is not in contact in the manufacturing process. Further, by providing the diffusion preventing insulating film 5 under the insulating layer 61, the insulating layer 61 made of SiO 2 can be covered on the wiring 3 provided with Cu. Further, since the SiN film (the diffusion preventing insulating film 5) becomes an etching stopper film by isotropic etching of the SiO 2 film, the hole diameter (W + 2G) of the surface of the insulating layer 61 is larger than the diameter W of the bonding electrode 7 That is, even if the gap G is designed to be large, a hole is not formed deep beyond the thickness D of the insulating layer 61.

接合部形成工程Ｓ２０の直前（半導体素子・配線形成工程Ｓ１０完了時）における表面が十分に平滑で、絶縁層６１の厚さＤが大きくなく、ＣＶＤ法等で十分に平滑な表面のＳｉＯ2膜を成膜することができる場合には、絶縁膜成膜工程Ｓ２２でＳｉＯ2膜を厚さＤに成膜して、平滑化工程Ｓ２３を行わなくてよい。 The surface is sufficiently smooth just before the junction formation step S20 (at the completion of the semiconductor element / wiring formation step S10), the thickness D of the insulating layer 61 is not large, and the SiO 2 film on the surface is sufficiently smooth by CVD method etc. If it is possible to form a film, the SiO 2 film may be formed to a thickness D in the insulating film forming step S22, and the smoothing step S23 may not be performed.

（接合工程）
２枚の半導体素子基板１（１１，１２）を接合装置に固定し、表面同士で接合して、接合型半導体素子１０とする。本実施形態に係る半導体素子基板１は、非酸化雰囲気で接合される。非酸化雰囲気とは、真空、またはＡｒ等の不活性ガス雰囲気であり、表面の凹み８の内側に露出する、接合電極７、拡散防止絶縁膜５および絶縁層６１の各材料に対して不活性とする。これにより、半導体素子基板１１，１２のそれぞれの表面の凹み８，８で形成される閉じた空間である空隙８０に、真空、またはＡｒ等の不活性ガスが封入される。また、半導体素子基板１の破損や半導体素子構造２等へのダメージを防止するために、比較的低温で、無加圧またはこれに近い低加圧で接合することが好ましい。このような接合方法として、半導体素子基板同士をハイブリッド接合する公知の方法を適用することができ、例えば表面活性化接合が挙げられる。常温または２００℃程度以下で、不活性ガス雰囲気にて、この不活性ガスのイオンやプラズマを半導体素子基板１１，１２の表面に照射することにより表面を活性化し、活性化した表面同士を接触させることにより接合される。 (Bonding process)
The two semiconductor element substrates 1 (11, 12) are fixed to a bonding apparatus, and the surfaces are bonded to each other to form a junction type semiconductor element 10. The semiconductor element substrate 1 according to the present embodiment is bonded in a non-oxidizing atmosphere. The non-oxidizing atmosphere is an inert gas atmosphere such as vacuum or Ar, and is inert to each material of the bonding electrode 7, the diffusion preventing insulating film 5 and the insulating layer 61 exposed inside the recess 8 on the surface. I assume. Thus, an inert gas such as vacuum or Ar is sealed in the air gap 80 which is a closed space formed by the recesses 8 and 8 on the surface of each of the semiconductor element substrates 11 and 12. Further, in order to prevent the damage of the semiconductor element substrate 1 and the damage to the semiconductor element structure 2 and the like, it is preferable to join at a relatively low temperature, no pressure or a low pressure close thereto. As such a bonding method, a known method of hybrid bonding semiconductor element substrates to each other can be applied, and for example, surface activation bonding can be mentioned. Surfaces are activated by irradiating the surfaces of the semiconductor element substrates 11 and 12 with ions or plasma of the inert gas in an inert gas atmosphere at normal temperature or about 200 ° C. or less, and the activated surfaces are brought into contact with each other. Are joined together.

半導体素子基板１１，１２を、接合する前に、必要に応じて裏面（Ｓｉ基板２０の裏面）を研削して（バックグラインド）薄肉化してもよく、さらに切断して個片化したチップとしてから接合することもできる。半導体素子基板１１，１２の一方のみを個片化してもよく、チップを他方のウェハに合わせて接合装置に配列して固定する。半導体素子基板１１，１２の少なくとも一方を個片化してから接合することにより、選別して良品同士を接合することができ、一方のみの不良による損失が低減される。   Before bonding the semiconductor element substrates 11 and 12, the back surface (the back surface of the Si substrate 20) may be ground (back grind) to thin as necessary, and then cut and separated into chips It can also be joined. Only one of the semiconductor element substrates 11 and 12 may be singulated, and the chips are aligned with the other wafer and arranged and fixed in a bonding apparatus. By separating at least one of the semiconductor element substrates 11 and 12 and then joining them, it is possible to select and join non-defective products, and the loss due to only one of the defects is reduced.

（変形例１）
第１実施形態においては、絶縁膜等方性エッチング工程Ｓ２４により、絶縁層６１を、接合電極７の径Ｗよりも一回り大きな径（Ｗ＋２ＧB）の領域で完全に除去する必要がある。そのため、半導体素子基板１は、接合電極７の厚さＨPLGが大きいと、それに伴い拡散防止絶縁膜５と絶縁層６１の合計の厚さＨも大きくなるので、凹み８の深さＤが深くなって、接合における位置ずれの最大値ｓMAXにかかわらず、間隙Ｇの長い広く開口した凹み８が表面に形成されることになる。その結果、特に接合電極７の数が多いと、接合面積が狭くなり、接合強度が低下する。そこで、接合電極７の厚さＨPLGが大きく、凹み８をこれに近い値の深さＤに設計すると間隙Ｇが不要に長くなる場合には、拡散防止絶縁膜５を厚膜化することにより、その分、絶縁層６１の厚さＤを小さくしてもよい。このような構造により、所望の間隙Ｇの凹み８を表面に形成することができる。また、拡散防止絶縁膜５の厚膜化により絶縁層６１の厚さＤを小さくすることで、接合電極７の側面で支持されていない部分での厚さ（ＨPLG−(Ｈ−Ｄ)）についてアスペクト比を低く抑えることができる。 (Modification 1)
In the first embodiment, an insulating film isotropic etching step S24, the insulating layer 61, it is necessary to completely remove the area of the large diameter slightly larger than the diameter W of the bonding electrodes 7 (W + 2G B). Therefore, in the semiconductor element substrate 1, when the thickness H PLG of the bonding electrode 7 is large, the total thickness H of the diffusion preventing insulating film 5 and the insulating layer 61 also becomes large accordingly, so the depth D of the recess 8 is deep. As a result, regardless of the maximum value s MAX of misalignment at the junction, a long, wide open recess 8 of the gap G will be formed on the surface. As a result, particularly when the number of bonding electrodes 7 is large, the bonding area becomes narrow and the bonding strength decreases. Therefore, when the thickness H PLG of the junction electrode 7 is large, and the gap G becomes unnecessarily long when the recess 8 is designed to have a depth D close to this, the diffusion preventing insulating film 5 is thickened. The thickness D of the insulating layer 61 may be reduced accordingly. With such a structure, the recess 8 of the desired gap G can be formed on the surface. Further, by making the thickness D of the insulating layer 61 smaller by thickening the diffusion preventing insulating film 5, the thickness at a portion not supported by the side surface of the bonding electrode 7 (H PLG- (H-D)) Aspect ratio can be kept low.

（変形例２）
第１実施形態においては、配線３の上面にコア部３２が露出しているので、絶縁層６１の下に拡散防止絶縁膜５を備える２層構造としている。しかし、配線３が、絶縁層４から露出して形成される部分が、絶縁層６１を構成するＳｉＯ2へ拡散し難い金属材料で形成されていたり、上面にもバリア膜３１を備えている場合には、拡散防止絶縁膜５が不要となる。このような配線３Ａを備える、第１実施形態の変形例に係る半導体素子基板１Ａは、図８に示すように、半導体素子基板１から拡散防止絶縁膜５を取り除き、配線３を配線３Ａに替えた構造で、絶縁層６１に形成された孔による凹み（ポケット）８の形状等は半導体素子基板１と同様である。このような半導体素子基板１Ａは、表面の凹み８の底面に配線３Ａが露出している。以下、本変形例に係る半導体素子基板を構成する各要素について、第１実施形態と異なるものについて詳細に説明する。 (Modification 2)
In the first embodiment, since the core portion 32 is exposed on the upper surface of the wiring 3, the diffusion preventing insulating film 5 is provided below the insulating layer 61 to form a two-layer structure. However, in the case where the portion formed by exposing the wiring 3 from the insulating layer 4 is formed of a metal material that does not easily diffuse into the SiO 2 constituting the insulating layer 61, or the barrier film 31 is also provided on the upper surface Therefore, the diffusion preventing insulating film 5 is unnecessary. As shown in FIG. 8, the semiconductor element substrate 1A according to the modification of the first embodiment, having such an interconnection 3A, removes the diffusion preventing insulating film 5 from the semiconductor element substrate 1 and replaces the interconnection 3 with the interconnection 3A. The shape of the recess (pocket) 8 due to the hole formed in the insulating layer 61 is the same as that of the semiconductor element substrate 1. In such a semiconductor element substrate 1A, the wiring 3A is exposed at the bottom of the recess 8 on the surface. The elements of the semiconductor device substrate according to the present modification will be described in detail below, as different from the first embodiment.

配線３Ａは、第１実施形態に係る半導体素子基板１の配線３と同様、コンタクト部３ｃ、配線部３ｉおよびビア３ｖ、ならびにパッド部３ｐを備える。そして、前記したように、絶縁層４から上面が露出して形成されるパッド部３ｐや配線部３ｉ2が、絶縁層６１へＣｕを拡散させない構造である。本変形例に係る半導体素子基板１Ａにおいてはさらに、配線３Ａのパッド部３ｐが、平面視で、接合電極７よりも大きいだけでなく、凹み８の底面（幅（Ｗ＋２ＧB））以上の大きさに設計されることが好ましい。すなわち、パッド部３ｐの接合電極７からの張出し長さが、ＧB（≒√[Ｇ2−(Ｄ／ｘ)2] ）以上となるように設計されることが好ましい。パッド部３ｐの張出し長さが底面の間隙ＧBよりも小さいと、凹み８が絶縁層６１の下の絶縁層４に及び、凹み８がさらに深いと、配線３Ａおよびその上の接合電極７が倒れる等の不良を生じる虞があるからである。したがって、絶縁層６１の厚さＨすなわち深さＤに対して、間隙Ｇの大きい、浅く広い凹み８を形成する場合には、配線３Ａのパッド部３ｐを拡張する。 Similar to the wiring 3 of the semiconductor element substrate 1 according to the first embodiment, the wiring 3A includes a contact portion 3c, a wiring portion 3i, a via 3v, and a pad portion 3p. Then, as described above, the pad portion 3 p and the wiring portion 3 i 2 formed by exposing the upper surface from the insulating layer 4 do not diffuse Cu into the insulating layer 61. In the semiconductor device substrate 1A according to the present variation further, the pad portion 3p of the wiring 3A is a plan view, not only greater than the bonding electrode 7, the bottom surface of the recess 8 (width (W + 2G B)) over size It is preferred to be designed. That is, projecting length from the junction electrode 7 of the pad portion 3p is, G B (≒ √ [G 2 - (D / x) 2]) are preferably designed such that the above. When projecting length of the pad portion 3p is smaller than the gap G B of the bottom surface, depressions 8 Oyobi the insulating layer 4 below the insulating layer 61, the recess 8 is deeper, wires 3A and bonding electrode 7 thereon It is because there is a possibility that a defect such as falling over may occur. Therefore, when forming the shallow wide recess 8 having a large gap G with respect to the thickness H, that is, the depth D of the insulating layer 61, the pad portion 3p of the wiring 3A is expanded.

第１実施形態の変形例に係る半導体素子基板１Ａは、図５に示す半導体素子基板１の製造方法の接合部形成工程Ｓ２０から、拡散防止絶縁膜成膜工程Ｓ２１と、拡散防止絶縁膜エッチング工程Ｓ２６を除いて製造することができる。それぞれの工程は、第１実施形態にて説明した通りである。ただし、絶縁膜等方性エッチング工程Ｓ２４においては、配線３Ａの最上層の材料に対する選択比の高いエッチング方法を適用することが好ましい。   The semiconductor element substrate 1A according to the modification of the first embodiment includes the diffusion preventing insulating film forming step S21 and the diffusion preventing insulating film etching step from the bonding portion forming step S20 of the method of manufacturing the semiconductor element substrate 1 shown in FIG. It can manufacture except S26. The respective steps are as described in the first embodiment. However, in the insulating film isotropic etching step S24, it is preferable to apply an etching method having a high selectivity to the material of the uppermost layer of the wiring 3A.

このように、配線３Ａが上側のＳｉＯ2膜への拡散防止構造を有することで、いっそう工程を簡略にして製造することができる。 Thus, the process can be further simplified by manufacturing the wiring 3A having the diffusion preventing structure to the upper SiO 2 film.

第１実施形態の変形例に係る半導体素子基板１Ａは、第１実施形態の接合工程Ｓ２と同様に、互いに接合電極７が左右対称に配置された２枚で接合して接合型半導体素子１０とすることができる。この接合型半導体素子１０は、空隙８０が絶縁体６０の高さ（厚さ）全体に形成された構造となる。また、半導体素子基板１Ａは、平面視で、互いに接合電極７が左右対称に配置されていれば、第１実施形態に係る半導体素子基板１と接合することもできる。   Similar to the bonding step S2 of the first embodiment, the semiconductor element substrate 1A according to the modification of the first embodiment is formed by bonding two bonding electrodes 7 symmetrically arranged on the left and right sides of the bonding type semiconductor device 10 and can do. The junction-type semiconductor device 10 has a structure in which the air gap 80 is formed over the entire height (thickness) of the insulator 60. The semiconductor element substrate 1A can also be joined to the semiconductor element substrate 1 according to the first embodiment as long as the junction electrodes 7 are arranged symmetrically in plan view.

以上のように、本発明の第１実施形態およびその変形例に係る接合型半導体素子によれば、Ｃｕ電極を接合部に備え、工程数等を増やすことなく、接合強度を十分に確保しつつ、接合の位置ずれに起因する信頼性低下等の不良を低減することができる。さらに、電極にバリア膜を被覆していないので、接合前において、接触する異種金属（ＣｕとＴａ，Ｔｉ）が共に露出していることによる局所電池効果で生じるガルバニック腐食の虞がなく、保管における環境や期間等の管理が容易である。   As described above, according to the junction-type semiconductor device according to the first embodiment of the present invention and the modification thereof, the Cu electrode is provided at the junction and the junction strength is sufficiently secured without increasing the number of steps and the like. It is possible to reduce defects such as reliability deterioration due to positional deviation of bonding. Furthermore, since the electrode is not coated with the barrier film, there is no risk of galvanic corrosion caused by the local battery effect due to the exposure of both the dissimilar metals (Cu, Ta, Ti) in contact before bonding. Management of environment and period is easy.

〔第２実施形態〕
第１実施形態に係る接合型半導体素子を構成する半導体素子基板は、最表面を被覆するＳｉＯ2膜を等方性エッチングで加工していることにより、表面の凹みによる電極周りの間隙がＳｉＯ2膜の厚さに依拠し、間隙を広がり過ぎないように抑えるためにはＳｉＯ2膜の厚さを小さくすることになる。しかし、表面の平滑化処理等の製造上の観点からＳｉＯ2膜の薄膜化には限界があるため、ＳｉＯ2膜の厚さによらずに凹みの間隙を所望の大きさとすることが好ましい。以下、第２実施形態に係る接合型半導体素子およびこれを構成する半導体素子基板について説明する。第１実施形態と同じ要素については同じ符号を付し、説明を省略する。 Second Embodiment
In the semiconductor element substrate constituting the junction-type semiconductor element according to the first embodiment, since the SiO 2 film covering the outermost surface is processed by isotropic etching, the gap around the electrode due to the depression of the surface is SiO 2 Depending on the thickness of the film, the thickness of the SiO 2 film should be reduced in order to prevent the gap from expanding too much. However, since there is a limit to thinning of the SiO 2 film from the viewpoint of manufacturing such as surface smoothing processing, it is preferable to set the gap of the recess to a desired size regardless of the thickness of the SiO 2 film. Hereinafter, a junction-type semiconductor device according to the second embodiment and a semiconductor device substrate constituting the same will be described. The same elements as in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

本発明の第２実施形態に係る接合型半導体素子１０Ｂは、図９に示す接合面近傍以外は、図２に示す第１実施形態に係る接合型半導体素子１０と同様の構造である。すなわち、本発明の第２実施形態に係る接合型半導体素子１０Ｂを構成する半導体素子基板（本発明の第２実施形態に係る半導体素子基板）１Ｂは、図１０に示す表面近傍以外は、図２および図３に示す半導体素子基板１と同様の構造である。接合型半導体素子１０Ｂは、絶縁体６０の高さ（厚さ）方向における一部の接合面を含む領域に空隙８０Ｂを有し、空隙８０Ｂのそれぞれを上下に貫通するように柱状電極７０Ｂが設けられる。したがって、接合型半導体素子１０Ｂは、柱状電極７０Ｂが空隙８０Ｂの上下にそれぞれ突き出して長く（高く）形成された構造となる。   The junction-type semiconductor device 10B according to the second embodiment of the present invention has the same structure as that of the junction-type semiconductor device 10 according to the first embodiment shown in FIG. 2 except in the vicinity of the bonding surface shown in FIG. That is, the semiconductor element substrate (the semiconductor element substrate according to the second embodiment of the present invention) 1B constituting the junction-type semiconductor element 10B according to the second embodiment of the present invention is the same as that shown in FIG. And the same structure as the semiconductor element substrate 1 shown in FIG. In the junction-type semiconductor device 10B, a void 80B is provided in a region including a part of the bonding surface in the height (thickness) direction of the insulator 60, and the columnar electrode 70B is provided to penetrate each of the voids 80B vertically. Be Therefore, the junction-type semiconductor device 10B has a structure in which the columnar electrodes 70B are formed long (high) by protruding above and below the air gap 80B.

本発明の第２実施形態に係る半導体素子基板１Ｂは、表層に半導体素子構造２を形成されたＳｉ基板２０（図３参照）と、半導体素子構造２に接続する配線３Ｂと、Ｓｉ基板２０上を被覆して配線３Ｂ間を絶縁する絶縁層４と、絶縁層４上に積層された拡散防止絶縁膜５と、拡散防止絶縁膜５に積層されて最表面に形成される絶縁層６１と、一部の配線３Ｂの上面に接続して表面に露出する柱状の接合電極７Ｂと、を備える。半導体素子基板１Ｂはさらに、上から見て接合電極７Ｂを囲む環状の凹み（ポケット）８Ｂが形成されるように、表面に広がって開口した穴が絶縁層６１に形成され、それぞれの穴の底面の中央から柱状の接合電極７Ｂが垂直に突設されている。以下、本実施形態に係る半導体素子基板を構成する各要素について、第１実施形態と異なるものについて詳細に説明する。   The semiconductor device substrate 1B according to the second embodiment of the present invention includes a Si substrate 20 (see FIG. 3) having the semiconductor device structure 2 formed on the surface, a wire 3B connected to the semiconductor device structure 2, and the Si substrate 20. An insulating layer 4 for covering between the wires 3B, a diffusion preventing insulating film 5 stacked on the insulating layer 4, and an insulating layer 61 stacked on the diffusion preventing insulating film 5 and formed on the outermost surface; And a columnar bonding electrode 7B connected to the upper surface of a part of the wiring 3B and exposed to the surface. The semiconductor element substrate 1B is further formed with a hole which is expanded and opened on the surface so as to form an annular recess (pocket) 8B surrounding the junction electrode 7B as viewed from above, and the bottom of each hole A columnar bonding electrode 7B is vertically protruded from the center of the. The components of the semiconductor element substrate according to the present embodiment, which are different from the first embodiment, will be described in detail below.

（配線）
配線３Ｂは、第１実施形態に係る半導体素子基板１の配線３と同じ構造で、絶縁層４から上面が露出して形成されるパッド部３ｐ等が、コア部３２とバリア膜３１とを備える。ただし、配線３Ｂのパッド部３ｐは、平面視形状が接合電極７Ｂよりも必ずしも大きくなくてよく、配線３Ｂ−接合電極７Ｂ間で必要な導通が得られればよく、本実施形態では接合電極７Ｂよりも少し小さい。 (wiring)
The wiring 3B has the same structure as the wiring 3 of the semiconductor element substrate 1 according to the first embodiment, and the pad 3p and the like formed with the upper surface exposed from the insulating layer 4 include the core 32 and the barrier film 31. . However, the pad portion 3p of the wiring 3B may not necessarily have a larger shape in plan view than the bonding electrode 7B, as long as necessary conduction can be obtained between the wiring 3B and the bonding electrode 7B. Even a little small.

（接合電極）
接合電極７Ｂは、第１実施形態に係る半導体素子基板１の接合電極７と同様、半導体素子基板１Ｂの表面に露出する柱状の電極で、別の半導体素子基板１Ｂ（１，１Ａ）の接合電極７Ｂ（７）と接合するために設けられる。接合電極７Ｂは、Ｃｕからなるプラグ７２と、その下（配線３Ｂと接続する側）のバリア膜７１とを備える２層構造である。本実施形態において、バリア膜７１は、その上のプラグ７２を絶縁層６１に接触させないように穴を形成された高さ位置まで持ち上げるために設けられる。したがって、バリア膜７１は、絶縁層６１を構成するＳｉＯ2に拡散し難い金属電極材料で形成される。バリア膜７１はさらに、プラグ７２との界面近傍で接触している絶縁層６１や接合電極７Ｂの下の絶縁層４へ、プラグ７２からＣｕを拡散させないために、配線３Ｂのバリア膜３１と同様、Ｔａ，ＴａＮ，Ｔｉ，ＴｉＮ，ＴｉＷ等を適用する。また、バリア膜７１は、これらの金属膜を２種類以上積層した多層膜としてもよく、プラグ７２の側（上）にＲｕ膜を積層した、例えばＲｕ／Ｔｉの２層膜としてもよい。バリア膜７１は、Ｃｕの拡散防止効果を十分に発現するために、材料にもよるが、厚さＨBRRが少なくとも数〜十数ｎｍ程度あればよい。ただし本実施形態に係る半導体素子基板１Ｂでは、表面の凹み８Ｂの深さＤに基づいて、バリア膜７１の厚さ（高さ）ＨBRRが設計され、ＨBRR＞Ｈ−Ｄ（Ｈ：拡散防止絶縁膜５と絶縁層６１の合計の厚さ）とする。 (Junction electrode)
Similar to the bonding electrode 7 of the semiconductor element substrate 1 according to the first embodiment, the bonding electrode 7B is a columnar electrode exposed on the surface of the semiconductor element substrate 1B, and is a bonding electrode of another semiconductor element substrate 1B (1, 1A). It is provided to join with 7B (7). The bonding electrode 7B has a two-layer structure including a plug 72 made of Cu and a barrier film 71 below the plug 72 (the side connected to the wiring 3B). In the present embodiment, the barrier film 71 is provided to lift up to a height position where a hole is formed so that the plug 72 thereon is not in contact with the insulating layer 61. Therefore, the barrier film 71 is formed of a metal electrode material which hardly diffuses into SiO 2 constituting the insulating layer 61. The barrier film 71 is also similar to the barrier film 31 of the wiring 3B in order to prevent Cu from diffusing from the plug 72 to the insulating layer 61 in contact with the vicinity of the interface with the plug 72 and the insulating layer 4 under the bonding electrode 7B. , Ta, TaN, Ti, TiN, TiW, etc. are applied. The barrier film 71 may be a multilayer film in which two or more of these metal films are stacked, or may be a Ru / Ti bilayer film in which a Ru film is stacked on the side (upper side) of the plug 72. The barrier film 71 may have a thickness HBRR of at least several to several tens of nm, depending on the material, in order to sufficiently exhibit the diffusion preventing effect of Cu. However, in the semiconductor element substrate 1B according to the present embodiment, the thickness (height) HBRR of the barrier film 71 is designed based on the depth D of the recess 8B on the surface, and HBRR > HD (H: diffusion The total thickness of the protective insulating film 5 and the insulating layer 61).

（絶縁層）
拡散防止絶縁膜５は、第１実施形態にて説明した通りの構造であるが、本実施形態においては特に、Ｃｕの拡散を防止することのできる程度に膜厚がより小さい（薄い）ことが好ましい。 (Insulating layer)
The diffusion preventing insulating film 5 has the structure as described in the first embodiment, but in the present embodiment, in particular, the film thickness is smaller (thin) to such an extent that the diffusion of Cu can be prevented. preferable.

絶縁層６１は、第１実施形態と同様に、接合電極７Ｂを貫通させ、かつ、半導体素子基板１Ｂの表面に接合電極７Ｂを囲む凹み８Ｂを形成する孔が形成されている。詳しくは、絶縁層６１には、表面から深さＤまでの領域において、上方へ広がって開口するように、断面視で接合電極７Ｂの側面に１／４円弧（楕円弧を含む）を描く形状の穴が形成されている。穴の深さＤは絶縁層６１の厚さよりも小さいため、絶縁層６１にはさらに、この穴の底面の中央から真下へ、接合電極７Ｂと同径Ｗの孔が下面まで穿設されている。したがって、下の径Ｗの孔は、絶縁層６１の下層部分とその下の拡散防止絶縁膜５に連続して形成されている。絶縁層６１は、このような構造により、表面から深さＤよりも上で接合電極７Ｂに非接触であり、深さＤ以下で接合電極７Ｂの側面に接触している。そして、前記したように、接合電極７Ｂが下層に厚さＨBRR（＞Ｈ−Ｄ）のバリア膜７１を設けられているので、絶縁層６１が接触する接合電極７Ｂの部分はバリア膜７１のみであり、プラグ７２には非接触となる。 As in the first embodiment, the insulating layer 61 has a hole for penetrating the bonding electrode 7B and forming a recess 8B surrounding the bonding electrode 7B on the surface of the semiconductor element substrate 1B. Specifically, the insulating layer 61 has a shape that draws a quarter arc (including an elliptic arc) on the side surface of the bonding electrode 7B in a cross sectional view so as to expand and open upward in the region from the surface to the depth D A hole is formed. Since the depth D of the hole is smaller than the thickness of the insulating layer 61, a hole having the same diameter W as that of the bonding electrode 7B is further bored in the insulating layer 61 from the center of the bottom to the bottom. . Therefore, the lower diameter W hole is continuously formed in the lower layer portion of the insulating layer 61 and the diffusion preventing insulating film 5 therebelow. With such a structure, the insulating layer 61 is not in contact with the junction electrode 7B above the depth D from the surface, and is in contact with the side surface of the junction electrode 7B at the depth D or less. Then, as described above, since the junction electrode 7B is provided with the barrier film 71 of the thickness H BRR (> H−D) in the lower layer, the portion of the junction electrode 7B in contact with the insulating layer 61 is only the barrier film 71. And the plug 72 is not in contact.

絶縁層６１は、第１実施形態と同様、穴の表面での開口幅（径）を（Ｗ＋２Ｇ）と表したとき、表面における接合電極７Ｂとの間隙Ｇは、接合における位置ずれの最大値ｓMAX等に基づいて設計される。なお、本実施形態においては、間隙Ｇに対して、穴の深さＤが、Ｄ≒ｘ×Ｇとなる。接合電極７Ｂは、半導体素子基板１Ｂにおいて、半導体素子基板１の接合電極７と同様、側面で支持されていない部分での高さ（厚さ）（ＨPLG−(Ｈ−Ｄ)）についてアスペクト比が高過ぎないことが好ましい。そのため、接合電極７Ｂの径Ｗにも応じて、穴（凹み８Ｂ）の深さＤおよび開口幅（Ｗ＋２Ｇ）を設計することが好ましい。 Similarly to the first embodiment, when the opening width (diameter) at the surface of the hole is expressed as (W + 2G), the gap G between the surface and the bonding electrode 7B at the surface is the maximum value s of positional deviation in bonding. It is designed based on MAX etc. In the present embodiment, for the gap G, the depth D of the hole is D ≒ x × G. The junction electrode 7B has an aspect ratio with respect to the height (thickness) (H PLG − (H−D)) at a portion not supported by the side surface of the semiconductor element substrate 1B as the junction electrode 7 of the semiconductor element substrate 1 Is preferably not too high. Therefore, it is preferable to design the depth D and the opening width (W + 2G) of the hole (dent 8B) in accordance with the diameter W of the bonding electrode 7B.

半導体素子基板１Ｂは、接合電極７Ｂの厚さＨPLG（＝Ｈ＋ΔＨPLG）に対して表面の凹み８Ｂの深さＤが浅いと、バリア膜７１の厚さＨBRRが大きくなる。バリア膜７１に適用される導電性材料は、プラグ７２（Ｃｕ）よりも導電性に劣るため、バリア膜７１が厚いほど接合電極７Ｂの導電性が低下することになる。そこで、間隙Ｇが長過ぎない程度に凹み８Ｂの深さＤを深く設計してバリア膜７１の厚膜化を抑制したり、接合電極７Ｂの径Ｗを広くして抵抗を低減することが好ましい。あるいは、バリア膜７１は、厚さＨBRRが大きい場合、３層構造として、配線３Ｂ（コア部３２）に接触する下層とプラグ７２に接触する上層との各数〜十数ｎｍの厚さの部分に、Ｃｕのバリア性の高い材料を選択し、中間層にはＷ等、Ｃｕ以外の比較的導電性の高い材料を設けてもよい。 In the semiconductor element substrate 1B, when the depth D of the recess 8B on the surface is shallower than the thickness H PLG (= H + ΔH PLG ) of the bonding electrode 7B, the thickness H BRR of the barrier film 71 becomes large. The conductive material applied to the barrier film 71 is inferior in conductivity to the plug 72 (Cu), so the thicker the barrier film 71, the lower the conductivity of the bonding electrode 7B. Therefore, it is preferable to design the depth D of the recess 8B deep enough to prevent the gap G from being too long to suppress thickening of the barrier film 71 or widen the diameter W of the bonding electrode 7B to reduce resistance. . Alternatively, when the thickness HBRR is large, the barrier film 71 has a three-layer structure in which the lower layer in contact with the wiring 3B (core portion 32) and the upper layer in contact with the plug 72 have a thickness of several to dozen nm For the part, a material having a high barrier property of Cu may be selected, and the intermediate layer may be provided with a material having a relatively high conductivity other than Cu, such as W.

（半導体素子基板の製造方法）
本発明の第２実施形態に係る半導体素子基板の製造方法について、図１１、図１２および図１３を参照して説明する。なお、図１２においては、加工前の膜についても加工後の要素と同じ符号を付して表す。本実施形態に係る半導体素子基板１Ｂは、Ｓｉ基板２０上に、半導体素子構造２とこれに接続する配線３Ｂ、および絶縁層４を形成する半導体素子・配線形成工程Ｓ１０と、表面を被覆する絶縁層６１と表面に露出する接合電極７Ｂを形成する接合部形成工程Ｓ２０Ａと、を行う（半導体素子製造工程Ｓ１）。 (Method of manufacturing semiconductor element substrate)
A method of manufacturing a semiconductor device substrate according to the second embodiment of the present invention will be described with reference to FIGS. 11, 12 and 13. In FIG. 12, the film before processing is also shown with the same reference numeral as the element after processing. The semiconductor element substrate 1B according to the present embodiment includes a semiconductor element / wiring forming step S10 for forming the semiconductor element structure 2 and the wiring 3B connected thereto and the insulating layer 4 on the Si substrate 20, and insulation for covering the surface. A bonding portion forming step S20A for forming the layer 61 and the bonding electrode 7B exposed on the surface is performed (semiconductor element manufacturing step S1).

半導体素子・配線形成工程Ｓ１０は、配線形成工程Ｓ１２で形成する配線３Ｂのパッド部３ｐの形状以外は第１実施形態で説明した通りである。接合部形成工程Ｓ２０Ａは、拡散防止絶縁膜５を構成する絶縁膜を成膜する拡散防止絶縁膜成膜工程Ｓ２１と、絶縁層６１を構成する絶縁膜を成膜する絶縁膜成膜工程Ｓ２２と、絶縁膜の表面を研磨して平滑化する平滑化工程Ｓ２３と、接合電極７が形成される領域を空けたレジストマスクＰＲ１を形成するマスク工程Ｓ３３と、等方性エッチングで絶縁層６１の上層を成形する絶縁膜等方性エッチング工程Ｓ２４Ａと、エッチング（異方性エッチング）で絶縁層６１の残部を成形する絶縁膜エッチング工程Ｓ２５と、エッチングで拡散防止絶縁膜５を成形する拡散防止絶縁膜エッチング工程Ｓ２６と、導電性材料を成膜してバリア膜７１を形成するバリア膜成膜工程Ｓ３１と、Ｃｕを成膜してプラグ７２を形成する電極成膜工程Ｓ３４と、レジストマスクＰＲ１を除去するマスク除去工程（リフトオフ工程）Ｓ３５と、を行う。すなわち、接合部形成工程Ｓ２０Ａは、第１実施形態の接合部形成工程Ｓ２０（図５参照）に対して、絶縁膜等方性エッチング工程Ｓ２４を絶縁膜等方性エッチング工程Ｓ２４Ａと絶縁膜エッチング工程Ｓ２５の２工程に分けて行い、さらに、電極成膜工程Ｓ３４の前にバリア膜成膜工程Ｓ３１を追加する。   The semiconductor element / wiring formation step S10 is as described in the first embodiment except for the shape of the pad portion 3p of the wiring 3B formed in the wiring formation step S12. The bonding portion forming step S20A includes a diffusion preventing insulating film forming step S21 of forming an insulating film forming the diffusion preventing insulating film 5, and an insulating film forming step S22 of forming an insulating film forming the insulating layer 61. A smoothing step S23 for polishing and smoothing the surface of the insulating film, a mask step S33 for forming a resist mask PR1 with an area where the bonding electrode 7 is formed, and an upper layer of the insulating layer 61 by isotropic etching Insulating film isotropic etching step S24A for forming the insulating film, insulating film etching step S25 for forming the remaining portion of the insulating layer 61 by etching (anisotropic etching), and a diffusion preventing insulating film for forming the diffusion preventing insulating film 5 by etching Etching step S26, barrier film forming step S31 of forming conductive film to form barrier film 71, electrode forming step S34 of forming Cu film to form plug 72, A mask removing step (lift-off process) S35 of removing the resist mask PR1, is carried out. That is, as compared with the joint formation process S20 (see FIG. 5) of the first embodiment, the joint formation process S20A is the insulation film isotropic etching process S24, the insulation film isotropic etching process S24A, and the insulation film etching process. The process is divided into two steps of S25, and a barrier film formation step S31 is added before the electrode formation step S34.

（絶縁膜エッチング工程、拡散防止絶縁膜エッチング工程）
接合部形成工程Ｓ２０Ａは、マスク工程Ｓ３３までは第１実施形態の接合部形成工程Ｓ２０と同様である（図６（ａ）〜（ｂ）参照）。本実施形態では、絶縁膜等方性エッチング工程Ｓ２４Ａにおいて、図１２（ａ）に示すように、絶縁層６１を構成するＳｉＯ2膜を等方性エッチングで、絶縁層６１の厚さよりも浅く、深さＤまでエッチングする。等方性エッチングにより、レジストマスクＰＲ１の空いた領域の直下で、表面に広がって径（Ｗ＋２Ｇ）開口した深さＤの穴が形成される。 (Insulating film etching process, diffusion preventing insulating film etching process)
The bonding portion forming step S20A is the same as the bonding portion forming step S20 of the first embodiment up to the mask step S33 (see FIGS. 6A and 6B). In this embodiment, in the insulating film isotropic etching step S24A, as shown in FIG. 12A, the SiO 2 film constituting the insulating layer 61 is isotropically etched and shallower than the thickness of the insulating layer 61, Etch to depth D. By the isotropic etching, a hole having a depth (D) which is spread on the surface and opened at a diameter (W + 2G) is formed immediately below the vacant region of the resist mask PR1.

図１２（ｂ）に示すように、絶縁膜等方性エッチング工程Ｓ２４Ａで形成された穴の底に残ったＳｉＯ2膜を、その下の拡散防止絶縁膜５を構成するＳｉＮ膜をエッチングストッパ膜として、ＲＩＥ等の異方性エッチングで完全に除去して、絶縁層６１に成形する（Ｓ２５）。その後、図１２（ｃ）に示すように、露出したＳｉＮ膜を異方性エッチングで完全に除去して（Ｓ２６）、配線３Ｂおよびその周囲の絶縁層４を露出させる。絶縁膜エッチング工程Ｓ２５は、拡散防止絶縁膜エッチング工程Ｓ２６と同様の異方性エッチングで行うことができ、ＳｉＯ2膜の下の拡散防止絶縁膜５を構成するＳｉＮ膜に対する選択比の高いことが好ましい。また、拡散防止絶縁膜エッチング工程Ｓ２６は、拡散防止絶縁膜５の空いた領域に露出する配線３Ｂと絶縁層４との境界で段差を生じないように、エッチング量を制御する。 As shown in FIG. 12B, the SiO 2 film left at the bottom of the hole formed in the insulating film isotropic etching step S24A is etched, and the SiN film forming the diffusion preventing insulating film 5 thereunder is etched. As a result, the insulating layer 61 is completely removed by anisotropic etching such as RIE (S25). Thereafter, as shown in FIG. 12C, the exposed SiN film is completely removed by anisotropic etching (S26) to expose the wiring 3B and the insulating layer 4 around it. The insulating film etching step S25 can be performed by the same anisotropic etching as the diffusion preventing insulating film etching step S26, and the selection ratio to the SiN film constituting the diffusion preventing insulating film 5 under the SiO 2 film is high. preferable. Further, in the diffusion preventing insulating film etching step S26, the etching amount is controlled so as not to cause a step at the boundary between the wiring 3B exposed to the open area of the diffusion preventing insulating film 5 and the insulating layer 4.

（バリア膜成膜工程、電極成膜工程、マスク除去工程）
Ｔａ等のバリア膜７１を構成する導電性材料を成膜して、レジストマスクＰＲ１の空いた領域の直下の径Ｗの孔およびその直上に厚さＨBRRまで埋め込んでバリア膜７１をパッド部３ｐ上に形成する（Ｓ３１）。引き続いて、Ｃｕを成膜して、図１３に示すように、バリア膜７１の直上に堆積させてプラグ７２を形成する（Ｓ３４）。バリア膜成膜工程Ｓ３１は、電極成膜工程Ｓ３４と同様、膜材料の直進性の高い真空蒸着法等を適用し、電極成膜工程Ｓ３４を連続して行うことができる。その後、レジストマスクＰＲ１をその上のＴａ膜、Ｃｕ膜ごと除去して（Ｓ３５）、半導体素子基板１Ｂが得られる。 (Barrier film deposition process, electrode film deposition process, mask removal process)
A conductive material constituting the barrier film 71 such as Ta is formed into a film, and the hole W of diameter W immediately below the opened region of the resist mask PR1 and the thickness H BRR are buried immediately above it, and the barrier film 71 is pad portion 3p. Form on (S31). Subsequently, Cu is formed into a film, and as shown in FIG. 13, the plug 72 is formed directly on the barrier film 71 (S34). Similar to the electrode film formation step S34, the barrier film formation step S31 can be performed by continuously forming the electrode film formation step S34 by applying a vacuum deposition method or the like with high straightness of film material. Thereafter, the resist mask PR1 is removed together with the Ta film and the Cu film thereon (S35), and the semiconductor element substrate 1B is obtained.

このように、接合電極７Ｂを下にバリア膜７１を設けた２層構造とすることで、ＳｉＯ2からなる絶縁層６１の上層にのみ所望の深さＤの凹み８Ｂを形成して、接合電極７ＢのＣｕ（プラグ７２）を絶縁層６１に接触させることなく形成することができる。さらに、バリア膜７１により、接合電極７ＢのＣｕが下の絶縁層４にも接触しない。得られた半導体素子基板１Ｂは、第１実施形態の接合工程Ｓ２と同様に、互いに接合電極７Ｂが左右対称に配置された２枚で接合して接合型半導体素子１０Ｂとすることができる。また、半導体素子基板１Ｂは、平面視で、互いに接合電極７が左右対称に配置されていれば、第１実施形態に係る半導体素子基板１，１Ａと接合することができる。 Thus, by forming the barrier film 71 below the junction electrode 7B, a recess 8B of a desired depth D is formed only in the upper layer of the insulating layer 61 made of SiO 2 to form the junction electrode. The Cu (plug 72) of 7B can be formed without contacting the insulating layer 61. Furthermore, due to the barrier film 71, Cu of the bonding electrode 7B is not in contact with the lower insulating layer 4 either. Similar to the bonding step S2 of the first embodiment, the obtained semiconductor element substrate 1B can be joined to form the junction-type semiconductor element 10B by joining two junction electrodes 7B arranged symmetrically to each other. The semiconductor element substrate 1B can be joined to the semiconductor element substrates 1 and 1A according to the first embodiment as long as the bonding electrodes 7 are arranged symmetrically in plan view.

（変形例）
第１実施形態の変形例に係る半導体素子基板１Ａ（図８参照）のように、ＳｉＯ2へ拡散し難い金属材料を最上層に備え、かつ平面視で、接合電極７Ｂよりも大きな形状に形成されたパッド部３ｐを備える配線３Ａであれば、拡散防止絶縁膜５が不要である。すなわち、その製造方法の接合部形成工程Ｓ２０Ａにおいて、拡散防止絶縁膜成膜工程Ｓ２１および拡散防止絶縁膜エッチング工程Ｓ２６を行わない。 (Modification)
As in the semiconductor element substrate 1A (see FIG. 8) according to the modification of the first embodiment, a metal material that hardly diffuses into SiO 2 is provided in the uppermost layer, and formed in a shape larger than the bonding electrode 7B in plan view In the case of the wiring 3A provided with the pad portion 3p, the diffusion preventing insulating film 5 is unnecessary. That is, in the bonding portion forming step S20A of the manufacturing method, the diffusion preventing insulating film forming step S21 and the diffusion preventing insulating film etching step S26 are not performed.

２層構造の接合電極７Ｂは、第１実施形態に係る半導体素子基板１，１Ａ（図３、図８参照）に設けられてもよい。バリア膜７１を拡散防止絶縁膜５よりも厚く形成することにより、凹み８の底面における間隙の長さＧBにマージンが十分になくても（ＧB≒０）、Ｃｕ（プラグ７２）が絶縁層６１に接触しない。また、前記したように、バリア膜７１によりＣｕ（プラグ７２）が下の絶縁層４に接触しないので、接合電極７Ｂは、半導体素子基板１，１Ａにおいても、平面視でパッド部３ｐの小さい配線３Ｂを備える場合に設けられる。この場合には、バリア膜７１の厚さを拡散防止絶縁膜５よりも小さくして、バリア膜７１を露出させないことが好ましい（図２２（ｂ）参照）。 The junction electrode 7B having a two-layer structure may be provided on the semiconductor element substrate 1 or 1A (see FIGS. 3 and 8) according to the first embodiment. By forming thicker than the barrier film 71 diffusion preventing insulating film 5, a margin in the length G B of the gap in the bottom of the recess 8 is also sufficiently without (G B ≒ 0), Cu ( plug 72) is insulated It does not contact the layer 61. Further, as described above, since Cu (plug 72) is not in contact with the lower insulating layer 4 by the barrier film 71, the junction electrode 7B is a wiring with a small pad portion 3p in plan view also in the semiconductor element substrates 1 and 1A. It is provided when providing 3B. In this case, it is preferable that the thickness of the barrier film 71 be smaller than that of the diffusion preventing insulating film 5 so that the barrier film 71 is not exposed (see FIG. 22B).

以上のように、本発明の第２実施形態およびその変形例に係る接合型半導体素子によれば、第１実施形態と同様に、Ｃｕ電極を接合部に備え、工程数等を増やすことなく、接合強度を十分に確保しつつ、接合の位置ずれに起因する信頼性低下等の不良を低減することができる。   As described above, according to the junction-type semiconductor device according to the second embodiment of the present invention and the modification thereof, as in the first embodiment, the Cu electrode is provided in the junction and the number of steps is not increased. It is possible to reduce defects such as reliability decrease due to misalignment of the bonding while securing sufficient bonding strength.

〔第１、第２実施形態の共通の変形例〕
（変形例１）
接合型半導体素子１０，１０Ｂは、柱状電極７０が、少なくとも接合部（接合面を含む部分）においてＡｕで形成されていてもよい。すなわち、半導体素子基板１，１Ａ，１Ｂ（以下、適宜まとめて、半導体素子基板１と表し、その構成要素もまとめて表す）は、接合電極７のプラグ７２が、Ｃｕに代えてＡｕからなる、あるいは原料コストの観点等から、Ｃｕ層の上にＡｕ膜を積層して備える（図示せず）。接合電極７が表面にのみＡｕ膜を備える場合には、電極成膜工程Ｓ３４でＣｕを成膜した後にＡｕを成膜すればよく、真空蒸着法による成膜を継続してＡｕに切り替えればよい。あるいは、無電解めっきにより、接合電極７の絶縁層６１に接触していない部分をＡｕ膜が被覆してもよい。ただし、ＡｕはＣｕを相互拡散により伝播させるので、接合電極７の側面を被覆するＡｕ膜が凹み８の内壁の絶縁層６１に到達しないように構成する。なお、接合される一組の半導体素子基板１１，１２の一方のみの接合電極７が表面にＡｕを備えて、ＡｕとＣｕとが接合されてもよい。 Common Modification of First and Second Embodiments
(Modification 1)
In each of the junction-type semiconductor elements 10 and 10B, the columnar electrode 70 may be formed of Au at least at a junction (a portion including a junction surface). That is, in the semiconductor element substrates 1, 1A and 1B (hereinafter collectively referred to as the semiconductor element substrate 1 and the components thereof are collectively indicated), the plug 72 of the bonding electrode 7 is made of Au instead of Cu. Alternatively, from the viewpoint of raw material cost, etc., an Au film is stacked on the Cu layer (not shown). In the case where the bonding electrode 7 has an Au film only on the surface, Au may be formed after forming Cu in the electrode film forming step S34, and film formation by a vacuum evaporation method may be continued and switched to Au. . Alternatively, the Au film may cover the portion of the bonding electrode 7 not in contact with the insulating layer 61 by electroless plating. However, since Au propagates Cu by mutual diffusion, the Au film covering the side surface of the junction electrode 7 is configured not to reach the insulating layer 61 on the inner wall of the recess 8. The bonding electrode 7 of only one of the pair of semiconductor element substrates 11 and 12 to be bonded may have Au on the surface, and Au and Cu may be bonded.

（変形例２）
接合型半導体素子１０は、これを構成する一組の半導体素子基板１１，１２の一方が、接合電極７が絶縁層６１の表面から突出して厚く（ΔＨPLG1＞０）、他方が、接合電極７が絶縁層６１の表面よりも低く（ΔＨPLG2＜０）、それぞれ形成されていてもよい（図示せず）。このとき、ΔＨPLG1≧−ΔＨPLG2となるように、接合電極７，７のそれぞれの厚さＨPLG1，ＨPLG2が設計される。このような半導体素子基板１１，１２を接合してなる接合型半導体素子１０は、絶縁体６０（絶縁層６１，６１）と柱状電極７０（接合電極７，７）とで接合面の高さ位置が異なる。 (Modification 2)
In the junction-type semiconductor device 10, one of the pair of semiconductor device substrates 11 and 12 constituting the junction-type semiconductor device 10 has a junction electrode 7 protruding from the surface of the insulating layer 61 and thick (ΔH PLG1 > 0), and the other is a junction electrode 7 Are lower than the surface of the insulating layer 61 (ΔH PLG2 <0), and may be formed respectively (not shown). At this time, the thicknesses H PLG1 and H PLG2 of the bonding electrodes 7 and 7 are designed so that ΔH PLG1 −−ΔH PLG2 . The junction-type semiconductor element 10 formed by joining such semiconductor element substrates 11 and 12 has the height position of the junction surface between the insulator 60 (insulation layers 61 and 61) and the columnar electrode 70 (junction electrodes 7 and 7). Is different.

〔第３実施形態〕
第１、第２実施形態に係る接合型半導体素子を構成する、表面に凹みを形成された半導体素子基板は、接合電極を成膜速度の遅い真空蒸着法で形成するために、厚く設けようとすると生産性が低下する上、接合に好適な表面粗さに形成することが困難になる。以下、第３実施形態に係る接合型半導体素子およびこれを構成する半導体素子基板について説明する。第１、第２実施形態と同じ要素については同じ符号を付し、説明を省略する。 Third Embodiment
The semiconductor element substrate of the junction type semiconductor element according to the first and second embodiments, in which the recess is formed on the surface, is thickly provided in order to form the junction electrode by a vacuum deposition method with a low deposition rate. This lowers productivity and makes it difficult to form a surface roughness suitable for bonding. Hereinafter, a junction-type semiconductor device according to the third embodiment and a semiconductor device substrate constituting the same will be described. The same elements as those in the first and second embodiments are given the same reference numerals, and descriptions thereof will be omitted.

本発明の第３実施形態に係る接合型半導体素子１０Ｃは、図９に示す第２実施形態に係る接合型半導体素子１０Ｂと類似した構造であり、図１４に示す接合面近傍以外は、図２に示す第１実施形態に係る接合型半導体素子１０と同様の構造である。すなわち、本発明の第３実施形態に係る接合型半導体素子１０Ｃを構成する半導体素子基板（本発明の第３実施形態に係る半導体素子基板）１Ｃは、図１５に示す表面近傍以外は、図２および図３に示す半導体素子基板１と同様の構造である。接合型半導体素子１０Ｃは、絶縁体６０の高さ（厚さ）方向における一部の接合面を含む領域に、断面形状が矩形の空隙８０Ｃを有し、柱状電極７０Ｃが空隙８０Ｃの上下にそれぞれ突き出して長く（高く）形成された構造である。   The junction-type semiconductor device 10C according to the third embodiment of the present invention has a structure similar to that of the junction-type semiconductor device 10B according to the second embodiment shown in FIG. 9, and except for the vicinity of the junction surface shown in FIG. The structure is the same as that of the junction-type semiconductor device 10 according to the first embodiment shown in FIG. That is, the semiconductor element substrate (the semiconductor element substrate according to the third embodiment of the present invention) 1C constituting the junction-type semiconductor element 10C according to the third embodiment of the present invention is the same as that shown in FIG. And the same structure as the semiconductor element substrate 1 shown in FIG. The junction-type semiconductor device 10C has a void 80C having a rectangular cross-sectional shape in a region including a part of the junction surface in the height (thickness) direction of the insulator 60, and the columnar electrodes 70C are respectively above and below the void 80C. It is a structure that protrudes and is long (high).

本発明の第３実施形態に係る半導体素子基板１Ｃは、表層に半導体素子構造２を形成されたＳｉ基板２０（図３参照）と、半導体素子構造２に接続する配線３Ｂと、Ｓｉ基板２０上を被覆して配線３Ｂ間を絶縁する絶縁層４と、絶縁層４上に積層された拡散防止絶縁膜５と、拡散防止絶縁膜５に積層されて最表面に形成される絶縁層６１と、一部の配線３Ｂの上面に接続して表面に露出する柱状の接合電極７Ｃと、を備える。半導体素子基板１Ｃはさらに、上から見て接合電極７Ｃを囲む環状の凹み（ポケット）８Ｃが形成されるように、表面に開口して内壁が垂直な穴が絶縁層６１に形成され、それぞれの穴の底面の中央から柱状の接合電極７Ｃが垂直に突設されている。以下、本実施形態に係る半導体素子基板を構成する各要素について、第１、第２実施形態と異なるものについて詳細に説明する。   A semiconductor device substrate 1C according to the third embodiment of the present invention includes a Si substrate 20 (see FIG. 3) having a semiconductor device structure 2 formed on the surface, a wire 3B connected to the semiconductor device structure 2, and the Si substrate 20. An insulating layer 4 for covering between the wires 3B, a diffusion preventing insulating film 5 stacked on the insulating layer 4, and an insulating layer 61 stacked on the diffusion preventing insulating film 5 and formed on the outermost surface; And a columnar bonding electrode 7C connected to the upper surface of a part of the wiring 3B and exposed to the surface. The semiconductor element substrate 1C is further formed with a hole having a perpendicular inner wall in the insulating layer 61 so that an annular recess (pocket) 8C is formed to surround the junction electrode 7C when viewed from above. A columnar bonding electrode 7C is vertically protruded from the center of the bottom of the hole. The components of the semiconductor element substrate according to this embodiment will be described in detail below, as different from the first and second embodiments.

（配線）
配線３Ｂは、第２実施形態に係る半導体素子基板１Ｂの配線３Ｂと同じ構造である。ただし、本実施形態において、パッド部３ｐの上面は、特に平滑としなくてよい。 (wiring)
The wiring 3B has the same structure as the wiring 3B of the semiconductor element substrate 1B according to the second embodiment. However, in the present embodiment, the upper surface of the pad portion 3p may not be particularly smooth.

（接合電極）
接合電極７Ｃは、第１実施形態に係る半導体素子基板１の接合電極７と同様、半導体素子基板１Ｃの表面に露出する柱状の電極で、別の半導体素子基板１Ｃ等の接合電極７（７Ｂ，７Ｃ）と接合するために設けられる。接合電極７Ｃは、Ｃｕからなるプラグ７２と、上面以外（下面と側面）を被覆するバリア膜７１とを備える。本実施形態において、バリア膜７１は、絶縁層６１および接合電極７Ｃの下の絶縁層４へ、プラグ７２からＣｕを拡散させないために設けられる。バリア膜７１を構成する導電性材料は、第２実施形態にて説明した通りである。接合電極７Ｃにおいて、バリア膜７１は、主に最薄となり易い側面において、Ｃｕの拡散を防止することのできる膜厚に形成され、材料にもよるが、少なくとも数〜十数ｎｍ程度とすることが好ましい。バリア膜７１は一方で、膜厚が厚いと低抵抗のプラグ７２の占める割合が低下し、接合電極７Ｃの導電性が低下するので、不要に厚くないことが好ましい。具体的には、バリア膜７１は、側面における膜厚が接合電極７Ｃの径（または幅）Ｗの０．１４６倍以上になると、面内方向における断面積が１／２を超えるため、それよりも薄いことが好ましい。 (Junction electrode)
Similar to the bonding electrode 7 of the semiconductor device substrate 1 according to the first embodiment, the bonding electrode 7C is a columnar electrode exposed on the surface of the semiconductor device substrate 1C, and another bonding electrode 7 (7B, 7C, 7C) for bonding. The bonding electrode 7C includes a plug 72 made of Cu, and a barrier film 71 which covers other than the upper surface (lower surface and side surface). In the present embodiment, the barrier film 71 is provided to prevent Cu from diffusing from the plug 72 into the insulating layer 4 under the insulating layer 61 and the bonding electrode 7C. The conductive material constituting the barrier film 71 is as described in the second embodiment. In the bonding electrode 7C, the barrier film 71 is formed to a film thickness that can prevent the diffusion of Cu mainly on the side that tends to be the thinnest, and depending on the material, at least about several to dozen nm Is preferred. On the other hand, the barrier film 71 is preferably not unnecessarily thick because the ratio occupied by the low-resistance plug 72 decreases if the film thickness is large, and the conductivity of the bonding electrode 7C decreases. Specifically, when the film thickness on the side surface of the barrier film 71 becomes 0.146 times or more of the diameter (or width) W of the junction electrode 7C, the cross-sectional area in the in-plane direction exceeds 1/2. Is preferably thin.

（絶縁層）
拡散防止絶縁膜５は、第２実施形態と同様の構造である。絶縁層６１は、第１、第２実施形態と同様に、接合電極７Ｃを貫通させ、かつ、半導体素子基板１Ｃの表面に接合電極７Ｃを囲む凹み８Ｃを形成する孔が形成されている。詳しくは、絶縁層６１には、表面から深さＤまでの領域において、一定の幅（径）（Ｗ＋２Ｇ）の垂直な穴が形成されている。穴の深さＤは、絶縁層６１の厚さ以下であり、ここでは絶縁層６１の厚さよりも小さい。そのため、絶縁層６１には、穴の底面の中央から真下へ、接合電極７Ｃと同径Ｗの孔が下面まで穿設されている。 (Insulating layer)
The diffusion preventing insulating film 5 has the same structure as that of the second embodiment. As in the first and second embodiments, the insulating layer 61 has a hole for penetrating the bonding electrode 7C and forming a recess 8C surrounding the bonding electrode 7C on the surface of the semiconductor element substrate 1C. Specifically, in the insulating layer 61, in the region from the surface to the depth D, vertical holes having a constant width (diameter) (W + 2G) are formed. The depth D of the hole is equal to or less than the thickness of the insulating layer 61, and is smaller than the thickness of the insulating layer 61 here. Therefore, in the insulating layer 61, a hole having the same diameter W as that of the bonding electrode 7C is bored to the lower surface from the center of the bottom of the hole to immediately below.

半導体素子基板１Ｃは、接合電極７Ｃの周囲に絶縁層６１のない凹み８Ｃを表面に形成されていることにより、絶縁層６１が、位置ずれを有して接合される別の半導体素子基板１Ｃの接合電極７Ｃの接合面（上面）に露出したプラグ７２に接触することがない。そのために、凹み８Ｃによる絶縁層６１と接合電極７Ｃとの間隙Ｇが、接合における位置ずれの最大値ｓMAX超（Ｇ＞ｓMAX）であればよく、例えばｓMAX＝０．４Ｗの場合には、マージンを含めてＧ≧０．５Ｗに設定することができる。また、凹み８Ｃの深さＤは、接合される別の半導体素子基板１Ｃの接合電極７Ｃの上面との距離が０超、すなわちＤ＞ΔＨPLGで、さらに十分なマージンを有するように、Ｄ≧ΔＨPLG＋５０ｎｍとすることが好ましい。一方、接合電極７Ｃは、半導体素子基板１Ｃにおいて、半導体素子基板１の接合電極７等と同様、側面で支持されていない部分での高さ（厚さ）（ＨPLG−(Ｈ−Ｄ)）についてアスペクト比が高過ぎないことが好ましい。本実施形態に係る半導体素子基板１Ｃにおいては、後記製造方法により、凹み８Ｃの間隙Ｇと深さＤとを互いに独立した値に設計することができる。 The semiconductor element substrate 1C is formed on the surface with a recess 8C without the insulating layer 61 around the bonding electrode 7C, so that the insulating layer 61 is joined with a positional deviation and that of another semiconductor element substrate 1C. It does not contact the plug 72 exposed on the bonding surface (upper surface) of the bonding electrode 7C. Therefore, the gap G between the insulating layer 61 and the junction electrode 7C due to the recess 8C may be greater than the maximum value s MAX (G> s MAX ) of the misalignment at the junction, for example, in the case of s MAX = 0.4 W. Can be set to G.gtoreq.0.5 W, including the margin. In addition, the depth D of the recess 8C is DD such that the distance to the upper surface of the junction electrode 7C of another semiconductor element substrate 1C to be joined is more than 0, that is, D> ΔH PLG and D 有するH. It is preferable to set it as ΔH PLG +50 nm. On the other hand, in the semiconductor element substrate 1C, the junction electrode 7C is, like the junction electrode 7 of the semiconductor element substrate 1, the height (thickness) of a portion not supported by the side surface (H PLG- (H-D)) Preferably, the aspect ratio is not too high. In the semiconductor element substrate 1C according to the present embodiment, the gap G and the depth D of the recess 8C can be designed to be values independent of each other by a manufacturing method described later.

〔半導体素子基板の製造方法〕
本発明の第３実施形態に係る半導体素子基板の製造方法について、図１６、図１７および図１８を参照して説明する。なお、図１７および図１８においては、加工前の膜についても加工後の要素と同じ符号を付して表す。本実施形態に係る半導体素子基板１Ｃは、Ｓｉ基板２０上に、半導体素子構造２とこれに接続する配線３Ｂ、および絶縁層４を形成する半導体素子・配線形成工程Ｓ１０と、絶縁膜を表面に被覆して接合電極７Ｃの形状の孔を形成する絶縁層形成工程Ｓ２０Ｂと、前記孔の内部に接合電極７Ｃを形成する電極形成工程Ｓ３０と、表面に凹み８Ｃを形成する接合部形成工程Ｓ４０と、を行う（半導体素子製造工程Ｓ１）。 [Method of Manufacturing Semiconductor Device Substrate]
A method of manufacturing a semiconductor device substrate according to the third embodiment of the present invention will be described with reference to FIGS. 16, 17 and 18. In FIG. 17 and FIG. 18, the film before processing is represented by the same reference numeral as the element after processing. The semiconductor element substrate 1C according to the present embodiment has a semiconductor element / wiring forming step S10 for forming the semiconductor element structure 2, the wiring 3B connected thereto, and the insulating layer 4 on the Si substrate 20, and the insulating film on the surface. Insulating layer forming step S20B for covering to form a hole in the shape of bonding electrode 7C, electrode forming step S30 for forming bonding electrode 7C inside the hole, and bonding portion forming step S40 for forming recess 8C on the surface , And (semiconductor element manufacturing process S1).

半導体素子・配線形成工程Ｓ１０は、第１、第２実施形態で説明した通りである。また、絶縁層形成工程Ｓ２０Ｂから電極形成工程Ｓ３０までは、公知のダマシン法によるＣｕ配線の形成方法である。絶縁層形成工程Ｓ２０Ｂは、拡散防止絶縁膜５を構成する絶縁膜を成膜する拡散防止絶縁膜成膜工程Ｓ２１と、絶縁層６１を構成する絶縁膜を成膜する絶縁膜成膜工程Ｓ２２と、接合電極７Ｃが形成される領域を空けたレジストマスクＰＲ１を形成するマスク工程Ｓ３３と、絶縁層６１をエッチングする絶縁膜エッチング工程Ｓ２５と、拡散防止絶縁膜５をエッチングする拡散防止絶縁膜エッチング工程Ｓ２６と、レジストマスクＰＲ１を除去するマスク除去工程Ｓ３５と、を行う。電極形成工程Ｓ３０は、金属材料を成膜してバリア膜７１を形成するバリア膜成膜工程Ｓ３１Ａと、Ｃｕを成膜してめっきのためのシード層７２ｓを形成するシード層成膜工程Ｓ３２と、Ｃｕをめっきする電極成膜工程Ｓ３４Ａと、表面を研削、研磨して絶縁膜（絶縁層６１）および接合電極７Ｂの上面を平滑化する平滑化工程Ｓ２３Ａと、を行う。接合部形成工程Ｓ４０は、接合電極７Ｂが露出している領域およびその周囲を空けたレジストマスクＰＲ２を形成するマスク工程Ｓ２７と、絶縁層６１を所定の深さまでエッチングする絶縁膜エッチング工程Ｓ２４Ｂと、レジストマスクＰＲ２を除去するマスク除去工程Ｓ２８と、を行う。   The semiconductor element / wiring formation step S10 is as described in the first and second embodiments. In addition, the insulating layer formation step S20B to the electrode formation step S30 are a method of forming a Cu wiring by a known damascene method. In the insulating layer forming step S20B, a diffusion preventing insulating film forming step S21 for forming an insulating film forming the diffusion preventing insulating film 5 and an insulating film forming step S22 for forming an insulating film forming the insulating layer 61 A mask step S33 of forming a resist mask PR1 in which a region in which the junction electrode 7C is formed is formed, an insulating film etching step S25 of etching the insulating layer 61, and a diffusion preventing insulating film etching step of etching the diffusion preventing insulating film 5; Step S26 and a mask removing step S35 for removing the resist mask PR1 are performed. The electrode forming step S30 includes a barrier film forming step S31A of forming a barrier film 71 by forming a metal material, and a seed layer forming step S32 of forming a seed layer 72s for plating by forming a Cu film. An electrode film forming step S34A for plating Cu, and a smoothing step S23A for grinding and polishing the surface to smooth the upper surfaces of the insulating film (insulating layer 61) and the bonding electrode 7B are performed. The bonding portion forming step S40 includes a mask step S27 of forming a resist mask PR2 in which an area where the bonding electrode 7B is exposed and a periphery thereof are opened, and an insulating film etching step S24B of etching the insulating layer 61 to a predetermined depth. And a mask removing step S28 for removing the resist mask PR2.

（拡散防止絶縁膜成膜工程、絶縁膜成膜工程、マスク工程）
配線３Ｂおよび絶縁層４を形成したＳｉ基板２０上に、第１実施形態と同様に、ＣＶＤ法等で、拡散防止絶縁膜５を構成するＳｉＮ膜を所定の厚さに成膜し（Ｓ２１）、引き続いて、絶縁層６１を構成するＳｉＯ2膜を、前記ＳｉＮ膜との合計で厚さＨ超に成膜する（Ｓ２２）。そして、図１７（ａ）に示すように、ＳｉＯ2膜上に、接合電極７Ｃが形成される径Ｗの領域を空けたレジストマスクＰＲ１を形成する（Ｓ３３）。 (Diffusion prevention insulating film deposition process, insulating film deposition process, mask process)
On the Si substrate 20 on which the wiring 3B and the insulating layer 4 are formed, as in the first embodiment, a SiN film constituting the diffusion preventing insulating film 5 is formed to a predetermined thickness by CVD or the like (S21) Subsequently, a SiO 2 film constituting the insulating layer 61 is formed to a thickness H or more in total with the SiN film (S22). Then, as shown in FIG. 17A, a resist mask PR1 is formed on the SiO 2 film in which a region having a diameter W in which the bonding electrode 7C is to be formed is left (S33).

（絶縁膜エッチング工程、拡散防止絶縁膜エッチング工程、マスク除去工程）
第２実施形態に係る半導体素子基板の製造方法の接合部形成工程Ｓ２０Ａと同様に、ＳｉＯ2膜を、その下の拡散防止絶縁膜５を構成するＳｉＮ膜をエッチングストッパ膜として異方性エッチングで完全に除去する（Ｓ２５）。本実施形態では、ＳｉＯ2膜（絶縁層６１）の厚さ方向全体を異方性エッチングで加工する。次に、露出したＳｉＮ膜を異方性エッチングで完全に除去して（Ｓ２６）、配線３Ｂおよびその周囲の絶縁層４を露出させる。その後、図１７（ｂ）に示すように、レジストマスクＰＲ１を除去する（Ｓ３５）。これにより、絶縁層６１および拡散防止絶縁膜５に、径Ｗの垂直な孔が形成される。 (Insulating film etching process, diffusion preventing insulating film etching process, mask removal process)
Similar to the bonding portion forming step S20A in the method of manufacturing the semiconductor element substrate according to the second embodiment, the SiO 2 film is anisotropically etched using the SiN film forming the diffusion preventing insulating film 5 thereunder as the etching stopper film. Completely remove (S25). In the present embodiment, the entire thickness direction of the SiO 2 film (insulating layer 61) is processed by anisotropic etching. Next, the exposed SiN film is completely removed by anisotropic etching (S26) to expose the wiring 3B and the insulating layer 4 around it. Thereafter, as shown in FIG. 17B, the resist mask PR1 is removed (S35). As a result, vertical holes with a diameter W are formed in the insulating layer 61 and the diffusion preventing insulating film 5.

（バリア膜成膜工程、シード層成膜工程）
Ｔａ等のバリア膜７１を構成する導電性材料を成膜して、絶縁層６１および拡散防止絶縁膜５の孔の内壁等も含めた全面に、バリア膜７１を所定の厚さに成膜する（Ｓ３１Ａ）。引き続いて、シード層７２ｓを構成する金属材料を成膜して、図１７（ｃ）に示すように、バリア膜７１上にシード層７２ｓを積層する。バリア膜成膜工程Ｓ３１Ａは垂直な面上にも成膜し易く、また、シード層成膜工程Ｓ３２はバリア膜７１の表面全体を被覆するように、それぞれスパッタ法等を適用し、連続して行うことができる。シード層７２ｓは、プラグ７２の一部で、Ｃｕのめっきのシード層となるものであり、例えばＣｕで形成される。また、シード層７２ｓの膜厚は、後続の電極成膜工程Ｓ３４Ａで、Ｃｕめっき膜が絶縁層６１および拡散防止絶縁膜５の孔全体に埋め込まれるように、孔の径（接合電極７Ｂの径Ｗ）と深さのアスペクト比等に応じて設計される。 (Barrier film deposition process, seed layer deposition process)
A conductive material constituting the barrier film 71 such as Ta is formed into a film, and the barrier film 71 is formed to a predetermined thickness on the entire surface including the inner walls of the holes of the insulating layer 61 and the diffusion preventing insulating film 5. (S31A). Subsequently, a metal material forming the seed layer 72s is formed into a film, and as shown in FIG. 17C, the seed layer 72s is stacked on the barrier film 71. The barrier film forming step S31A can be easily formed on a vertical surface, and the seed layer forming step S32 can be continuously applied sputtering or the like so as to cover the entire surface of the barrier film 71. It can be carried out. The seed layer 72s is a part of the plug 72 and serves as a seed layer of Cu plating, and is formed of, for example, Cu. Further, the film thickness of the seed layer 72s is the diameter of the hole (the diameter of the bonding electrode 7B so that the Cu plating film is embedded in the entire hole of the insulating layer 61 and the diffusion preventing insulating film 5 in the subsequent electrode film forming step S34A. It is designed according to the aspect ratio etc. of W) and depth.

（電極成膜工程、平滑化工程）
図１７（ｄ）に示すように、Ｃｕをめっきにより絶縁層６１および拡散防止絶縁膜５の孔に埋め込む（Ｓ３４Ａ）。めっきは、電解めっきや無電解めっきを適用することができる。その後、ＣＭＰ法により、表面のＣｕ膜、Ｔａ膜を順次研削してその下のＳｉＯ2膜（絶縁層６１）を露出させる。図１８（ａ）に示すように、さらに研磨して、接合電極７Ｃを厚さＨPLGとし、かつ所定の表面粗さに平滑化し、また、絶縁層６１の表面を研磨して、拡散防止絶縁膜５との合計厚さＨとし、かつ所定の表面粗さに平滑化する（Ｓ２３Ａ）。拡散防止絶縁膜５と絶縁層６１の合計の厚さＨと接合電極７Ｃの厚さＨPLGは、ＣＭＰのスラリの成分や研磨パッド等によって個別に制御することができる。 (Electrode deposition process, smoothing process)
As shown in FIG. 17D, Cu is embedded in the holes of the insulating layer 61 and the diffusion preventing insulating film 5 by plating (S34A). As plating, electrolytic plating or electroless plating can be applied. Thereafter, the Cu film and the Ta film on the surface are sequentially ground by the CMP method to expose the underlying SiO 2 film (insulation layer 61). As shown in FIG. 18A, the electrode 7C is further polished to a thickness H PLG and smoothed to a predetermined surface roughness, and the surface of the insulating layer 61 is polished to prevent diffusion and insulation. The total thickness H with the film 5 is taken and smoothed to a predetermined surface roughness (S23A). The total thickness H of the diffusion preventing insulating film 5 and the insulating layer 61 and the thickness H PLG of the bonding electrode 7C can be individually controlled by the component of the slurry of CMP, the polishing pad, and the like.

（マスク工程、絶縁膜エッチング工程、マスク除去工程）
図１８（ｂ）に示すように、接合電極７Ｃが露出した領域上に、径（Ｗ＋２Ｇ）の領域を空けたレジストマスクＰＲ２を形成する（Ｓ２７）。図１８（ｃ）に示すように、絶縁膜エッチング工程Ｓ２５と同様に、異方性エッチングでＳｉＯ2膜のみを深さＤまでエッチングして、絶縁層６１を成形する（Ｓ２４Ｂ）。異方性エッチングは、接合電極７Ｃ、特にプラグ７２を構成するＣｕに対する選択比の高い、Ｃｕをまったくエッチングしない方法が好ましい。その後、レジストマスクＰＲ２を除去して（Ｓ２８）、半導体素子基板１Ｃが得られる。 (Mask process, insulating film etching process, mask removal process)
As shown in FIG. 18B, a resist mask PR2 in which a region of diameter (W + 2G) is opened is formed on the region where the bonding electrode 7C is exposed (S27). As shown in FIG. 18C, as in the insulating film etching step S25, only the SiO 2 film is etched to a depth D by anisotropic etching to form the insulating layer 61 (S24B). The anisotropic etching is preferably a method which does not etch Cu at all, which has a high selectivity to the bonding electrode 7 C, particularly to the Cu constituting the plug 72. Thereafter, the resist mask PR2 is removed (S28), and the semiconductor element substrate 1C is obtained.

このように、絶縁層６１を２回に分けて加工することにより、バリア膜付きの所望の厚さＨPLGの接合電極７Ｃを備え、所望の間隙Ｇと深さＤの凹み８Ｃが表面に形成された半導体素子基板１Ｃが得られる。なお、レジストマスクＰＲ２は、接合電極７Ｃが露出した領域をさらに覆う、すなわち接合電極７Ｃが露出した領域の周囲のみを覆う環型に空いたパターンでもよい。このようなレジストマスクＰＲ２は、位置合わせ（アライメント）のずれで接合電極７Ｃのすぐ外側を被覆して、表面近傍で接合電極７Ｃの側面にＳｉＯ2膜（絶縁層６１）を残すことのないように、接合電極７Ｃが露出した径Ｗの領域よりも一回り小さな領域を覆うことが好ましい。得られた半導体素子基板１Ｃは、第１実施形態の接合工程Ｓ２と同様に、互いに接合電極７Ｃが左右対称に配置された２枚で接合して接合型半導体素子１０Ｃとすることができる。また、半導体素子基板１Ｃは、平面視で、互いに接合電極７（７Ｂ，７Ｃ）が左右対称に配置されていれば、第１、第２実施形態に係る半導体素子基板１，１Ａ，１Ｂと接合することができる。 Thus, by processing the insulating layer 61 in two steps, a junction electrode 7C of a desired thickness H PLG with a barrier film is provided, and a desired gap G and a recess 8C of a depth D are formed on the surface. Thus obtained semiconductor element substrate 1C is obtained. The resist mask PR2 may be an open pattern further covering the area where the bonding electrode 7C is exposed, that is, only the periphery of the area where the bonding electrode 7C is exposed. Such a resist mask PR2 covers the immediate outside of the bonding electrode 7C due to misalignment, so as not to leave the SiO 2 film (insulating layer 61) on the side surface of the bonding electrode 7C in the vicinity of the surface. It is preferable to cover an area slightly smaller than the area of the diameter W where the bonding electrode 7C is exposed. Similar to the bonding step S2 of the first embodiment, the obtained semiconductor element substrate 1C can be joined to form the junction-type semiconductor element 10C by joining two junction electrodes 7C arranged symmetrically with each other. The semiconductor element substrate 1C is joined to the semiconductor element substrates 1, 1A and 1B according to the first and second embodiments as long as the junction electrodes 7 (7B and 7C) are arranged symmetrically in plan view. can do.

（変形例１）
第１実施形態の変形例に係る半導体素子基板１Ａ（図８参照）のように、ＳｉＯ2へ拡散し難い金属材料を最上層に備え、かつ平面視で、接合電極７Ｃよりも大きな形状に形成されたパッド部３ｐを備える配線３Ａであれば、拡散防止絶縁膜５が不要である。すなわち、その製造方法の絶縁層形成工程Ｓ２０Ｂにおいて、拡散防止絶縁膜成膜工程Ｓ２１および拡散防止絶縁膜エッチング工程Ｓ２６を行わない。 (Modification 1)
As in a semiconductor element substrate 1A (see FIG. 8) according to a modification of the first embodiment, a metal material which hardly diffuses into SiO 2 is provided in the uppermost layer, and formed in a shape larger than the bonding electrode 7C in plan view In the case of the wiring 3A provided with the pad portion 3p, the diffusion preventing insulating film 5 is unnecessary. That is, in the insulating layer forming step S20B of the manufacturing method, the diffusion preventing insulating film forming step S21 and the diffusion preventing insulating film etching step S26 are not performed.

（変形例２）
第３実施形態に係る半導体素子基板１Ｃにおいては、レジストマスクＰＲ２のパターン形状次第で、表面の凹み８Ｃを、接合電極７Ｃの寸法と独立した所望の平面視形状に形成することができる。したがって、半導体素子基板１Ｃは、接合面積を確保することのできる程度に、隣り合う２以上の接合電極７Ｃを内包する１つの凹みを形成してもよい。さらに、図１９に示すように、凹みを、配列されている接合電極７Ｃを１列ないし複数列ずつまとめて連結させた溝状の凹み８Ｄに形成し、その両端または一端をウェハまたはチップの端まで延設してもよい。このような溝状の凹み８Ｄを表面に形成された半導体素子基板１Ｄを接合した接合型半導体素子１０Ｃ（図示省略）は、形成された空隙８０Ｃが端面で開口し、閉じた空間にならないので、接合後にこの空隙８０Ｃに不活性ガスや樹脂等を封入すればよく、大気雰囲気で接合することができる。また、半導体素子基板１Ｄは、半導体素子基板１Ｃ、または第１、第２実施形態に係る半導体素子基板１，１Ａ，１Ｂと接合しても、同様に空隙８０Ｃが閉じた空間にならずに端面で開口するので、大気雰囲気で接合することができる。 (Modification 2)
In the semiconductor element substrate 1C according to the third embodiment, the recess 8C on the surface can be formed into a desired plan view shape independent of the size of the bonding electrode 7C depending on the pattern shape of the resist mask PR2. Therefore, the semiconductor element substrate 1C may be formed with a single recess including two or more adjacent bonding electrodes 7C to such an extent that a bonding area can be secured. Further, as shown in FIG. 19, a recess is formed in a groove-like recess 8D in which bonding electrodes 7C arranged are connected together in one or a plurality of rows, and both ends or one end thereof is the end of the wafer or chip It may extend up to. In the junction type semiconductor device 10C (not shown) obtained by joining the semiconductor device substrate 1D having the groove-like recess 8D formed on the surface, the formed air gap 80C is opened at the end face and does not become a closed space, After bonding, the void 80C may be filled with an inert gas, a resin or the like, and bonding can be performed in the air. Further, even when the semiconductor element substrate 1D is joined to the semiconductor element substrate 1C or the semiconductor element substrates 1, 1A and 1B according to the first and second embodiments, the end face is not the same as the space where the air gap 80C is closed. Can be bonded in the atmosphere.

（変形例３）
第３実施形態においては、絶縁膜エッチング工程Ｓ２４Ｂを等方性エッチングで行って、表面に凹みを形成することもできる。マスク工程Ｓ２７で、図２０に示すように、径（Ｗ＋２Ｇ0）の領域を空けたレジストマスクＰＲ２Ａを形成する（０＜Ｇ0＜Ｇ）。Ｇ0の値は特に規定されないが、レジストマスクＰＲ２Ａのアライメントのずれも含めて、平面視で接合電極７Ｃの周囲が全周にわたって確実に空くように設計する。本変形例に係る半導体素子基板１Ｅは、図１０に示す第２実施形態に係る半導体素子基板１Ｂのように、断面視で接合電極７Ｃの側面に１／４円弧（楕円弧を含む）を描く形状の穴が絶縁層６１に形成されて、表面に広がって開口した凹み８Ａが形成され、深さＤが、Ｄ≒ｘ×(Ｇ−Ｇ0)となる（ｘ：絶縁層６１の等方性エッチングのエッチングファクター）。また、表面における凹み８Ａの間隙Ｇが、接合における位置ずれの最大値ｓMAXに基づいて、√[(Ｇ−Ｇ0)2−(ΔＨPLG／ｘ)2]＞ｓMAXに設計される。なお、半導体素子基板１Ｅは、凹み８Ａの形状以外は、第３実施形態に係る半導体素子基板１Ｃと同様の構造である。等方性エッチングで絶縁層６１を成形することで、使用するレジストマスクＰＲ２ＡがレジストマスクＰＲ１に近い形状になり、レジストマスクＰＲ１を形成するためのレチクル（フォトマスク）を、露光条件等を変えて流用し得る。 (Modification 3)
In the third embodiment, the insulating film etching step S24B may be performed by isotropic etching to form a recess on the surface. In the mask step S27, as shown in FIG. 20, a resist mask PR2A in which a region of diameter (W + 2G 0 ) is left is formed (0 <G 0 <G). Although the value of G 0 is not particularly defined, it is designed to ensure that the periphery of the bonding electrode 7 C is completely open in a plan view including the misalignment of the resist mask PR 2 A. The semiconductor element substrate 1E according to the present modification has a shape that draws a quarter arc (including an elliptic arc) on the side surface of the bonding electrode 7C in a cross sectional view like the semiconductor element substrate 1B according to the second embodiment shown in FIG. Is formed in the insulating layer 61 to form a recess 8A which is spread and opened on the surface, and the depth D becomes D ≒ x × (G−G 0 ) (x: isotropic of the insulating layer 61 Etching factor of etching). Further, the gap G of the recess 8A on the surface is designed to be √ [(G−G 0 ) 2 − (ΔH PLG / x) 2 ]> s MAX based on the maximum value s MAX of the positional deviation at the junction. The semiconductor element substrate 1E has the same structure as the semiconductor element substrate 1C according to the third embodiment except for the shape of the recess 8A. By forming the insulating layer 61 by isotropic etching, the resist mask PR2A used becomes a shape close to the resist mask PR1, and the reticle (photo mask) for forming the resist mask PR1 is changed in exposure conditions etc. It can be diverted.

以上のように、本発明の第３実施形態およびその変形例に係る接合型半導体素子によれば、所望の厚さおよびアスペクト比で、表面粗さの小さなＣｕ電極を生産性よく形成しつつ、第１、第２実施形態と同様に、接合強度を十分に確保しつつ、接合の位置ずれに起因する信頼性低下等の不良を低減することができる。   As described above, according to the junction-type semiconductor device according to the third embodiment of the present invention and the modification thereof, a Cu electrode with a small surface roughness is formed with high productivity with desired thickness and aspect ratio. Similar to the first and second embodiments, it is possible to reduce defects such as reliability decrease due to misalignment of the junction while securing sufficient bonding strength.

〔第４実施形態〕
第１、第２実施形態の共通の変形例として説明したように、本発明に係る接合型半導体素子は、絶縁体と柱状電極とで接合面の高さ位置が異なっていてもよい。このような接合型半導体素子を構成する一組の半導体素子基板の一方は、接合電極を突出させて表面に凹みのない構造とすることもできる。以下、第４実施形態に係る接合型半導体素子およびこれを構成する半導体素子基板について説明する。第１、第２、第３実施形態と同じ要素については同じ符号を付し、説明を省略する。 Fourth Embodiment
As described as a common modification of the first and second embodiments, in the junction-type semiconductor device according to the present invention, the height position of the junction surface may be different between the insulator and the columnar electrode. One of the pair of semiconductor element substrates constituting such a junction-type semiconductor element can have a structure in which the junction electrode is made to protrude and the surface is not dented. Hereinafter, a junction-type semiconductor device according to the fourth embodiment and a semiconductor device substrate constituting the same will be described. The same elements as those in the first, second, and third embodiments are given the same reference numerals and descriptions thereof will be omitted.

本発明の第４実施形態に係る接合型半導体素子１０Ｅは、図２１に示す接合面近傍以外は、図２に示す第１実施形態に係る接合型半導体素子１０と同様の構造である。接合型半導体素子１０Ｅは、絶縁体６０の高さ（厚さ）方向における一部の接合面を含む領域に空隙８０Ｅを有し、空隙８０Ｅのそれぞれを上下に貫通するように柱状電極７０Ｅが設けられる。詳しくは、空隙８０Ｅは、絶縁体６０の下側の約半分の領域に設けられ、断面形状が、図２に示す第１実施形態に係る接合型半導体素子１０の空隙８０の下半分と同じ形状である。したがって、柱状電極７０Ｅが空隙８０Ｅの上側により長く（高く）突き出されている。接合型半導体素子１０Ｅは、接合面の高さ位置が、図２１に一点鎖線で示すように、絶縁体６０においては空隙８０Ｅの上端であり、柱状電極７０Ｅにおいてはそれよりも下方の空隙８０Ｅの中間位置である。本発明の第４実施形態に係る接合型半導体素子１０Ｅを構成する一組の半導体素子基板（本発明の第４実施形態に係る半導体素子基板）１Ｆ，１Ｇは、図２２（ａ）、（ｂ）に示す、絶縁体６０および柱状電極７０Ｅを構成する表面近傍の構造が互いに異なり、それ以外は、図２および図３に示す半導体素子基板１と同様の構造である。以下、本実施形態に係る接合型半導体素子を構成する各要素について、第１、第２、第３実施形態と異なるものについて詳細に説明する。   The junction-type semiconductor device 10E according to the fourth embodiment of the present invention has the same structure as that of the junction-type semiconductor device 10 according to the first embodiment shown in FIG. 2 except in the vicinity of the bonding surface shown in FIG. In the junction-type semiconductor device 10E, a void 80E is provided in a region including a part of the bonding surface in the height (thickness) direction of the insulator 60, and the columnar electrode 70E is provided to penetrate each of the voids 80E vertically. Be Specifically, the air gap 80E is provided in about a half area under the insulator 60, and the cross-sectional shape is the same as the lower half of the air gap 80 of the junction-type semiconductor device 10 according to the first embodiment shown in FIG. It is. Therefore, the columnar electrode 70E is projected longer (higher) above the air gap 80E. In the junction-type semiconductor device 10E, the height position of the bonding surface is at the upper end of the air gap 80E in the insulator 60 and in the air gap 80E below it in the columnar electrode 70E as shown by the alternate long and short dash line in FIG. It is an intermediate position. A set of semiconductor element substrates (semiconductor element substrates according to the fourth embodiment of the present invention) 1F and 1G constituting the junction-type semiconductor element 10E according to the fourth embodiment of the present invention are shown in FIGS. The structures in the vicinity of the surface constituting the insulator 60 and the columnar electrode 70E are different from each other, and the other structure is the same as that of the semiconductor element substrate 1 shown in FIGS. The elements of the junction-type semiconductor device according to this embodiment that are different from the first, second, and third embodiments will be described in detail below.

半導体素子基板１Ｆは、表層に半導体素子構造２を形成されたＳｉ基板２０（図３参照）と、半導体素子構造２に接続する配線３Ｂと、Ｓｉ基板２０上を被覆して配線３Ｂ間を絶縁する絶縁層４と、絶縁層４上に積層された拡散防止絶縁膜５と、拡散防止絶縁膜５に積層されて最表面に形成される絶縁層６１と、一部の配線３Ｂの上面に接続して表面に突出して露出する柱状の接合電極７Ｃと、を備える。すなわち、半導体素子基板１Ｆは、図１５に示す第３実施形態に係る半導体素子基板１Ｃに対して、表面に凹み８Ｃがなく、接合電極７Ｃが周囲（絶縁層６１）よりも高く突出した構造である。   The semiconductor element substrate 1F covers the Si substrate 20 with the Si substrate 20 (see FIG. 3) having the semiconductor element structure 2 formed on the surface, the wiring 3B connected to the semiconductor element structure 2, and insulates the wiring 3B from each other. Connected to the upper surface of a part of the wiring 3B and the insulating layer 61 formed on the outermost surface, the insulating layer 4 formed on the insulating layer 4, the diffusion preventing insulating film 5 stacked on the insulating layer 4, and the insulating layer 61 stacked on the diffusion preventing insulating film 5 And a columnar bonding electrode 7C which protrudes and is exposed on the surface. That is, the semiconductor element substrate 1F has a structure in which there is no recess 8C on the surface of the semiconductor element substrate 1C according to the third embodiment shown in FIG. 15 and the junction electrode 7C protrudes higher than the periphery (insulating layer 61). is there.

絶縁層６１は、接合電極７Ｃを貫通させる接合電極７Ｃと同径Ｗの孔が形成されている以外は平坦で、表面がハイブリッド接合に好適となるように平滑である。接合電極７Ｃは、第３実施形態にて説明した通り、プラグ７２と、上面以外を被覆するバリア膜７１とを備える。半導体素子基板１Ｆにおいては、接合電極７Ｃは、厚さＨPLG1が拡散防止絶縁膜５と絶縁層６１の合計の厚さＨ1よりも十分に大きく形成される（ΔＨPLG1＝ＨPLG1−Ｈ1＞０）。接合電極７Ｃの突出高さΔＨPLG1は、具体的には２０ｎｍ以上が好ましく、５０ｎｍ以上がより好ましい。本実施形態において、接合電極７Ｃの突出高さΔＨPLG1は、後記するように、接合電極７Ｃがダマシン法で形成される際のＣＭＰによる接合電極７Ｃ（Ｃｕ）と絶縁層６１（ＳｉＯ2）のそれぞれの研磨によって調整される。 The insulating layer 61 is flat except that a hole having the same diameter W as the bonding electrode 7C penetrating the bonding electrode 7C is formed, and the surface is smooth so as to be suitable for hybrid bonding. As described in the third embodiment, the bonding electrode 7C includes the plug 72 and the barrier film 71 covering the surface other than the upper surface. In semiconductor element substrate 1F, junction electrode 7C is formed to have a thickness H PLG1 sufficiently larger than a total thickness H 1 of diffusion preventing insulating film 5 and insulating layer 61 (ΔH PLG1 = H PLG1 -H 1 > 0). Specifically, the protrusion height ΔH PLG1 of the bonding electrode 7C is preferably 20 nm or more, and more preferably 50 nm or more. In the present embodiment, the protrusion height ΔH PLG1 of the bonding electrode 7C is, as described later, between the bonding electrode 7C (Cu) and the insulating layer 61 (SiO 2 ) by CMP when the bonding electrode 7C is formed by a damascene method. It is adjusted by each grinding.

半導体素子基板１Ｇは、表層に半導体素子構造２を形成されたＳｉ基板２０（図３参照）と、半導体素子構造２に接続する配線３Ｂと、Ｓｉ基板２０上を被覆して配線３Ｂ間を絶縁する絶縁層４と、絶縁層４上に積層された拡散防止絶縁膜５と、拡散防止絶縁膜５に積層されて最表面に形成される絶縁層６１と、一部の配線３Ｂの上面に接続して表面に露出する柱状の接合電極７Ｂと、を備え、表面に凹み（ポケット）８が形成されている。すなわち、半導体素子基板１Ｇは、図３に示す第１実施形態に係る半導体素子基板１に対して、接合電極７（プラグ７２）の下にバリア膜７１を設けた接合電極７Ｂとし、絶縁層６１の上面よりも低く形成した構造である。   The semiconductor element substrate 1G covers the Si substrate 20 with the Si substrate 20 (see FIG. 3) having the semiconductor element structure 2 formed on the surface, the wiring 3B connected to the semiconductor element structure 2, and insulates the wiring 3B from each other. Connected to the upper surface of a part of the wiring 3B and the insulating layer 61 formed on the outermost surface, the insulating layer 4 formed on the insulating layer 4, the diffusion preventing insulating film 5 stacked on the insulating layer 4, and the insulating layer 61 stacked on the diffusion preventing insulating film 5 And a columnar bonding electrode 7B exposed on the surface, and a recess (pocket) 8 is formed on the surface. That is, the semiconductor element substrate 1G is a junction electrode 7B in which the barrier film 71 is provided under the junction electrode 7 (plug 72) with respect to the semiconductor element substrate 1 according to the first embodiment shown in FIG. It is a structure formed lower than the upper surface of.

絶縁層６１の構造および表面の凹み８の形状は、第１実施形態にて説明した通りであるが、本実施形態においては、絶縁層６１の表面における接合電極７Ｂとの間隙Ｇは、接合における位置ずれの最大値ｓMAX、半導体素子基板１Ｆの接合電極７Ｃの突出高さΔＨPLG1に基づいて、√[Ｇ2−(ΔＨPLG1／ｘ)2]＞ｓMAXに設計される（ｘ：絶縁層６１の等方性エッチングのエッチングファクター）。このマージン（√[Ｇ2−(ΔＨPLG1／ｘ)2]−ｓMAX）は、第１実施形態と同様、２０ｎｍ以上に設計されることが好ましく、５０ｎｍ以上に設計されることがより好ましい。接合電極７Ｂは、その下の絶縁層４へプラグ７２からＣｕを拡散させないために、バリア膜７１を備えた構造である。半導体素子基板１Ｇにおいては、接合電極７Ｂは、厚さＨPLG2が拡散防止絶縁膜５と絶縁層６１の合計の厚さＨ2よりも小さく形成され（ΔＨPLG2＝ＨPLG2−Ｈ2＜０）、その差（接合電極７Ｂのマイナス方向への突出高さ）ΔＨPLG2は、絶対値で半導体素子基板１Ｆの接合電極７Ｃの突出高さΔＨPLG1と一致、または僅かな差で小さく、この差を５〜１０ｎｍの範囲とすることが好ましい（ΔＨPLG1≧−ΔＨPLG2、ΔＨPLG1−(−ΔＨPLG2)＝５〜１０ｎｍ）。さらに、接合電極７Ｂの突出高さΔＨPLG2は、絶対値で２０ｎｍ以上（ΔＨPLG2≦−２０ｎｍ）であることが好ましく、４０ｎｍ以上であることがより好ましい。本実施形態において、接合電極７Ｂの突出高さΔＨPLG2は、後記するように、接合電極７Ｂを構成する電極材料の成膜厚さによって調整される。 The structure of the insulating layer 61 and the shape of the recess 8 on the surface are as described in the first embodiment, but in the present embodiment, the gap G between the surface of the insulating layer 61 and the junction electrode 7B is the junction Maximum displacement s MAX , protrusion height ΔH PLG1 of junction electrode 7C of semiconductor element substrate 1F, designed as 基 づ い [G 2 − (ΔH PLG 1 / x) 2 ]> s MAX (x: insulation Etch factor of isotropic etching of layer 61). The margin ( 第 [G 2 − (ΔH PLG 1 / x) 2 ] −s MAX ) is preferably designed to be 20 nm or more, more preferably 50 nm or more, as in the first embodiment. The bonding electrode 7B has a structure including a barrier film 71 in order to prevent the diffusion of Cu from the plug 72 into the insulating layer 4 thereunder. In semiconductor element substrate 1G, junction electrode 7B is formed such that thickness H PLG2 is smaller than total thickness H 2 of diffusion preventing insulating film 5 and insulating layer 61 (ΔH PLG2 = H PLG2 -H 2 <0). The difference (protrusion height of junction electrode 7B in the negative direction) ΔH PLG2 is, in absolute value, in agreement with or slightly smaller than the projection height ΔH PLG1 of junction electrode 7C of semiconductor element substrate 1F, this difference The range of 5 to 10 nm is preferable (ΔH PLG1 PL− ΔH PLG2 , ΔH PLG1 − (− ΔH PLG2 ) = 5 to 10 nm). Furthermore, the protrusion height ΔH PLG2 of the bonding electrode 7B is preferably 20 nm or more (ΔH PLG2 ≦ −20 nm) in absolute value, and more preferably 40 nm or more. In the present embodiment, the protrusion height ΔH PLG2 of the bonding electrode 7B is adjusted by the film thickness of the electrode material constituting the bonding electrode 7B, as described later.

〔接合型半導体素子の製造方法〕
半導体素子基板１Ｆは、図１６、図１７および図１８（ａ）に示す第３実施形態に係る半導体素子基板の製造方法における絶縁層形成工程Ｓ２０Ｂから電極形成工程Ｓ３０までの工程によって、すなわち公知のダマシン法により製造することができる。本実施形態においては、最後の平滑化工程Ｓ２３Ａにおいて、絶縁層６１（ＳｉＯ2膜）を接合電極７Ｃ（プラグ７２（Ｃｕ）、バリア膜７１）よりも深く研磨して、接合電極７Ｃを突出させる。半導体素子基板１Ｇは、図１１、図１２および図１３に示す第２実施形態に係る半導体素子基板の製造方法において、絶縁膜エッチング工程Ｓ２４Ａ，Ｓ２５に代えて図６（ｃ）に示す第１実施形態の絶縁膜等方性エッチング工程Ｓ２４を行って、等方性エッチングのみで絶縁層６１を加工して製造することができる。また、本実施形態においては、電極成膜工程Ｓ３４で、プラグ７２を形成するＣｕの厚さを抑える。そして、得られた半導体素子基板１Ｆ，１Ｇは、第１実施形態の接合工程Ｓ２と同様に接合して接合型半導体素子１０Ｅとすることができる。 [Method of manufacturing junction type semiconductor device]
The semiconductor element substrate 1F is known by the steps from the insulating layer forming step S20B to the electrode forming step S30 in the method of manufacturing the semiconductor element substrate according to the third embodiment shown in FIGS. 16, 17 and 18A, that is, It can be manufactured by the damascene method. In the present embodiment, in the final smoothing step S23A, the insulating layer 61 (SiO 2 film) is polished deeper than the bonding electrode 7C (plug 72 (Cu), barrier film 71) to project the bonding electrode 7C. . The semiconductor element substrate 1G is the first embodiment shown in FIG. 6C in place of the insulating film etching steps S24A and S25 in the method of manufacturing a semiconductor element substrate according to the second embodiment shown in FIGS. 11, 12 and 13. By performing the insulating film isotropic etching step S24 in the form, the insulating layer 61 can be processed and manufactured only by isotropic etching. Further, in the present embodiment, the thickness of Cu forming the plug 72 is suppressed in the electrode film forming step S34. Then, the obtained semiconductor element substrates 1F and 1G can be joined in the same manner as the joining step S2 of the first embodiment to form a junction-type semiconductor element 10E.

このように、半導体素子基板１Ｆは、表面に突出させた接合電極７Ｃを、第３実施形態のように厚膜化し易いダマシン法で形成することにより、公知のＣｕ配線の形成方法から工程等を増やすことなく製造することができる。反対に、接合電極７Ｂの厚さの小さい半導体素子基板１Ｇは、第１、第２実施形態と同様に、接合電極７Ｂを形成するためのレジストマスクＰＲ１で凹みを形成することができ、また、接合電極７Ｂの厚さが小さいので、成膜速度の遅い真空蒸着法でも生産性が低下せず、接合電極７Ｂを所望の表面粗さに形成し易い。   As described above, the semiconductor element substrate 1F has the bonding electrode 7C protruding from the surface formed by the damascene method which can easily be thickened as in the third embodiment, whereby the known Cu wiring formation method to the steps, etc. are carried out. It can be manufactured without increasing. On the contrary, in the semiconductor element substrate 1G having a small thickness of the bonding electrode 7B, a recess can be formed by the resist mask PR1 for forming the bonding electrode 7B, as in the first and second embodiments. Since the thickness of the bonding electrode 7B is small, productivity is not reduced even by a vacuum deposition method with a slow film forming rate, and the bonding electrode 7B can be easily formed to a desired surface roughness.

（変形例）
半導体素子基板１Ｇは、拡散防止絶縁膜５およびバリア膜７１を備える構造としたが、第１、第２実施形態およびその変形例にて説明したように、それぞれ、配線３（３Ａ，３Ｂ）のパッド部３ｐの平面視形状および材料によっては設けなくてもよい。また、半導体素子基板１Ｇは、半導体素子基板１Ｆのように、第３実施形態に係る半導体素子基板１Ｃと同じ方法で、平滑化工程Ｓ２３Ａにおいて接合電極７Ｃの方をより深く研磨して製造してもよい。さらにこの場合、第３実施形態の変形例（図１９参照）として説明したように、表面の凹みを溝状に形成して、空隙が端面に開口した接合型半導体素子とすることができる。 (Modification)
Although the semiconductor element substrate 1G has a structure including the diffusion preventing insulating film 5 and the barrier film 71, as described in the first and second embodiments and the modification thereof, each of the wirings 3 (3A, 3B) is used. It may not be provided depending on the plan view shape and material of the pad portion 3p. The semiconductor element substrate 1G is manufactured by polishing the bonding electrode 7C more deeply in the smoothing step S23A by the same method as the semiconductor element substrate 1C according to the third embodiment, like the semiconductor element substrate 1F. It is also good. Furthermore, in this case, as described as the modification of the third embodiment (see FIG. 19), the recess on the surface can be formed in a groove shape, and a void can be made into the junction type semiconductor element opened at the end face.

バリア膜７１付きの接合電極７Ｃを備える半導体素子基板１Ｆに代えて、図２２（ｃ）に示すように、パッド部３ｐが接合電極７よりも大きい配線３を備え、平滑な絶縁層４Ａとすることで、絶縁層６１を設けずに、Ｃｕ（プラグ７２）のみからなる接合電極７を備える半導体素子基板１Ｈを、接合型半導体素子１０Ｅを構成する一組の一方とすることもできる。このような半導体素子基板１Ｈは、幅（径）Ｗ２（＞Ｗ）のパッド部３ｐのコア部３２が接合面に露出しているため、接合される半導体素子基板１Ｇは、表面の凹みの開口幅（Ｗ＋２Ｇ）の間隙Ｇを、Ｇ’（＝Ｇ−(Ｗ２−Ｗ)／２）に置き換えた√[Ｇ’2−(ΔＨPLG1／ｘ)2]＞ｓMAXから設計される。また、ΔＨPLG1＝ＨPLG1である。 Instead of the semiconductor element substrate 1F provided with the junction electrode 7C with the barrier film 71, as shown in FIG. 22C, the pad portion 3p is provided with the wiring 3 larger than the junction electrode 7 to form a smooth insulating layer 4A. Thus, without providing the insulating layer 61, the semiconductor element substrate 1H provided with the junction electrode 7 consisting only of Cu (plug 72) can be used as one of a pair constituting the junction type semiconductor element 10E. In such a semiconductor element substrate 1H, since the core portion 32 of the pad portion 3p having a width (diameter) W2 (> W) is exposed to the bonding surface, the semiconductor element substrate 1G to be bonded has an opening on the surface The gap G of width (W + 2G) is designed from PL [G ′ 2 − (ΔH PLG 1 / x) 2 ]> s MAX in which G ′ (= G− (W 2 −W) / 2) is replaced. Also, ΔH PLG1 = H PLG1 .

半導体素子基板１Ｈは、第１実施形態に係る半導体素子基板の製造方法における半導体素子・配線形成工程Ｓ１０の最後に、ＣＭＰ法で絶縁層４Ａおよびパッド部３ｐを接合に好適な平滑な表面に形成して製造することができる。そしてその次に、接合電極７が形成される領域を空けたレジストマスクＰＲ１を形成するマスク工程Ｓ３３を行い、その上からＣｕを成膜する電極成膜工程Ｓ３４を行い、レジストマスクＰＲ１をその上のＣｕ膜ごと除去するマスク除去工程Ｓ３５を行う。電極成膜工程Ｓ３４は、下地であるパッド部３ｐの表面の平滑性が確保される方法であればよい。あるいは、パッド部３ｐのコア部３２をシード層としてめっきで接合電極７（プラグ７２）を形成して、その後、表面（上面）を研磨してもよい。半導体素子基板１Ｈは、半導体素子基板１Ｆのように、ＣＭＰ法で接合電極７（７Ｃ）を突出させないので、接合電極７の突出高さΔＨPLG1（＝ＨPLG1）を高く形成することが容易である。 The semiconductor element substrate 1H is formed on the smooth surface suitable for bonding the insulating layer 4A and the pad portion 3p by the CMP method at the end of the semiconductor element / wiring formation step S10 in the method of manufacturing the semiconductor element substrate according to the first embodiment. Can be manufactured. Then, a mask step S33 of forming a resist mask PR1 in which a region where the bonding electrode 7 is to be formed is formed is performed, and an electrode film forming step S34 of forming Cu from above is performed to form a resist mask PR1 thereon. Mask removal step S35 for removing the entire Cu film. The electrode film forming step S34 may be any method as long as the smoothness of the surface of the pad portion 3p which is the base is ensured. Alternatively, the bonding electrode 7 (plug 72) may be formed by plating using the core portion 32 of the pad portion 3p as a seed layer, and then the surface (upper surface) may be polished. Like the semiconductor element substrate 1F, the semiconductor element substrate 1H does not allow the bonding electrode 7 (7C) to protrude by the CMP method, so it is easy to form the protrusion height ΔH PLG1 (= H PLG1 ) of the bonding electrode 7 high. is there.

以上のように、本発明の第４実施形態およびその変形例に係る接合型半導体素子によれば、構成する一組の半導体素子の一方のみに凹みを形成することにより、第１、第２実施形態と同様に、接合強度を十分に確保しつつ、接合の位置ずれに起因する信頼性低下等の不良を低減することができる。   As described above, according to the junction-type semiconductor device according to the fourth embodiment of the present invention and the modification thereof, the first and second embodiments can be implemented by forming a recess only in one of a pair of semiconductor devices to be configured. Similar to the embodiment, it is possible to reduce defects such as reliability decrease due to misalignment of the bonding while securing sufficient bonding strength.

〔第５実施形態〕
第１〜第４実施形態に係る接合型半導体素子は、いずれもＳｉ基板の表側同士を対面させたＦａｃｅ−ｔｏ−Ｆａｃｅ接合であるが、Ｆａｃｅ−ｔｏ−Ｂａｃｋ接合に適用することもできる。以下、第５実施形態に係る接合型半導体素子およびこれを構成する半導体素子基板について説明する。第１〜第４実施形態と同じ要素については同じ符号を付し、説明を省略する。 Fifth Embodiment
The junction-type semiconductor devices according to the first to fourth embodiments are face-to-face junctions in which the front sides of the Si substrates face each other, but can be applied to face-to-back junctions. Hereinafter, a junction-type semiconductor device according to the fifth embodiment and a semiconductor device substrate constituting the same will be described. The same elements as those in the first to fourth embodiments are given the same reference numerals and descriptions thereof will be omitted.

本発明の第５実施形態に係る接合型半導体素子１０Ｆは、図２３に示すように、それぞれが表層に半導体素子構造２を形成されたＳｉ基板２０を備える３枚の半導体素子基板１１，１３，１２を下から順に積層して備える。半導体素子基板１２と半導体素子基板１３は、図２に示す接合型半導体素子１０と同様に、それぞれのＳｉ基板２０の半導体素子構造２を形成した側同士が対面するように、表面（上面）同士で接合する（Ｆａｃｅ−ｔｏ−Ｆａｃｅ接合）。一方、半導体素子基板１１と半導体素子基板１３は、半導体素子基板１１の表面と半導体素子基板１３の裏面とが接合する（Ｆａｃｅ−ｔｏ−Ｂａｃｋ接合）。最上層、最下層の半導体素子基板１２，１１の構造は、第１実施形態に係る半導体素子基板１と同様である。以下、半導体素子基板１３（１Ｉ）について説明する。第１〜第４実施形態と同じ要素については同じ符号を付し、説明を省略する。   The junction-type semiconductor device 10F according to the fifth embodiment of the present invention, as shown in FIG. 23, includes three semiconductor device substrates 11, 13 each having a Si substrate 20 having the semiconductor device structure 2 formed on the surface. 12 are stacked in order from the bottom. The semiconductor element substrate 12 and the semiconductor element substrate 13 have surfaces (upper surfaces) such that the sides on which the semiconductor element structure 2 of the respective Si substrates 20 are formed face each other, as in the junction-type semiconductor element 10 shown in FIG. Bonding (Face-to-Face bonding). On the other hand, in the semiconductor element substrate 11 and the semiconductor element substrate 13, the surface of the semiconductor element substrate 11 and the back surface of the semiconductor element substrate 13 are joined (Face-to-Back junction). The structures of the uppermost and lowermost semiconductor element substrates 12 and 11 are the same as those of the semiconductor element substrate 1 according to the first embodiment. The semiconductor element substrate 13 (1I) will be described below. The same elements as those in the first to fourth embodiments are given the same reference numerals and descriptions thereof will be omitted.

本発明の第５実施形態に係る半導体素子基板１Ｉは、図２４に示す、裏面側（図中、上向き）の接合面近傍以外は図２および図３に示す半導体素子基板１と同様の構造である。すなわち、半導体素子基板１Ｉは、半導体素子基板１にさらに、貫通電極７Ｆと、裏面側絶縁層６２と、貫通孔側壁絶縁層６３と、を備える。半導体素子基板１Ｉはさらに、裏面に開口して貫通電極７Ｆを囲む内壁が垂直な凹み（ポケット）８Ｆが形成されるように、裏面側絶縁層６２および貫通孔側壁絶縁層６３に穴が形成され、それぞれの穴の底面の中央から柱状の貫通電極７Ｆが垂直に突設されている。凹み８Ｆは、図１５に示す第３実施形態に係る半導体素子基板１Ｃの凹み８Ｃと同様の形状である。また、半導体素子基板１Ｉにおいては、Ｓｉ基板２０が裏面から研削されて薄型化されている。   The semiconductor element substrate 1I according to the fifth embodiment of the present invention has the same structure as that of the semiconductor element substrate 1 shown in FIGS. 2 and 3 except in the vicinity of the bonding surface on the back side (upward in the figure) shown in FIG. is there. That is, the semiconductor element substrate 1I further includes the through electrode 7F, the back side insulating layer 62, and the through hole side wall insulating layer 63 in the semiconductor element substrate 1. In the semiconductor element substrate 1I, a hole is formed in the back surface side insulating layer 62 and the through hole side wall insulating layer 63 so that a recess (pocket) 8F having an opening on the back surface and a perpendicular inner wall surrounding the through electrode 7F is formed. A columnar through electrode 7F is vertically protruded from the center of the bottom of each hole. The recess 8F has the same shape as the recess 8C of the semiconductor element substrate 1C according to the third embodiment shown in FIG. Moreover, in the semiconductor element substrate 1I, the Si substrate 20 is ground from the back surface to be thinned.

（貫通電極）
貫通電極７Ｆは、積層型半導体素子に適用されるＳｉ貫通ビア（ＴＳＶ：through-silicon via）であり、裏面からＳｉ基板２０を貫通して配線３に接続する。貫通電極７Ｆは、第３実施形態に係る半導体素子基板１Ｃの接合電極７Ｃと同様、Ｃｕからなるプラグ７２と、側面、さらに上面（配線３側）を被覆するバリア膜７１とを備える。 (Through electrode)
The through electrode 7F is a through silicon via (TSV: through-silicon via) applied to the stacked semiconductor device, and is connected to the wiring 3 through the Si substrate 20 from the back surface. Similar to the bonding electrode 7C of the semiconductor element substrate 1C according to the third embodiment, the through electrode 7F includes the plug 72 made of Cu, and the barrier film 71 covering the side surface and the upper surface (wiring 3 side).

（貫通孔側壁絶縁層）
貫通孔側壁絶縁層６３は、貫通電極７ＦとＳｉ基板２０のＳｉ部分とを絶縁するために、貫通電極７Ｆの側面を被覆するように設けられる。貫通孔側壁絶縁層６３は、後記の裏面側絶縁層６２と同時にエッチング可能な絶縁材料を適用し、同じ絶縁材料を適用することが好ましい。 (Through-hole sidewall insulating layer)
The through hole side wall insulating layer 63 is provided to cover the side surface of the through electrode 7F in order to insulate the through electrode 7F from the Si portion of the Si substrate 20. It is preferable that the through-hole side-wall insulating layer 63 apply an insulating material that can be etched simultaneously with the back-side insulating layer 62 described later, and that the same insulating material is applied.

（裏面側絶縁層）
裏面側絶縁層６２は、絶縁層６１と同様に、ハイブリッド接合に好適となるように表面が平滑であり、そのために、ＳｉＯ2，ＳｉＯＣ等のＳｉ酸化物またはこれを基とするＳｉ化合物で形成される。また、裏面側絶縁層６２は、半導体素子基板１Ｉの裏面に凹み８Ｆが形成されるように、第３実施形態に係る半導体素子基板１Ｃの絶縁層６１と同様の形状の穴が形成されている。 (Back side insulation layer)
Like the insulating layer 61, the back side insulating layer 62 has a smooth surface so as to be suitable for hybrid bonding, and is therefore formed of Si oxide such as SiO 2 or SiOC or a Si compound based thereon Be done. Further, in the back surface side insulating layer 62, a hole having the same shape as the insulating layer 61 of the semiconductor element substrate 1C according to the third embodiment is formed such that a recess 8F is formed on the back surface of the semiconductor element substrate 1I. .

〔半導体素子基板の製造方法〕
本発明の第５実施形態に係る半導体素子基板の製造方法について、図２５、図２６および図２７を参照して説明する。なお、図２６および図２７においては、加工前の膜についても加工後の要素と同じ符号を付して表す。本実施形態に係る半導体素子基板１Ｉ（１３）は、第１実施形態に係る半導体素子基板１を製造した（半導体素子製造工程Ｓ１）後、あるいはさらに表側を半導体素子基板１（１１）と接合した（接合工程Ｓ２）後に、半導体素子基板１の裏面を研削してＳｉ基板２０を薄型化するバックグラインディング工程Ｓ５１と、絶縁膜を裏面に被覆して貫通電極７Ｆの形状の孔を形成する裏面側絶縁層形成工程Ｓ６０と、前記孔の内部に貫通電極７Ｆを形成する電極形成工程Ｓ３０Ａと、裏面に凹み８Ｆを形成する接合部形成工程Ｓ４０Ａと、を行って製造される。 [Method of Manufacturing Semiconductor Device Substrate]
A method of manufacturing a semiconductor device substrate according to the fifth embodiment of the present invention will be described with reference to FIGS. 25, 26 and 27. In FIGS. 26 and 27, the film before processing is represented by the same reference numeral as the element after processing. The semiconductor element substrate 1I (13) according to the present embodiment is joined to the semiconductor element substrate 1 (11) after manufacturing the semiconductor element substrate 1 according to the first embodiment (semiconductor element manufacturing step S1) or further on the front side. (Bonding step S2) A back grinding step S51 of grinding the back surface of the semiconductor element substrate 1 to reduce the thickness of the Si substrate 20, and a back surface of covering the insulating film on the back surface to form holes in the shape of through electrodes 7F. It is manufactured by performing a side insulating layer forming step S60, an electrode forming step S30A in which the through electrode 7F is formed in the inside of the hole, and a bonding portion forming step S40A in which the recess 8F is formed in the back surface.

裏面側絶縁層形成工程Ｓ６０は、裏面側絶縁層６２を構成する絶縁膜を成膜する絶縁膜成膜工程Ｓ６１と、貫通電極７Ｆが形成される領域とその周囲を空けたレジストマスクＰＲ３を形成するマスク工程Ｓ６２と、裏面側絶縁層６２をエッチングする絶縁膜エッチング工程Ｓ６３と、Ｓｉ基板２０をエッチングする基板エッチング工程Ｓ６４と、絶縁層４をエッチングして配線３を露出させる絶縁層エッチング工程Ｓ６５と、レジストマスクＰＲ３を除去するマスク除去工程Ｓ６６と、貫通孔側壁絶縁層６３を構成する絶縁膜を成膜する絶縁膜成膜工程Ｓ６７と、貫通孔側壁絶縁層６３をエッチングして配線３を再び露出させる絶縁膜異方性エッチング工程Ｓ６８と、を行う。電極形成工程Ｓ３０Ａは接合電極７Ｃを形成する第３実施形態の電極形成工程Ｓ３０（図１６参照）とほぼ同様であり、金属材料を成膜してバリア膜７１を形成するバリア膜成膜工程Ｓ３１Ａと、Ｃｕを成膜してめっきのためのシード層７２ｓを形成するシード層成膜工程Ｓ３２と、Ｃｕをめっきする電極成膜工程Ｓ３４Ａと、裏面を研削、研磨して絶縁膜（裏面側絶縁層６２）および貫通電極７Ｆの上面を平滑化する平滑化工程Ｓ６９と、を行う。接合部形成工程Ｓ４０Ａは第３実施形態の接合部形成工程Ｓ４０（図１６参照）とほぼ同様であり、貫通電極７Ｆが露出している領域およびその周囲を空けたレジストマスクを形成するマスク工程Ｓ２７Ａと、裏面側絶縁層６２および貫通孔側壁絶縁層６３を所定の深さまでエッチングする絶縁膜エッチング工程Ｓ２４Ｃと、レジストマスクを除去するマスク除去工程Ｓ２８と、を行う。   In the back surface side insulating layer forming step S60, an insulating film forming step S61 of forming an insulating film forming the back surface side insulating layer 62, and a resist mask PR3 having a region in which the through electrode 7F is formed and the periphery thereof are formed. Mask step S62, insulating film etching step S63 for etching the back surface side insulating layer 62, substrate etching step S64 for etching the Si substrate 20, and insulating layer etching step S65 for etching the insulating layer 4 to expose the wiring 3 , Mask removing step S66 for removing the resist mask PR3, insulating film forming step S67 for forming the insulating film forming the through-hole sidewall insulating layer 63, and etching the through-hole sidewall insulating layer 63 to form the wiring 3 And an insulating film anisotropic etching step S68 of exposing again. The electrode forming step S30A is substantially the same as the electrode forming step S30 (see FIG. 16) of the third embodiment for forming the bonding electrode 7C, and a barrier film forming step S31A for forming a barrier film 71 by forming a metal material. , Seed layer formation step S32 for forming Cu and deposit seed layer 72s for plating, electrode formation step S34A for plating Cu, grinding and polishing the back surface, insulating film (back side insulation And a smoothing step S69 for smoothing the upper surface of the layer 62) and the through electrode 7F. The bonding portion forming step S40A is substantially the same as the bonding portion forming step S40 (see FIG. 16) of the third embodiment, and a mask step S27A for forming a resist mask in which the region where the through electrode 7F is exposed and the periphery are open. Then, an insulating film etching step S24C of etching the back surface side insulating layer 62 and the through hole side wall insulating layer 63 to a predetermined depth and a mask removing step S28 of removing the resist mask are performed.

（バックグラインディング工程）
半導体素子基板１の裏面を研削して（バックグラインディング；ＢＧ）、あるいはさらに研磨して（Back Side Polishing；ＢＳＰ）、半導体素子構造２等にダメージのないように、Ｓｉ基板２０を所定の厚さに薄型化する（Ｓ５１）。 (Back grinding process)
The back surface of the semiconductor element substrate 1 is ground (back grinding; BG) or further polished (Back Side Polishing; BSP) so that the Si substrate 20 has a predetermined thickness so as not to damage the semiconductor element structure 2 and the like. Reduce the thickness (S51).

（裏面側絶縁層形成工程）
薄型化したＳｉ基板２０の裏面上に、裏面側絶縁層６２を構成するＳｉＯ2膜を、第３実施形態の絶縁膜成膜工程Ｓ２２と同様に、完成時の厚さよりも厚く成膜する（Ｓ６１）。このＳｉＯ2膜上に、図２６（ａ）に示すように、貫通電極７Ｆが形成される領域とその周囲を空けたレジストマスクＰＲ３を形成する（Ｓ６２）。そして、ＳｉＯ2膜をエッチングし（Ｓ６３）、引き続いてＳｉ基板２０をエッチングし（Ｓ６４）、さらにその上の絶縁層４をエッチングして、裏面側絶縁層６２、Ｓｉ基板２０、および絶縁層４の配線３に到達する孔（貫通孔）を形成する（Ｓ６５）。そして、図２６（ｂ）に示すようにレジストマスクＰＲ３を除去する（Ｓ６６）。次に、図２７（ａ）に示すように、貫通孔の内側も含めた全面に、貫通孔側壁絶縁層６３を構成する絶縁膜を、貫通孔の側壁において所定の厚さに成膜する（Ｓ６７）。異方性エッチングにより、図２７（ｂ）に示すように、貫通孔の底面（配線３上）の絶縁膜を除去して配線３を露出させて、貫通孔側壁絶縁層６３を成形する（Ｓ６８）。 (Back side insulation layer formation process)
On the back surface of the thinned Si substrate 20, the SiO 2 film constituting the back surface side insulating layer 62 is formed to be thicker than the completed thickness, as in the insulating film forming step S22 of the third embodiment ( S61). On the SiO 2 film, as shown in FIG. 26A, a resist mask PR3 is formed in which the region where the through electrode 7F is to be formed and the periphery thereof are opened (S62). Then, the SiO 2 film is etched (S 63), and subsequently the Si substrate 20 is etched (S 64), and the insulating layer 4 thereon is further etched to form the back side insulating layer 62, the Si substrate 20, and the insulating layer 4. A hole (through hole) reaching the wiring 3 of the above is formed (S65). Then, as shown in FIG. 26B, the resist mask PR3 is removed (S66). Next, as shown in FIG. 27A, an insulating film forming the through hole sidewall insulating layer 63 is formed on the entire surface including the inside of the through hole to a predetermined thickness on the side wall of the through hole ( S67). As shown in FIG. 27B, the insulating film on the bottom surface (on the wiring 3) of the through hole is removed by anisotropic etching to expose the wiring 3 and form the through hole sidewall insulating layer 63 (S68) ).

（電極形成工程、接合部形成工程）
図１７（ｃ）、（ｄ）および図１８（ａ）に示す第３実施形態の電極形成工程Ｓ３０と同様に、バリア膜７１およびプラグ７２を貫通孔に埋め込み（Ｓ３１Ａ，Ｓ３２，Ｓ３４Ａ）、裏面をＣＭＰで研削して裏面側絶縁層６２を露出させ、さらに研磨して、貫通電極７Ｆ、裏面側絶縁層６２をそれぞれ所定の厚さとし、かつ所定の表面粗さに平滑化する（Ｓ６９）。そして、図１８（ｂ）、（ｃ）に示す第３実施形態の接合部形成工程Ｓ４０と同様に、裏面の貫通電極７Ｆが露出した領域上に、貫通電極７Ｆよりも一回り大きな領域を空けたレジストマスクを形成し（Ｓ２７Ａ）、裏面側絶縁層６２および貫通孔側壁絶縁層６３を所望の深さまでエッチングして穴を形成し（Ｓ２４Ｃ）、レジストマスクを除去して（Ｓ２８）、半導体素子基板１Ｉが得られる。 (Electrode formation process, junction formation process)
As in the electrode forming step S30 of the third embodiment shown in FIGS. 17C, 17D and 18A, the barrier film 71 and the plug 72 are embedded in the through holes (S31A, S32, S34A), and the back surface Is polished by CMP to expose the back side insulating layer 62 and further polished to make the through electrode 7F and the back side insulating layer 62 to have predetermined thicknesses and smooth to a predetermined surface roughness (S69). Then, similarly to the bonding portion forming step S40 of the third embodiment shown in FIGS. 18B and 18C, a region slightly larger than the through electrode 7F is opened above the region where the through electrode 7F on the back surface is exposed. The resist mask is formed (S27A), the back side insulating layer 62 and the through hole side wall insulating layer 63 are etched to a desired depth to form a hole (S24C), the resist mask is removed (S28), and the semiconductor element is formed. Substrate 1I is obtained.

裏面側絶縁層形成工程Ｓ６０において、マスク除去工程Ｓ６６は、絶縁膜エッチング工程Ｓ６３の後、基板エッチング工程Ｓ６４の前に行うこともでき、裏面側絶縁層６２をマスクとしてＳｉ基板２０をエッチングする。この場合、裏面側絶縁層６２は絶縁層エッチング工程Ｓ６５で減肉するため、絶縁膜成膜工程Ｓ６１でその分を加算した厚さに成膜する。また、接合部形成工程Ｓ４０Ａにおいて、絶縁膜エッチング工程Ｓ２４Ｃは、第３実施形態の絶縁膜エッチング工程Ｓ２４Ｂと同様に、図２０に示す変形例のように等方性エッチングで行うこともできる。この場合、レジストマスクの形成（Ｓ２７Ａ）にレジストマスクＰＲ３を形成するためのレチクル（フォトマスク）を流用し得る。また、絶縁膜エッチング工程Ｓ２４Ｃにおいて、エッチングレートが裏面側絶縁層６２と貫通孔側壁絶縁層６３で異なっていてもよく、この場合には凹み８Ｆの底面に段差を生じるため、エッチングレートの遅い方が、所定の深さに到達するように設定する。ただし、エッチングレートの速い方が過剰に深いと、貫通電極７Ｆが側面で十分に支持されないため、裏面側絶縁層６２と貫通孔側壁絶縁層６３は、それぞれを構成する絶縁材料のエッチングレートの差が大き過ぎないように選択される。   In the back surface side insulating layer forming step S60, the mask removing step S66 may be performed after the insulating film etching step S63 and before the substrate etching step S64, and the Si substrate 20 is etched using the back surface side insulating layer 62 as a mask. In this case, since the back side insulating layer 62 is thinned in the insulating layer etching step S65, the back surface side insulating layer 62 is formed to a thickness obtained by adding that amount in the insulating film forming step S61. In the bonding portion forming step S40A, the insulating film etching step S24C can also be performed by isotropic etching as in the modification shown in FIG. 20, as in the insulating film etching step S24B of the third embodiment. In this case, a reticle (photomask) for forming the resist mask PR3 can be diverted to the formation of the resist mask (S27A). In the insulating film etching step S24C, the etching rate may be different between the back side insulating layer 62 and the through hole side wall insulating layer 63. In this case, a step is generated on the bottom of the recess 8F, so the etching rate is slower. Set to reach a predetermined depth. However, if the faster etching rate is excessively deep, the through electrode 7F is not sufficiently supported on the side surface, so the difference between the etching rates of the insulating materials constituting the back surface side insulating layer 62 and the through hole side wall insulating layer 63 Is chosen not to be too large.

このように、Ｓｉ基板２０に貫通電極７Ｆを埋め込まれる貫通孔を開ける前に、裏面上にＳｉＯ2膜を成膜することにより、裏面を被覆する裏面側絶縁層６２が、成膜されるときに貫通電極７ＦからＣｕが拡散されず、かつ、接合面に好適な平滑面に形成することができる。得られた半導体素子基板１Ｉ（１３）は、その裏面を、第１実施形態に係る半導体素子基板１（１１）の表面と接合して、接合型半導体素子１０Ｆとすることができる。接合方法は、第１実施形態の接合工程Ｓ２と同様である。半導体素子基板１Ｉの裏面側絶縁層６２と半導体素子基板１の絶縁層６１とが接合して、一体の絶縁体６０Ａとなり、空隙８０Ｆが内包される。また、半導体素子基板１Ｉの貫通電極７Ｆと半導体素子基板１の接合電極７とが接合して、柱状電極７０Ｆとなる。 As described above, when the back side insulating layer 62 covering the back surface is formed by forming the SiO 2 film on the back surface before forming the through hole in which the through electrode 7F is embedded in the Si substrate 20. Cu can not be diffused from the through electrode 7F to a smooth surface suitable for the bonding surface. The obtained semiconductor element substrate 1I (13) can be bonded to the surface of the semiconductor element substrate 1 (11) according to the first embodiment to form a junction-type semiconductor element 10F. The bonding method is the same as the bonding step S2 of the first embodiment. The back side insulating layer 62 of the semiconductor element substrate 1I and the insulating layer 61 of the semiconductor element substrate 1 are joined to form an integral insulator 60A, and the void 80F is included. Further, the through electrode 7F of the semiconductor element substrate 1I and the bonding electrode 7 of the semiconductor element substrate 1 are joined to form a columnar electrode 70F.

なお、裏面の凹み８Ｆは、第３実施形態に係る半導体素子基板１Ｃの表面の凹み８Ｃと同様、任意の平面視形状とすることができ、図１９に示す変形例に係る半導体素子基板１Ｄの凹み８Ｄのように、端まで延設した溝状としてもよい。また、接合部形成工程Ｓ４０Ａを行わず、図２２（ａ）に示す半導体素子基板１Ｆのように、平滑化工程Ｓ６９において、貫通電極７Ｆを突出させてもよい。また、半導体素子基板１Ｉの表側の接合電極７および凹み８は、第１実施形態に限られず、図８、図１０、図１５、図２０、図２２に示す、第２、第３、第４実施形態としてもよい。   The recess 8F on the back surface can have an arbitrary plan view shape like the recess 8C on the surface of the semiconductor element substrate 1C according to the third embodiment, and the recess 8F of the semiconductor element substrate 1D according to the modification shown in FIG. Like a recess 8D, it may be a groove extending to the end. Further, the through electrode 7F may be protruded in the smoothing step S69 as in the semiconductor element substrate 1F shown in FIG. 22A, without performing the bonding portion forming step S40A. Further, the bonding electrode 7 and the recess 8 on the front side of the semiconductor element substrate 1I are not limited to the first embodiment, and the second, third and fourth shown in FIGS. 8, 10, 15, 20 and 22. It is good also as an embodiment.

（変形例）
前記製造方法では、完成した半導体素子基板１に裏面側から加工して貫通電極７Ｆを形成する、バックサイドビアプロセス（ビアラストプロセス）で半導体素子基板１Ｉを製造しているが、半導体素子基板１の製造時の、半導体素子構造２の形成前に、または配線３の形成前に、表側からＳｉ基板２０を加工して貫通電極７Ｆを形成することもできる（ビアファーストプロセス、ビアミドルプロセス）。これらのプロセスでは、貫通電極７Ｆは、形成後に裏面を研削してＳｉ基板２０が薄型化されると共に露出するため、その形成時においては図２９（ａ）に示すように、Ｓｉ基板２０を貫通させない。このような貫通電極７Ｆを形成するために、図２８に示すように、半導体素子・配線形成工程Ｓ１０において、半導体素子形成工程Ｓ１１の後に、裏面側絶縁層形成工程Ｓ６０Ａと前記孔の内部に貫通電極７Ｆを形成する電極形成工程Ｓ３０Ｂを順に行った後、配線形成工程Ｓ１２を行う。詳しくは、半導体素子構造２およびその上を被覆する絶縁層４を形成した（Ｓ１１）後、絶縁層４上にレジストマスクＰＲ３を形成して（Ｓ６２）、絶縁層４をエッチングし（Ｓ６５Ａ）、引き続いてＳｉ基板２０を所定の深さまでエッチングして（Ｓ６４Ａ）、レジストマスクＰＲ３を除去する（Ｓ６６）。そして、貫通孔側壁絶縁層６３Ａを構成するＳｉＯ2膜を全面に成膜した（Ｓ６７Ａ）後、電極形成工程Ｓ３０Ｂを行う。電極形成工程Ｓ３０Ｂは、接合電極７Ｃを形成する第３実施形態の電極形成工程Ｓ３０（図１６参照）とほぼ同様である。その後、配線３や残りの絶縁層４を形成し（配線形成工程Ｓ１２）、接合電極７等を形成する接合部形成工程Ｓ２０を行って、接合電極７と共に貫通電極７Ｆを備えた半導体素子基板１を製造する。 (Modification)
In the above manufacturing method, the semiconductor element substrate 1I is manufactured by the back side via process (via last process) of processing the completed semiconductor element substrate 1 from the back side to form the through electrode 7F. Before the formation of the semiconductor element structure 2 or the formation of the wiring 3 at the time of manufacturing, the Si substrate 20 can be processed from the front side to form the through electrode 7F (via first process, via middle process). In these processes, the through electrode 7F is formed by grinding the back surface after formation to thin and expose the Si substrate 20. Therefore, the through electrode 7F penetrates the Si substrate 20 as shown in FIG. I will not let you. In order to form such a through electrode 7F, as shown in FIG. 28, in the semiconductor element / wiring formation step S10, after the semiconductor element formation step S11, the backside insulating layer formation step S60A and the inside of the hole are penetrated. After sequentially performing the electrode formation step S30B for forming the electrode 7F, the wiring formation step S12 is performed. Specifically, after forming the semiconductor element structure 2 and the insulating layer 4 covering the upper side (S11), a resist mask PR3 is formed on the insulating layer 4 (S62), and the insulating layer 4 is etched (S65A), Subsequently, the Si substrate 20 is etched to a predetermined depth (S64A), and the resist mask PR3 is removed (S66). Then, after an SiO 2 film constituting the through hole sidewall insulating layer 63A is formed on the entire surface (S67A), an electrode forming step S30B is performed. The electrode forming step S30B is substantially the same as the electrode forming step S30 (see FIG. 16) of the third embodiment for forming the bonding electrode 7C. Thereafter, the wiring 3 and the remaining insulating layer 4 are formed (wiring forming step S12), and the bonding portion forming step S20 for forming the bonding electrode 7 and the like is performed to obtain the semiconductor element substrate 1 including the through electrode 7F together with the bonding electrode 7. Manufacture.

この半導体素子基板１の裏面を研削、研磨してＳｉ基板２０を薄型化し（Ｓ５１Ａ）、貫通電極７ＦをＳｉ基板２０から裏面側絶縁層６２の厚さよりも高く裏面に突出させる（図２９（ｂ）参照）。このとき、貫通電極７Ｆのプラグ７２を露出させないために、Ｓｉ基板２０を、バックグラインディング等では貫通電極７Ｆの底面のバリア膜７１まで到達させない厚さとし、その後、Ｓｉエッチング等でＳｉ基板２０を選択的にエッチングして、貫通電極７Ｆを、その底面と側面のバリア膜７１を残して突出させる。図２９（ｂ）では、貫通電極７Ｆを被覆する貫通孔側壁絶縁層６３Ａも残した状態で示すが、貫通孔側壁絶縁層６３ＡもＳｉ基板２０の裏面に合わせて除去してもよい。この上から、図２９（ｂ）に示すように、裏面側絶縁層６２を構成するＳｉＯ2膜を成膜する（Ｓ６１）。次に、再びＣＭＰで今度は裏面を平坦、平滑化して、貫通電極７Ｆを裏面に露出させる（Ｓ６９Ｂ）。その後、前記第５実施形態と同様に、接合部形成工程Ｓ４０Ａを行って裏面に凹み８Ｆを形成したり、または、前記平滑化工程Ｓ６９Ｂで貫通電極７Ｆを裏面に突出させる。 The back surface of the semiconductor element substrate 1 is ground and polished to thin the Si substrate 20 (S51A), and the through electrode 7F is protruded from the Si substrate 20 to the back surface more than the thickness of the back surface insulating layer 62 (FIG. )reference). At this time, in order to prevent the plug 72 of the through electrode 7F from being exposed, the thickness of the Si substrate 20 does not reach the barrier film 71 on the bottom of the through electrode 7F in back grinding etc. Selective etching is performed to project the through electrode 7F leaving the barrier film 71 on the bottom and the side thereof. In FIG. 29B, the through-hole sidewall insulating layer 63A covering the through electrode 7F is also left, but the through-hole sidewall insulating layer 63A may be removed in accordance with the back surface of the Si substrate 20. From above, as shown in FIG. 29B, a SiO 2 film constituting the back side insulating layer 62 is formed (S61). Next, the back surface is flattened and smoothed again by CMP again to expose the through electrode 7F on the back surface (S69B). After that, as in the fifth embodiment, the bonding portion forming step S40A is performed to form a recess 8F on the back surface, or the through electrode 7F is protruded to the back surface in the smoothing step S69B.

このように、Ｃｕ（プラグ７２）が露出しないように貫通電極７Ｆを突出させてＳｉ基板２０を薄型化して、その上からＳｉＯ2膜を成膜することにより、裏面を被覆する裏面側絶縁層６２が、成膜されるときに貫通電極７ＦからＣｕが拡散されず、かつ、接合面に好適な平滑面に形成することができる。 As described above, the back surface side insulating layer that covers the back surface by forming the SiO 2 film on the Si substrate 20 by thinning the Si substrate 20 by projecting the through electrode 7F so that Cu (plug 72) is not exposed. When forming a film 62, Cu is not diffused from the through electrode 7F when forming a film, and can be formed on a smooth surface suitable for the bonding surface.

以上のように、本発明の第５実施形態に係る接合型半導体素子によれば、裏面側においてもハイブリッド接合することができ、第１実施形態等と同様に、接合強度を十分に確保しつつ、接合の位置ずれに起因する信頼性低下等の不良を低減することができる。   As described above, according to the junction-type semiconductor device according to the fifth embodiment of the present invention, hybrid junction can be performed also on the back surface side, and as in the first embodiment etc., the junction strength is sufficiently ensured. It is possible to reduce defects such as reliability deterioration due to positional deviation of bonding.

以上、本発明の積層型半導体素子を実施するための各実施形態について述べてきたが、本発明はこれらの実施形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能である。   As mentioned above, although each embodiment for carrying out the lamination type semiconductor device of the present invention has been described, the present invention is not limited to these embodiments, and various modifications can be made within the scope of the claims. It is.

１０，１０Ｂ，１０Ｃ，１０Ｅ，１０Ｆ 接合型半導体素子（積層型半導体素子）
１，１Ａ，１Ｂ，１Ｃ，１Ｄ，１Ｅ，１Ｆ，１Ｇ，１Ｈ，１Ｉ 半導体素子基板（半導体素子）
１１，１２，１３ 半導体素子基板（半導体素子）
２０ Ｓｉ基板
２１，２２ Ｓｉ基板
２ 半導体素子構造
３，３Ａ，３Ｂ 配線
３１ バリア膜
３２ コア部
４，４Ａ 絶縁層
５ 拡散防止絶縁膜
６０，６０Ａ 絶縁体
６１，６２ 絶縁層（絶縁体）
７０，７０Ｂ，７０Ｃ，７０Ｅ，７０Ｆ 柱状電極
７，７Ｂ，７Ｃ 接合電極
７Ｆ 貫通電極
７１ バリア膜
７２ プラグ
８０，８０Ｂ，８０Ｃ，８０Ｅ，８０Ｆ 空隙
８，８Ａ，８Ｂ，８Ｃ，８Ｄ，８Ｆ 凹み
Ｓ１ 半導体素子製造工程
Ｓ２ 接合工程
Ｓ２１ 拡散防止絶縁膜成膜工程
Ｓ２２ 絶縁膜成膜工程
Ｓ２３，Ｓ２３Ａ 平滑化工程
Ｓ２４，Ｓ２４Ａ 絶縁膜等方性エッチング工程（絶縁膜エッチング工程）
Ｓ２４Ｂ 絶縁膜エッチング工程
Ｓ２５ 絶縁膜エッチング工程
Ｓ２６ 拡散防止絶縁膜エッチング工程
Ｓ２７ マスク工程
Ｓ２８ マスク除去工程
Ｓ３１ バリア膜成膜工程
Ｓ３２ シード層成膜工程
Ｓ３３ マスク工程
Ｓ３４，Ｓ３４Ａ 電極成膜工程
Ｓ３５ マスク除去工程 10, 10B, 10C, 10E, 10F Junction type semiconductor element (stacked type semiconductor element)
1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I Semiconductor element substrate (semiconductor element)
11, 12, 13 Semiconductor element substrate (semiconductor element)
Reference Signs List 20 Si substrate 21, 22 Si substrate 2 semiconductor element structure 3, 3A, 3B wiring 31 barrier film 32 core portion 4, 4A insulating layer 5 diffusion preventing insulating film 60, 60A insulator 61, 62 insulating layer (insulator)
70, 70B, 70C, 70E, 70F Columnar electrode 7, 7B, 7C Junction electrode 7F Through electrode 71 Barrier film 72 Plug 80, 80B, 80C, 80E, 80F Air gap 8, 8A, 8B, 8C, 8D, 8F Indented S1 semiconductor Element manufacturing process S2 bonding process S21 diffusion preventing insulating film forming process S22 insulating film forming process S23, S23A smoothing process S24, S24A insulating film isotropic etching process (insulating film etching process)
S24B Insulating film etching process S25 Insulating film etching process S26 Diffusion preventing insulating film etching process S27 Mask process S28 Mask removal process S31 Barrier film formation process S32 Seed film formation process S33 Mask process S34, S34A Electrode film formation process S35 Mask removal process

Claims (9)

積層方向に沿った柱状電極で層間を接続した積層型半導体素子であって、
積層方向における前記柱状電極が設けられた領域で、前記柱状電極の側面と絶縁体とが空隙を挟んで対向していることを特徴とする積層型半導体素子。 A stacked semiconductor device in which layers are connected by columnar electrodes along a stacking direction,
A stacked semiconductor device characterized in that a side surface of the columnar electrode and an insulator face each other with a gap in a region where the columnar electrode is provided in the stacking direction. 前記柱状電極の一方または両方の底面を被覆する導体からなるバリア膜を備えることを特徴とする請求項１に記載の積層型半導体素子。   2. The stacked semiconductor device according to claim 1, further comprising a barrier film made of a conductor that covers the bottom surface of one or both of the columnar electrodes. 前記柱状電極の側面を被覆する導体からなるバリア膜を備えることを特徴とする請求項１または請求項２に記載の積層型半導体素子。   3. The stacked semiconductor device according to claim 1, further comprising: a barrier film made of a conductor which covers the side surface of the columnar electrode. 半導体素子が形成された基板と、前記半導体素子に電気的に接続した柱状電極と、前記柱状電極を露出させて前記基板上を被覆する絶縁体と、を備え、
前記柱状電極を囲む凹みを上面に有し、前記絶縁体が少なくとも上面において前記柱状電極と非接触であることを特徴とする半導体素子基板。 A substrate on which a semiconductor element is formed, a columnar electrode electrically connected to the semiconductor element, and an insulator which exposes the columnar electrode and covers the substrate.
A semiconductor element substrate having a recess on an upper surface surrounding the columnar electrode, wherein the insulator is not in contact with the columnar electrode at least on the upper surface. 前記柱状電極の下面を被覆する導体からなるバリア膜を備えることを特徴とする請求項４に記載の半導体素子基板。   5. The semiconductor element substrate according to claim 4, further comprising a barrier film made of a conductor covering the lower surface of the columnar electrode. 前記柱状電極の側面を被覆する導体からなるバリア膜を備えることを特徴とする請求項４または請求項５に記載の半導体素子基板。   The semiconductor element substrate according to claim 4 or 5, further comprising: a barrier film made of a conductor that covers the side surface of the columnar electrode. 上面に柱状電極が露出した半導体素子基板の製造方法であって、
半導体素子が形成された基板上に、絶縁膜を成膜する絶縁膜成膜工程と、
柱状電極が形成される領域を空けたマスクを形成するマスク工程と、
前記絶縁膜をエッチングする絶縁膜エッチング工程と、
電極材料を成膜して、前記マスクの空いた領域に柱状電極を形成する電極成膜工程と、
前記マスクを除去するリフトオフ工程と、を行い、
前記絶縁膜エッチング工程は、等方性エッチングを行い、前記絶縁膜を、少なくともその上面において、前記柱状電極が形成される領域を超えて除去することを特徴とする半導体素子基板の製造方法。 A method of manufacturing a semiconductor device substrate having a columnar electrode exposed on the upper surface, comprising:
An insulating film forming step of forming an insulating film on a substrate on which a semiconductor element is formed;
A mask process for forming a mask having an area in which a columnar electrode is to be formed;
An insulating film etching step of etching the insulating film;
An electrode film forming step of forming an electrode material and forming a columnar electrode in a region where the mask is opened;
Performing a lift-off process to remove the mask;
The method of manufacturing a semiconductor element substrate according to claim 1, wherein the insulating film etching step performs isotropic etching to remove the insulating film at least on the upper surface thereof beyond the region where the columnar electrode is formed. 半導体素子が形成された基板上に、柱状電極が形成される領域を空けた絶縁膜を形成する絶縁膜形成工程と、
電極材料を成膜して、前記基板上の前記絶縁膜の空いた領域に柱状電極を形成する電極形成工程と、を行って、最上層に設けられた絶縁膜および前記絶縁膜を貫通して露出する柱状電極を形成した後に、
前記柱状電極が露出している領域の周囲を少なくとも空けたマスクを形成するマスク工程と、
前記絶縁膜を、その厚さ以下をエッチングする絶縁膜エッチング工程と、
前記マスクを除去するマスク除去工程と、を行うことを特徴とする半導体素子基板の製造方法。 An insulating film forming step of forming an insulating film having a region where a columnar electrode is to be formed on a substrate having a semiconductor element formed thereon
An electrode forming step of forming an electrode material and forming a columnar electrode in a vacant area of the insulating film on the substrate; and penetrating the insulating film provided on the uppermost layer and the insulating film. After forming the exposed columnar electrodes,
Forming a mask spaced at least around the exposed area of the columnar electrode;
An insulating film etching step of etching the insulating film below its thickness;
And a mask removing step of removing the mask. 請求項７または請求項８に記載の半導体素子基板の製造方法を行って、それぞれの上面における柱状電極の配置が対称な２つの半導体素子基板を製造する半導体素子基板製造工程と、
前記２つの半導体素子基板の上面同士を前記柱状電極および絶縁体のそれぞれで接合する接合工程と、を行うことを特徴とする積層型半導体素子の製造方法。 9. A semiconductor element substrate manufacturing process for manufacturing two semiconductor element substrates in which the arrangement of columnar electrodes on their upper surfaces is symmetrical by performing the method of manufacturing a semiconductor element substrate according to claim 7 or 8;
And a bonding step of bonding the upper surfaces of the two semiconductor element substrates to each other with the columnar electrode and the insulator.
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