JP2018181099A - 表示装置 - Google Patents
表示装置 Download PDFInfo
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- JP2018181099A JP2018181099A JP2017081989A JP2017081989A JP2018181099A JP 2018181099 A JP2018181099 A JP 2018181099A JP 2017081989 A JP2017081989 A JP 2017081989A JP 2017081989 A JP2017081989 A JP 2017081989A JP 2018181099 A JP2018181099 A JP 2018181099A
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- Liquid Crystal Display Device Control (AREA)
Abstract
【解決手段】基板、複数の画素電極、表示機能層、複数の共通電極及び複数の第1電極は、この順で重なって設けられ、複数の共通電極と第1電極とは、平面視で互いに交差して設けられており、表示期間には、制御部からの制御信号に応じて、画素電極に画素信号が供給されると共に、共通電極に共通信号が供給され、第1センサ期間には、制御部からの制御信号に応じて、共通電極に第1駆動信号が供給されて電磁誘導を形成し、第1電極には、電磁誘導に基づく起電力が発生し、第2センサ期間には、制御部からの制御信号に応じて、共通電極に第2駆動信号が供給されて第1電極との間で静電容量を形成する。
【選択図】図8
Description
図1は、第1の実施形態に係る表示装置の一構成例を示すブロック図である。本実施形態の表示装置1は、被検出体の表示面への接触や近接を検出する検出機能が内蔵されている。図1に示すように、表示装置1は、表示パネル10と、制御部11と、ゲートドライバ12と、ソースドライバ13と、駆動回路14と、検出部40とを備える。
図23は、第2の実施形態に係る表示装置の分解斜視図である。図24は、第2の実施形態に係る表示装置の概略断面構造を表す断面図である。本実施形態の表示装置1Bは、第1基板21、信号線SGL、第2電極24、画素電極25、表示機能層としての液晶層6、共通電極COML及び第1電極TDLは、この順で重なって設けられる。言い換えると、第1基板21の表面に垂直な方向において、第1基板21と第2電極24との間に信号線SGLが設けられる。
図25は、第3の実施形態に係る表示装置の分解斜視図である。本実施形態の表示装置1Cにおいて、第1基板21、第2電極24B、信号線SGL、複数の画素電極25、表示機能層としての液晶層6、複数の共通電極COMLA及び複数の第1電極TDLAは、この順で重なって設けられる。共通電極COMLAは、第2方向Dyに長尺に設けられ、第1方向Dxに複数配列されている。また、第1電極TDLAは、第1方向Dxに長尺に設けられ、第2方向Dyに複数配列される。本実施形態においても、第1電極TDLAは、平面視で、共通電極COMLAと交差する。共通電極COMLA、第1電極TDLA共に帯状に形成されている。
図34は、共通電極のパターン構成例を示す平面図である。図35は、共通電極と液晶の配向の関係を説明するための説明図である。図35は、画素電極25と、共通電極COMLと、画素電極25と共通電極COMLとの間に配置される液晶層6とを模式的に示している。液晶層6は、各液晶分子6aを楕円で示し、液晶分子6aの配向状態のイメージを示す。
スリットSLBは、平面視で、隣り合う副画素SPixの間に設けられる。スリットSLA及びスリットSLBは、それぞれゲート線GCL(図29参照)と重なって設けられる。また、スリットSLA及びスリットSLBの幅はゲート線GCLの幅よりも大きい。これにより、ゲート線GCLと共通電極COMLとの間の容量が低減される。
2 画素基板
3 対向基板
6 液晶層
10 表示パネル
11 制御部
12 ゲートドライバ
13 ソースドライバ
14 駆動回路
19 駆動IC
21 第1基板
24、24A、24B 第2電極
24b、24Bb 配線
25 画素電極
26a 金属層
26b 透光性導電層
29 平坦化膜
32 カラーフィルタ
40 検出部
47A 第1AFE
47B 第2AFE
48 マルチプレクサ
49 タッチIC
50 カバー部材
72 接続電極
80 周辺回路領域
81 導通部
100 タッチペン
COML 共通電極
TDL 第1電極
CTx 送信コイル
CRx 受信コイル
SGL 信号線
GCL ゲート線
VTP 第1駆動信号
TSVcom 第2駆動信号
Claims (13)
- 基板と、複数の画素電極と、表示機能層と、複数の共通電極と、複数の第1電極と、前記画素電極、前記共通電極及び前記第1電極を制御する制御部と、を備え、
前記基板、複数の前記画素電極、前記表示機能層、複数の前記共通電極及び複数の前記第1電極は、この順で重なって設けられ、複数の前記共通電極と前記第1電極とは、平面視で互いに交差して設けられており、
前記制御部は、画像を表示する複数の表示期間と、第1センサ期間と、第2センサ期間とを時分割で実行し、夫々の期間に応じて前記画素電極、前記共通電極及び前記第1電極を制御し、
前記表示期間には、前記制御部からの制御信号に応じて、前記画素電極に画素信号が供給されると共に、前記共通電極に共通信号が供給され、
前記第1センサ期間には、前記制御部からの制御信号に応じて、前記共通電極に第1駆動信号が供給されて電磁誘導を形成し、前記第1電極には、前記電磁誘導に基づく起電力が発生し、
前記第2センサ期間には、前記制御部からの制御信号に応じて、前記共通電極に第2駆動信号が供給されて前記第1電極との間で静電容量を形成する、
表示装置。 - 前記複数の共通電極のうち、一対の共通電極の同側の端部を接続するスイッチ部が設けられており、
前記制御部は、前記第1センサ期間に、前記スイッチ部の動作により前記一対の共通電極どうしを接続し、前記第1センサ期間とは異なる期間に前記スイッチ部の動作により前記一対の共通電極どうしを非接続状態とする
請求項1に記載の表示装置。 - 前記複数の共通電極に第1電圧を供給する第1電圧供給部と、前記複数の共通電極に第1電圧よりも小さい第2電圧を供給する第2電圧供給部と、を備え、
前記制御部からの制御信号に応じて、前記第1センサ期間に、少なくとも1つの前記共通電極の一端側に前記第1電圧供給部が接続され、他端側に前記第2電圧供給部が接続され、少なくとも1つの前記共通電極の他の前記共通電極の一端側に前記第2電圧供給部が接続され、他端側に前記第1電圧供給部が接続される請求項1に記載の表示装置。 - 前記第1電極に接続されたアナログフロントエンド回路をさらに備えている請求項1から請求項3のいずれか1項に記載の表示装置。
- 前記第1電極と前記アナログフロントエンド回路の間には、これらの接続状態を切り替えるスイッチ回路が設けられており、
前記スイッチ回路は、
前記第1センサ期間に、少なくとも一対の第1電極の同側の一端部どうしを接続すると共に、当該一対の第1電極のうちの一方の第1電極の他端部と前記アナログフロントエンド回路とを接続し、
前記第2センサ期間には、各前記第1電極と前記アナログフロントエンド回路とを接続する
請求項4に記載の表示装置。 - 前記基板と前記画素電極との間に複数の第2電極を備え、
複数の前記第2電極は、平面視で、前記共通電極と同じ方向に長手を有する
請求項1から請求項5のいずれか1項に記載の表示装置。 - 前記基板と前記表示機能層との間に、前記基板の一側から他側に亘って複数並んで設けられた配線を備え、
前記共通電極及び前記第2電極は、平面視で、複数の前記配線に交差して設けられている
請求項6に記載の表示装置。 - 複数の前記配線は平坦化膜に覆われており、複数の前記第2電極は、前記平坦化膜の表面に形成されている
請求項7に記載の表示装置。 - 前記第2電極は、金属層と、前記金属層を覆う透光性導電層により形成されている
請求項8に記載の表示装置。 - 前記画素電極は反射電極として形成されており、前記第2電極は、前記反射電極に重なる位置に形成されている
請求項8又は請求項9に記載の表示装置。 - 前記基板と前記表示機能層との間に、前記基板の一側から他側に亘って複数並んで設けられた配線を備え、
前記共通電極及び前記第2電極は、複数の前記配線に沿って設けられている
請求項6に記載の表示装置。 - 複数の前記第2電極は、前記制御部からの制御信号に応じて、
前記表示期間、前記第1センサ期間及び前記第2センサ期間に、前記共通電極と同じ信号が供給される
請求項6から請求項11のいずれか1項に記載の表示装置。 - 複数の前記第2電極は、前記制御部からの制御信号に応じて、
前記表示期間には共通電極と同じ電位信号が供給され
前記第1センサ期間には、前記第1駆動信号が供給される前記共通電極に対向する前記第2電極に前記第1駆動信号と同じ電位信号が供給され、
前記第2センサ期間には、前記第2駆動信号が供給される前記共通電極に対向する前記第2電極に前記第2駆動信号と同じ電位信号が供給される、
請求項12に記載の表示装置。
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