JP2018107373A - Chip resistor - Google Patents
Chip resistor Download PDFInfo
- Publication number
- JP2018107373A JP2018107373A JP2016254909A JP2016254909A JP2018107373A JP 2018107373 A JP2018107373 A JP 2018107373A JP 2016254909 A JP2016254909 A JP 2016254909A JP 2016254909 A JP2016254909 A JP 2016254909A JP 2018107373 A JP2018107373 A JP 2018107373A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- trimming groove
- region
- electrode
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Details Of Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
本発明は、抵抗体にトリミング溝を形成することによって抵抗値が調整されるチップ抵抗器に係り、より詳しくは、一対の表電極間に複数の抵抗体が並列接続されているチップ抵抗器に関するものである。 The present invention relates to a chip resistor whose resistance value is adjusted by forming a trimming groove in the resistor, and more particularly to a chip resistor in which a plurality of resistors are connected in parallel between a pair of surface electrodes. Is.
一般的にチップ抵抗器は、直方体形状の絶縁基板と、絶縁基板の表面における相対する両辺部に沿って設けられた一対の表電極と、これら一対の表電極間に接続された矩形状の抵抗体等によって主に構成されており、抵抗体には抵抗値を調整するためのトリミング溝が形成されている。 In general, a chip resistor is a rectangular parallelepiped insulating substrate, a pair of front electrodes provided along opposite sides of the surface of the insulating substrate, and a rectangular resistor connected between the pair of front electrodes. A trimming groove for adjusting a resistance value is formed in the resistor.
この種のチップ抵抗器において、図５に示すように、直方体形状の絶縁基板１００の両長辺に沿って形成された一対の表電極１０１間に複数の抵抗体１０２，１０３，１０４を並列に接続し、そのうち抵抗体１０３に一対のトリミング溝１０５を形成し、残りの抵抗体１０２と抵抗体１０４にはトリミング溝を形成しないように構成したものが従来技術として提案されている（特許文献１参照）。ここで、トリミング溝が形成されていない方の抵抗体１０２，１０４における電極間方向と直交する方向の最小抵抗体幅α１と、トリミング溝１０５が形成された方の抵抗体１０３における電極間方向と直交する方向の最小抵抗体幅α２、つまり、一対のトリミング溝１０５の先端部によって挟まれた抵抗体１０３の幅寸法とは略同一になるように形成されている。 In this type of chip resistor, as shown in FIG. 5, a plurality of resistors 102, 103, 104 are arranged in parallel between a pair of front electrodes 101 formed along both long sides of a rectangular parallelepiped insulating substrate 100. A conventional technique is proposed in which a pair of trimming grooves 105 are formed in the resistor 103 and no trimming grooves are formed in the remaining resistors 102 and 104 (Patent Document 1). reference). Here, the minimum resistor width α1 in the direction orthogonal to the inter-electrode direction in the resistors 102 and 104 where the trimming groove is not formed, and the inter-electrode direction in the resistor 103 where the trimming groove 105 is formed The minimum resistor width α2 in the orthogonal direction, that is, the width dimension of the resistor 103 sandwiched between the tips of the pair of trimming grooves 105 is formed to be substantially the same.
このように構成されたチップ抵抗器によれば、一対の表電極１０１間に幅広の抵抗体１０３と幅狭の抵抗体１０２，１０４を並列に接続し、幅広の抵抗体１０３のみにトリミング溝１０５が形成されるため、全ての抵抗体１０２，１０３，１０４にトリミング溝を形成する場合に比べてトリミング作業の手間を小さくすることができる。また、トリミング溝の形成されていない抵抗体１０２，１０４の最小抵抗体幅α１と、トリミング溝１０５が形成された抵抗体１０３の最小抵抗体幅α２とをほぼ同一にしているため、全ての抵抗体１０２，１０３，１０４で電流経路の最小幅を均一にでき、よって、任意の抵抗体の電気的特性や耐久性が低下してしまうことを防止できる。 According to the chip resistor configured as described above, the wide resistor 103 and the narrow resistors 102 and 104 are connected in parallel between the pair of front electrodes 101, and the trimming groove 105 is formed only in the wide resistor 103. Therefore, the labor of the trimming operation can be reduced as compared with the case where the trimming grooves are formed in all the resistors 102, 103, 104. In addition, since the minimum resistor width α1 of the resistors 102 and 104 in which the trimming groove is not formed and the minimum resistor width α2 of the resistor 103 in which the trimming groove 105 is formed are substantially the same, all the resistors It is possible to make the minimum width of the current path uniform in the bodies 102, 103, and 104, thereby preventing the electrical characteristics and durability of an arbitrary resistor from being lowered.
しかしながら、特許文献１に記載された従来技術のように、幅広の抵抗体１０３にトリミング溝１０５を形成して幅狭の抵抗体１０２，１０４と最小抵抗体幅を同一にしたとしても、この抵抗体１０３には最小抵抗体幅α２を規定する領域の外側に表電極１０１と接続する部分が存在するため、図５の符号Ｓ1で示す部分も電流が流れることになり、実際はトリミング溝１０５を形成した抵抗体１０３の方がトリミング溝を形成していない抵抗体１０２，１０４よりも抵抗値が低くなってしまい、各抵抗体１０２，１０３，１０４に抵抗値差が発生してしまう。その結果、抵抗値の低い方の抵抗体１０３に負荷が集中し、抵抗体の電気的特性や耐久性に支障をきたす虞があり、特に、トリミング溝１０５の終端部分の抵抗体１０３にはマイクロクラックが生じ易いため、抵抗体１０２，１０４よりも耐久性に劣る抵抗体１０３に負荷が集中してしまい、支障をきたす虞がより高くなってしまう。 However, even if the trimming groove 105 is formed in the wide resistor 103 and the minimum resistor width is made the same as that of the narrow resistors 102 and 104 as in the prior art described in Patent Document 1, this resistance Since the body 103 has a portion connected to the surface electrode 101 outside the region defining the minimum resistor width α2, the current flows also in the portion indicated by reference numeral S1 in FIG. 5, and the trimming groove 105 is actually formed. The resistance value of the resistor 103 is lower than that of the resistors 102 and 104 in which the trimming grooves are not formed, and a difference in resistance value occurs between the resistors 102, 103, and 104. As a result, the load is concentrated on the resistor 103 having the lower resistance value, which may impair the electrical characteristics and durability of the resistor. Since cracks are likely to occur, the load concentrates on the resistor 103 which is inferior in durability to the resistors 102 and 104, and the possibility of causing trouble becomes higher.
本発明は、このような従来技術の実情に鑑みてなされたもので、その目的は、表電極に並列接続した複数の抵抗体の一部だけにトリミング溝を形成してトリミング作業の手間を小さくした上で、トリミング溝有りの抵抗体とトリミング溝無しの抵抗体の抵抗値差を小さくできるチップ抵抗器を提供することにある。 The present invention has been made in view of the actual situation of the prior art, and an object thereof is to reduce the labor of trimming work by forming trimming grooves only in a part of a plurality of resistors connected in parallel to the surface electrode. In addition, an object of the present invention is to provide a chip resistor that can reduce the difference in resistance value between a resistor with a trimming groove and a resistor without a trimming groove.
上記の目的を達成するために、本発明のチップ抵抗器は、直方体形状の絶縁基板と、この絶縁基板の表面における相対する両辺部に沿って設けられた一対の表電極と、これら一対の表電極間に並列に接続された複数の抵抗体とを備え、前記複数の抵抗体が、トリミング溝の形成されていない矩形状の第１抵抗体と、トリミング溝が形成された第２抵抗体とからなると共に、前記第１抵抗体と前記第２抵抗体の電極間方向と直交する方向の最小抵抗体幅が均一に形成されているチップ抵抗器において、前記表電極に電極間距離を異にする第１領域と第２領域とが形成されており、前記第１抵抗体を電極間距離が短い方の前記第１領域に接続すると共に、前記第２抵抗体を電極間距離が長い方の前記第２領域に接続したことを特徴としている。 In order to achieve the above object, a chip resistor of the present invention includes a rectangular parallelepiped insulating substrate, a pair of front electrodes provided along opposite sides of the surface of the insulating substrate, and the pair of front and rear surfaces. A plurality of resistors connected in parallel between the electrodes, wherein the plurality of resistors are a rectangular first resistor having no trimming groove formed thereon, and a second resistor having a trimming groove formed thereon. A chip resistor having a uniform minimum resistor width in a direction orthogonal to the direction between the electrodes of the first resistor and the second resistor, wherein the distance between the electrodes is different between the surface electrodes. A first region and a second region are formed, the first resistor is connected to the first region having a shorter inter-electrode distance, and the second resistor is connected to a longer inter-electrode distance. It is characterized in that it is connected to the second region.
このように構成されたチップ抵抗器では、一対の表電極間に並列接続された第１抵抗体と第２抵抗体のうち、電極間距離が短い方の第１領域に接続されて抵抗値の低い第１抵抗体にトリミング溝は形成されておらず、電極間距離が長い方の第２領域に接続されて抵抗値の高い第２抵抗体のみにトリミング溝が形成されているため、トリミング溝を有していない第１抵抗体とトリミング溝を有している第２抵抗体との抵抗値差が小さくなり、トリミング溝が形成された第２抵抗体への負荷集中を軽減することができる。 In the chip resistor configured as described above, the resistance value of the first resistor and the second resistor connected in parallel between the pair of surface electrodes is connected to the first region having the shorter inter-electrode distance. The trimming groove is not formed in the low first resistor, and the trimming groove is formed only in the second resistor having a high resistance value connected to the second region having the longer inter-electrode distance. The difference in resistance value between the first resistor having no trim and the second resistor having the trimming groove is reduced, and the load concentration on the second resistor having the trimming groove can be reduced. .
上記構成のチップ抵抗器において、表電極に並列接続される第１抵抗体と第２抵抗体の数は特に限定されないが、少なくとも２つ以上の第１抵抗体を形成する場合は、第１抵抗体と第２抵抗体がガラス材料からなるアンダーコート層によって覆われていると共に、絶縁基板の表電極が延在しない方の両辺部に、第２抵抗体を挟んで２つの第１抵抗体が並設されていることが好ましい。このようにすると、表電極が延在せずに水分の入り込みやすい方の絶縁基板の両辺部近傍に位置する第１抵抗体は、抵抗体の露出するトリミング溝が形成されていないため、マイグレーションによる抵抗値変化を防止できる共に耐湿性を高めることができる。 In the chip resistor having the above configuration, the number of the first resistor and the second resistor connected in parallel to the surface electrode is not particularly limited, but when forming at least two or more first resistors, the first resistor The body and the second resistor are covered by an undercoat layer made of a glass material, and the two first resistors are sandwiched between the second resistor on both sides of the insulating substrate where the surface electrode does not extend. It is preferable that they are arranged side by side. In this case, the first resistor located near both sides of the insulating substrate that does not extend the surface electrode and easily enters moisture is not formed with a trimming groove that exposes the resistor. Resistance value change can be prevented and moisture resistance can be improved.
本発明によれば、表電極に並列接続した複数の抵抗体の一部だけにトリミング溝を形成してトリミング作業の手間を小さくした上で、トリミング溝有りの抵抗体とトリミング溝無しの抵抗体の抵抗値差が小さくなるため、トリミング溝が形成された抵抗体への負荷集中を軽減したチップ抵抗器を提供することができる。 According to the present invention, a trimming groove is formed only in a part of a plurality of resistors connected in parallel to the surface electrode to reduce the labor of trimming work, and a resistor with a trimming groove and a resistor without a trimming groove are provided. Therefore, it is possible to provide a chip resistor that reduces the load concentration on the resistor in which the trimming groove is formed.
発明の実施の形態について図面を参照して説明すると、図１と図２に示すように、本発明の第１実施形態例に係るチップ抵抗器は、セラミックス等からなる直方体形状の絶縁基板１と、絶縁基板１の表面における短手方向（Ｙ方向）の両端部に設けられた一対の表電極２と、これら一対の表電極２の間に並列に接続された第１抵抗体３および第２抵抗体４と、第１抵抗体３および第２抵抗体４を覆うアンダーコート層５と、アンダーコート層５を覆うオーバーコート層６等によって主に構成されており、第２抵抗体４には絶縁基板１の長手方向（Ｘ方向）に沿って直線状に延びるトリミング溝７が形成されている。なお、図示省略されているが、絶縁基板１の裏面には表電極２に対応するように一対の裏電極が設けられており、絶縁基板１の短手方向の両端面には対応する表電極と裏電極を橋絡する端面電極が設けられている。 The embodiment of the invention will be described with reference to the drawings. As shown in FIGS. 1 and 2, the chip resistor according to the first embodiment of the present invention includes a rectangular parallelepiped insulating substrate 1 made of ceramics and the like. The pair of surface electrodes 2 provided at both ends in the short direction (Y direction) on the surface of the insulating substrate 1, and the first resistor 3 and the second resistor 2 connected in parallel between the pair of surface electrodes 2 The resistor 4 is mainly composed of an undercoat layer 5 that covers the first resistor 3 and the second resistor 4, an overcoat layer 6 that covers the undercoat layer 5, and the like. A trimming groove 7 extending linearly along the longitudinal direction (X direction) of the insulating substrate 1 is formed. Although not shown in the drawing, a pair of back electrodes is provided on the back surface of the insulating substrate 1 so as to correspond to the front electrode 2, and corresponding front electrodes on both end surfaces in the short direction of the insulating substrate 1. And an end face electrode for bridging the back electrode.
一対の表電極２は絶縁基板１の相対する長辺に沿って帯状に形成されており、これら表電極２はＡｇペーストをスクリーン印刷して乾燥・焼成させたものである。ここで、一対の表電極２の対向辺は段付き形状に形成されており、図示左側部分は電極間距離の短い第１領域２ａとなっており、図示右側部分は電極間距離の長い第２領域２ｂとなっている。 The pair of front electrodes 2 are formed in a strip shape along the opposing long sides of the insulating substrate 1, and these front electrodes 2 are obtained by screen-printing Ag paste, drying and firing. Here, the opposing sides of the pair of front electrodes 2 are formed in a stepped shape, the left portion in the figure is a first region 2a having a short inter-electrode distance, and the right portion in the figure is a second having a long inter-electrode distance. Region 2b is formed.
第１抵抗体３は平面視で矩形状に形成されており、そのＹ方向の両端部はそれぞれ表電極２の第１領域２ａに接続されている。第２抵抗体４もトリミング溝７の形成前は平面視で矩形状に形成されており、そのＹ方向の両端部はそれぞれ表電極２の第２領域２ｂに接続されている。これら第１抵抗体３と第２抵抗体４は酸化ルテニウム等の抵抗体ペーストをスクリーン印刷して乾燥・焼成させたものであり、第１抵抗体３の幅寸法Ｗ１に対して第２抵抗体４の幅寸法Ｗ２は十分に大きく設定されている。 The first resistor 3 is formed in a rectangular shape in plan view, and both ends in the Y direction are connected to the first region 2 a of the surface electrode 2, respectively. The second resistor 4 is also formed in a rectangular shape in plan view before the trimming groove 7 is formed, and both ends in the Y direction are connected to the second region 2b of the surface electrode 2, respectively. The first resistor 3 and the second resistor 4 are obtained by screen-printing a resistor paste such as ruthenium oxide, drying and firing, and the second resistor 3 with respect to the width W1 of the first resistor 3. The width dimension W2 of 4 is set sufficiently large.
トリミング溝７は第２抵抗体４の左辺４ａから右辺４ｂに向かって直線状に延びるスリットであり、このようなトリミング溝７を第２抵抗体４に形成することにより、トリミング溝を有していない第１抵抗体３における電極間方向と直交する方向（Ｘ方向）の最小抵抗体幅α１（＝Ｗ１）と、トリミング溝７の形成後の第２抵抗体４における電極間方向と直交する方向の最小抵抗体幅α２とが略同一になるようなっている。すなわち、第２抵抗体４はもともと第１抵抗体３と同様に矩形状の外観を呈しているが、トリミング溝７を形成することによって図１に示すような形状となる。 The trimming groove 7 is a slit that extends linearly from the left side 4 a to the right side 4 b of the second resistor 4. By forming such a trimming groove 7 in the second resistor 4, the trimming groove 7 has a trimming groove. The minimum resistor width α1 (= W1) in the direction (X direction) orthogonal to the interelectrode direction in the first resistor 3 that is not present, and the direction orthogonal to the interelectrode direction in the second resistor 4 after the trimming groove 7 is formed The minimum resistor width α2 is substantially the same. That is, the second resistor 4 originally has a rectangular appearance like the first resistor 3, but the shape shown in FIG. 1 is obtained by forming the trimming groove 7.
アンダーコート層５はガラスペーストをスクリーン印刷して焼成させたものであり、このアンダーコート層５はトリミング溝７を形成する前に第１抵抗体３と第２抵抗体４の両方を覆うように形成されている。 The undercoat layer 5 is obtained by screen-printing and baking a glass paste, and this undercoat layer 5 covers both the first resistor 3 and the second resistor 4 before the trimming groove 7 is formed. Is formed.
オーバーコート層６はエポキシ系樹脂ペーストをスクリーン印刷して加熱硬化させたものであり、このオーバーコート層６は、アンダーコート層５の上から第２抵抗体４にトリミング溝７を形成した後に、トリミング溝７を含めて第１抵抗体３と第２抵抗体４上のアンダーコート層５を全体的に覆うように形成されている。 The overcoat layer 6 is obtained by screen-printing and curing an epoxy resin paste, and this overcoat layer 6 is formed after the trimming groove 7 is formed on the second resistor 4 from above the undercoat layer 5. The undercoat layer 5 on the first resistor 3 and the second resistor 4 is formed so as to entirely cover the trimming groove 7.
次に、このように構成されたチップ抵抗器の製造工程について、図３を参照しながら説明する。 Next, a manufacturing process of the chip resistor configured as described above will be described with reference to FIG.
まず、図３（ａ）に示すように、絶縁基板１が多数個取りされる大判基板１Ａを準備する。この大判基板１Ａには予め１次分割溝と２次分割溝（いずれも図示省略）が格子状に設けられており、両分割溝によって区切られたマス目の１つ１つが１個分のチップ領域となる。なお、図３では１個分のチップ領域に相当する大判基板１Ａが代表的に示されているが、実際は多数個分のチップ領域に相当する大判基板１Ａに対して以下に説明する各工程が一括して行われる。 First, as shown in FIG. 3A, a large substrate 1A from which a large number of insulating substrates 1 are taken is prepared. The large substrate 1A is preliminarily provided with a primary dividing groove and a secondary dividing groove (both not shown) in a lattice shape, and each of the squares divided by both the dividing grooves is one chip. It becomes an area. FIG. 3 representatively shows a large substrate 1A corresponding to one chip area. Actually, however, each process described below is performed for a large substrate 1A corresponding to many chip areas. It is done in a lump.
まず、大判基板１Ａの表面にＡｇペーストをスクリーン印刷した後、これを乾燥・焼成することにより、図３（ｂ）に示すように、大判基板１Ａの相対する両長辺に沿って一対の表電極２を帯状に形成する。その際、これら表電極２の対向辺には段付き形状の第１領域２ａと第２領域２ｂが形成され、第１領域２ａの電極間距離をＬ１、第２領域２ｂの電極間距離をＬ２とすると、第１領域２ａの電極間距離Ｌ１よりも第２領域２ｂの電極間距離Ｌ２の方が長く設定される（Ｌ１＜Ｌ２）。 First, an Ag paste is screen-printed on the surface of the large substrate 1A, and then dried and baked. As shown in FIG. 3B, a pair of tables are formed along both opposing long sides of the large substrate 1A. The electrode 2 is formed in a strip shape. At this time, a step-shaped first region 2a and second region 2b are formed on opposite sides of the surface electrode 2, and the distance between the electrodes of the first region 2a is L1, and the distance between the electrodes of the second region 2b is L2. Then, the interelectrode distance L2 of the second region 2b is set longer than the interelectrode distance L1 of the first region 2a (L1 <L2).
図示省略されているが、この表電極形成工程に前後して大判基板１Ａの裏面にＡｇペーストをスクリーン印刷し、これを乾燥・焼成することにより、大判基板１Ａの裏面に図示せぬ一対の裏電極を形成する。 Although not shown in the figure, before and after the front electrode forming step, an Ag paste is screen-printed on the back surface of the large substrate 1A, and dried and baked, whereby a pair of back surfaces not shown on the back surface of the large substrate 1A. An electrode is formed.
次に、大判基板１Ａの表面に酸化ルテニウム等の抵抗体ペーストをスクリーン印刷した後、これを乾燥・焼成することにより、図３（ｃ）に示すように、一対の表電極２の電極間距離が短い方の第１領域２ａに接続された第１抵抗体３と、電極間距離が長い方の第２領域２ｂに接続された第２抵抗体４とを形成する。ここで、第１抵抗体３と第２抵抗体４はいずれも平面視で矩形状に形成されているが、第１抵抗体３の幅寸法Ｗ１に対して第２抵抗体４の幅寸法Ｗ２は十分に大きくなっている。 Next, after a resistor paste such as ruthenium oxide is screen-printed on the surface of the large-sized substrate 1A, this is dried and fired to obtain a distance between the pair of front electrodes 2 as shown in FIG. The first resistor 3 connected to the shorter first region 2a and the second resistor 4 connected to the second region 2b having the longer interelectrode distance are formed. Here, both the first resistor 3 and the second resistor 4 are formed in a rectangular shape in a plan view, but the width dimension W2 of the second resistor 4 with respect to the width dimension W1 of the first resistor 3. Is big enough.
次に、第１抵抗体３と第２抵抗体４の上からガラスペーストをスクリーン印刷して焼成することにより、図３（ｄ）に示すように、第１抵抗体３と第２抵抗体４を覆うアンダーコート層５を形成する。 Next, the first resistor 3 and the second resistor 4 are screen-printed and fired from above the first resistor 3 and the second resistor 4 as shown in FIG. Undercoat layer 5 is formed to cover
次いで、一対の表電極２に図示せぬプローブを当てながら、アンダーコート層５の上からレーザ光を照射して第２抵抗体４の左辺４ａからトリミングを開始していき、一対の表電極２間の抵抗値が所定の抵抗値になるまでトリミングすることにより、図３（ｅ）に示すように、第２抵抗体４に幅方向へ直線状に延びるトリミング溝７を形成する。 Next, while applying a probe (not shown) to the pair of front electrodes 2, laser light is irradiated from above the undercoat layer 5 to start trimming from the left side 4 a of the second resistor 4. By trimming until the resistance value between them becomes a predetermined resistance value, a trimming groove 7 extending linearly in the width direction is formed in the second resistor 4 as shown in FIG.
ここで、トリミング溝７の先端（終端）から第２抵抗体４の右辺４ｂまでの長さ（第２抵抗体４の最小抵抗体幅α２）が第１抵抗体３の最小抵抗体幅α１（＝Ｗ１）と略同一となった場合に、一対の表電極２間の抵抗値が所定の抵抗値となるように、予め第１抵抗体３と第２抵抗体４の大きさを決定しておく。つまり、第１抵抗体３および第２抵抗体４の幅寸法Ｗ１，Ｗ２と、両表電極２間の抵抗値が所定値となる場合のトリミング溝７の切込み量との関係のデータを入手しておき、第２抵抗体４の最小抵抗体幅α２が第１抵抗体３の最小抵抗体幅α１（＝Ｗ１）とほぼ同一となった場合に所定の抵抗値となるように、幅α１，α２の長さと第１および第２抵抗体３，４の電極間方向に沿う長さを設定しておく。 Here, the length (minimum resistor width α2 of the second resistor 4) from the tip (end) of the trimming groove 7 to the right side 4b of the second resistor 4 is the minimum resistor width α1 of the first resistor 3 ( = W1), the sizes of the first resistor 3 and the second resistor 4 are determined in advance so that the resistance value between the pair of front electrodes 2 becomes a predetermined resistance value. deep. That is, data on the relationship between the width dimensions W1 and W2 of the first resistor 3 and the second resistor 4 and the cutting depth of the trimming groove 7 when the resistance value between the surface electrodes 2 becomes a predetermined value is obtained. The width α1, so that the predetermined resistance value is obtained when the minimum resistor width α2 of the second resistor 4 is substantially the same as the minimum resistor width α1 (= W1) of the first resistor 3. The length of α2 and the length along the interelectrode direction of the first and second resistors 3 and 4 are set.
なお、ここでは第１抵抗体３の最小抵抗体幅α１と第２抵抗体４の最小抵抗体幅α２を略同じ寸法にさせつつ抵抗値調整ができる方法について説明したが、特にこの方法に限られるものでなく、例えばトリミング形状をＬカット（前記トリミング溝終端から９０度ターンさせた形状）とし、ターン前のトリミング溝にて第１抵抗体３の最小抵抗体幅α１と第２抵抗体４の最小抵抗体幅α２を略同じ寸法にさせ、ターン後のトリミング溝にて抵抗値調整を行う方法を用いるなど、第２抵抗体４の最小抵抗体幅α２と抵抗値調整が両立できる方法を適宜採用することも可能である。 Here, a method has been described in which the resistance value can be adjusted while making the minimum resistor width α1 of the first resistor 3 and the minimum resistor width α2 of the second resistor 4 substantially the same dimensions. For example, the trimming shape is an L cut (a shape turned 90 degrees from the end of the trimming groove), and the minimum resistor width α1 of the first resistor 3 and the second resistor 4 in the trimming groove before the turn. A method in which the minimum resistor width α2 of the second resistor 4 and the resistance value adjustment can be made compatible, such as a method of adjusting the resistance value in the trimming groove after the turn by making the minimum resistor width α2 of the second resistor 4 substantially the same size. It is also possible to adopt as appropriate.
次に、アンダーコート層５を覆うようにエポキシ系等の樹脂ペーストをスクリーン印刷した後、これを加熱硬化することにより、図３（ｆ）に示すように、第１抵抗体３と第２抵抗体４を覆うオーバーコート層６を形成する。このオーバーコート層６はトリミング溝７を覆って外部環境から保護するためのものであり、このようにトリミング溝７が形成された第２抵抗体４をアンダーコート層５とオーバーコート層６で覆うことにより、湿度に影響されないチップ抵抗器が実現されるようになっている。 Next, an epoxy-based resin paste or the like is screen-printed so as to cover the undercoat layer 5 and then heat-cured, whereby the first resistor 3 and the second resistor are formed as shown in FIG. An overcoat layer 6 covering the body 4 is formed. The overcoat layer 6 covers the trimming groove 7 and protects it from the external environment. The second resistor 4 in which the trimming groove 7 is thus formed is covered with the undercoat layer 5 and the overcoat layer 6. As a result, a chip resistor that is not affected by humidity is realized.
ここまでの各工程は多数個取り用の大判基板１Ａに対する一括処理であるが、次なる工程では、大判基板１Ａを１次分割溝に沿って短冊状に分割するという１次ブレーク加工を行うことより、複数個分のチップ領域が設けられた図示せぬ短冊状基板を得る。しかる後、短冊状基板の分割面に表電極２と裏電極を橋絡する図示せぬ端面電極を形成した後、短冊状基板を２次分割溝に沿って分割するという２次ブレーク加工を行うことにより、チップ抵抗器と同等の大きさの個片（チップ単体）に細分割して図１に示すようなチップ抵抗器を得る。最後に、個片化された各チップ単体の絶縁基板１の短手方向両端部に電解メッキを施すことにより、チップ抵抗器を完成することができる。 Each process so far is a batch process for a large-sized substrate 1A for multi-cavity, but in the next process, a primary break process is performed in which the large-sized substrate 1A is divided into strips along the primary dividing groove. Thus, a strip-shaped substrate (not shown) provided with a plurality of chip regions is obtained. Thereafter, after forming an end face electrode (not shown) that bridges the front electrode 2 and the back electrode on the dividing surface of the strip-shaped substrate, a secondary break process is performed in which the strip-shaped substrate is divided along the secondary dividing groove. Thus, the chip resistor as shown in FIG. 1 is obtained by being subdivided into individual pieces (chip alone) having the same size as the chip resistor. Finally, the chip resistor can be completed by performing electrolytic plating on both ends in the short direction of the insulating substrate 1 of each chip separated into individual pieces.
以上説明したように、本実施形態例に係るチップ抵抗器は、一対の表電極２間に並列接続された第１抵抗体３と第２抵抗体４のうち、第２抵抗体４のみにトリミング溝７が形成されているため、全ての抵抗体３，４にトリミング溝を形成する場合に比べてトリミング作業の手間を小さくすることができる。また、トリミング溝の形成されていない第１抵抗体３の最小抵抗体幅α１と、トリミング溝７が形成された第２抵抗体４の最小抵抗体幅α２とをほぼ同一にしているため、全ての抵抗体３，４で電流経路の最小幅を均一にでき、よって、任意の抵抗体の電気的特性や耐久性が低下してしまうことを防止できる。 As described above, the chip resistor according to this embodiment is trimmed only to the second resistor 4 among the first resistor 3 and the second resistor 4 connected in parallel between the pair of front electrodes 2. Since the grooves 7 are formed, it is possible to reduce the labor of the trimming work compared to the case where the trimming grooves are formed in all the resistors 3 and 4. Further, since the minimum resistor width α1 of the first resistor 3 in which the trimming groove is not formed and the minimum resistor width α2 of the second resistor 4 in which the trimming groove 7 is formed are substantially the same, The minimum width of the current path can be made uniform by the resistors 3 and 4, and therefore it is possible to prevent the electrical characteristics and durability of an arbitrary resistor from deteriorating.
ここで、第１抵抗体３は電極間距離Ｌ１が短い方の第１領域２ａに接続され、第２抵抗体４は電極間距離Ｌ２が長い方の第２領域２ｂに接続されているため、第１抵抗体３の最小抵抗値幅とトリミング溝７が形成された第２抵抗体４の最小抵抗値幅とを均一にした場合でも、トリミング溝を有していない第１抵抗体３とトリミング溝７を有している第２抵抗体４との抵抗値差が小さくなり、トリミング溝７が形成された第２抵抗体への負荷集中を軽減することができる。 Here, the first resistor 3 is connected to the first region 2a having the shorter interelectrode distance L1, and the second resistor 4 is connected to the second region 2b having the longer interelectrode distance L2, Even when the minimum resistance value width of the first resistor 3 and the minimum resistance value width of the second resistor 4 in which the trimming groove 7 is formed are uniform, the first resistor 3 and the trimming groove 7 having no trimming groove are provided. Therefore, the difference in resistance value with the second resistor 4 having the above becomes small, and the load concentration on the second resistor in which the trimming groove 7 is formed can be reduced.
なお、上記第１実施形態例では、一対の表電極２に２つの抵抗体３，４を並列接続したチップ抵抗器について説明したが、両表電極２に並列接続される抵抗体の数は２つに限定されず、第１抵抗体３と第２抵抗体４の総数が３つ以上であっても良い。 In the first embodiment, a chip resistor in which two resistors 3 and 4 are connected in parallel to a pair of surface electrodes 2 has been described. However, the number of resistors connected in parallel to both surface electrodes 2 is two. However, the total number of the first resistor 3 and the second resistor 4 may be three or more.
例えば、図４に示す第２実施形態例に係るチップ抵抗器のように、一対の表電極２間に２つの第１抵抗体３と１つの第２抵抗体４を並列接続し、これら３つの抵抗体のうち、中央の第２抵抗体４を挟んで２つの第１抵抗体３を絶縁基板１の長手方向両端部に配置するという構成にしても良い。この場合、一対の表電極２には第２領域２ｂを挟んで長手方向の両端部２箇所に第１領域２ａが形成されており、電極間距離が短い方の２つの第１領域２ａにそれぞれ第１抵抗体３が接続されると共に、電極間距離が長い方の第２領域２ｂに第２抵抗体４が接続され、この第２抵抗体４に対して２つのトリミング溝７が形成されている。 For example, like the chip resistor according to the second embodiment shown in FIG. 4, two first resistors 3 and one second resistor 4 are connected in parallel between a pair of surface electrodes 2, and the three Of the resistors, two first resistors 3 may be arranged at both ends in the longitudinal direction of the insulating substrate 1 with the second resistor 4 at the center interposed therebetween. In this case, a pair of front electrodes 2 are formed with two first regions 2a at both ends in the longitudinal direction across the second region 2b, and each of the two first regions 2a having a shorter inter-electrode distance is provided. The first resistor 3 is connected, and the second resistor 4 is connected to the second region 2b having the longer inter-electrode distance, and two trimming grooves 7 are formed in the second resistor 4 Yes.
このように構成された第２実施形態例に係るチップ抵抗器では、絶縁基板１の長手方向の両端部２箇所にトリミング溝の形成されない第１抵抗体３が配置され、これら２つの第１抵抗体３で挟まれた第２抵抗体４にトリミング溝７が形成されているため、トリミング溝７によって生じる破断面は第１抵抗体３の内方側の辺部と対向することになる。そして、これら第１抵抗体３は絶縁基板１との密着性に優れたガラス材料からなるアンダーコート層５によって覆われているため、マイグレーションによる抵抗値変化を防止できて耐湿性にも優れたチップ抵抗器を実現することができる。 In the chip resistor according to the second embodiment configured as described above, the first resistor 3 in which the trimming groove is not formed is arranged at two positions in the longitudinal direction of the insulating substrate 1, and the two first resistors Since the trimming groove 7 is formed in the second resistor 4 sandwiched between the bodies 3, the fracture surface generated by the trimming groove 7 faces the inner side of the first resistor 3. Since these first resistors 3 are covered with an undercoat layer 5 made of a glass material having excellent adhesion to the insulating substrate 1, a chip that can prevent a change in resistance value due to migration and has excellent moisture resistance. A resistor can be realized.
１ 絶縁基板
２ 表電極
２ａ 第１領域
２ｂ 第２領域
３ 第１抵抗体
４ 第２抵抗体
５ アンダーコート層
６ オーバーコート層
７ トリミング溝
DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Front electrode 2a 1st area | region 2b 2nd area | region 3 1st resistor 4 2nd resistor 5 Undercoat layer 6 Overcoat layer 7 Trimming groove
Claims (2)
前記表電極に電極間距離を異にする第１領域と第２領域とが形成されており、前記第１抵抗体を電極間距離が短い方の前記第１領域に接続すると共に、前記第２抵抗体を電極間距離が長い方の前記第２領域に接続したことを特徴とするチップ抵抗器。 A rectangular parallelepiped insulating substrate, a pair of front electrodes provided along opposite sides of the surface of the insulating substrate, and a plurality of resistors connected in parallel between the pair of front electrodes, The plurality of resistors include a rectangular first resistor having no trimming groove and a second resistor having a trimming groove, and electrodes of the first resistor and the second resistor. In the chip resistor in which the minimum resistor width in the direction orthogonal to the inter-direction is formed uniformly,
A first region and a second region having different inter-electrode distances are formed on the front electrode, and the first resistor is connected to the first region having a shorter inter-electrode distance, and the second region A chip resistor comprising a resistor connected to the second region having a longer inter-electrode distance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016254909A JP2018107373A (en) | 2016-12-28 | 2016-12-28 | Chip resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016254909A JP2018107373A (en) | 2016-12-28 | 2016-12-28 | Chip resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2018107373A true JP2018107373A (en) | 2018-07-05 |
Family
ID=62787949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016254909A Pending JP2018107373A (en) | 2016-12-28 | 2016-12-28 | Chip resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2018107373A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS646004U (en) * | 1987-06-30 | 1989-01-13 | ||
| JP2005123424A (en) * | 2003-10-17 | 2005-05-12 | Taiyosha Electric Co Ltd | Chip resistor |
-
2016
- 2016-12-28 JP JP2016254909A patent/JP2018107373A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS646004U (en) * | 1987-06-30 | 1989-01-13 | ||
| JP2005123424A (en) * | 2003-10-17 | 2005-05-12 | Taiyosha Electric Co Ltd | Chip resistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI687942B (en) | Chip resistor and method for manufacturing chip resistor | |
| JP6371187B2 (en) | Resistor trimming method | |
| WO2007029635A1 (en) | Chip resistor and method for producing the same | |
| JP6479361B2 (en) | Chip resistor | |
| JP2018010987A (en) | Chip resistor and manufacturing method of chip resistor | |
| JP6371080B2 (en) | Manufacturing method of chip resistor | |
| US10096409B2 (en) | Chip resistor and method for manufacturing same | |
| JP2018107373A (en) | Chip resistor | |
| JP2018088497A (en) | Chip resistor and manufacturing method for the same | |
| WO2019082523A1 (en) | Chip resistor and method for manufacturing chip resistor | |
| JP6615637B2 (en) | Manufacturing method of chip resistor | |
| JP6749752B2 (en) | Chip resistor and method of manufacturing chip resistor | |
| JP2018107374A (en) | Chip resistor | |
| JP2018107375A (en) | Chip resistor | |
| JP2017224677A (en) | Chip resistor and manufacturing method thereof | |
| JP6731246B2 (en) | Manufacturing method of chip resistor | |
| JP6498885B2 (en) | Chip resistor and chip resistor trimming method | |
| TWI817476B (en) | Chip resistor and method of manufacturing chip resistor | |
| JP6393484B2 (en) | Chip resistor | |
| US11742116B2 (en) | Chip resistor | |
| JP2016225572A (en) | Chip resistor and method of manufacturing the same | |
| JP2016131169A (en) | Chip resistor | |
| JPH0897018A (en) | Manufacture of chip resistor | |
| JP2022159796A (en) | Chip resistor and manufacturing method thereof | |
| JP2019016643A (en) | Chip resistor and method of manufacturing chip resistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20191125 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20200812 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200908 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20210302 |