JP2018037687A - Semiconductor device and manufacturing method for the same - Google Patents

Semiconductor device and manufacturing method for the same Download PDF

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JP2018037687A
JP2018037687A JP2017227702A JP2017227702A JP2018037687A JP 2018037687 A JP2018037687 A JP 2018037687A JP 2017227702 A JP2017227702 A JP 2017227702A JP 2017227702 A JP2017227702 A JP 2017227702A JP 2018037687 A JP2018037687 A JP 2018037687A
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chip
wiring layer
electrode
layer
circuit surface
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JP6496389B2 (en
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一茂 河崎
Kazushige Kawasaki
一茂 河崎
栗田　洋一郎
Yoichiro Kurita
洋一郎 栗田
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Kioxia Corp
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Toshiba Memory Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method therefor which can reduce parasitic capacitance of a through electrode part.SOLUTION: A semiconductor device includes a second chip laminated on a first wiring layer of a first chip. The second chip has: a second semiconductor layer having a second circuit face opposite to the first wiring layer and a second rear face opposite to the second circuit face; a second wiring layer which is provided on the second circuit face and connected with the first wiring layer of the first chip; and a second through electrode which is provided so as to pass through the second semiconductor layer and connected with the second wiring layer. The semiconductor device includes a third chip laminated at a second rear face side of the second chip. The third chip has: a third semiconductor layer having a third circuit face and a third rear face opposite to the second chip; a third wiring layer provided on the third circuit face; and a third through electrode which is provided so as to pass through the third semiconductor layer, connected with the third wiring layer and connected with the second through electrode of the second chip. A distance between the first chip and the second chip is smaller than a distance between the second chip and the third chip.SELECTED DRAWING: Figure 1

Description

本発明の実施形態は、半導体装置及びその製造方法に関する。   Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

ＴＳＶ（Through-Silicon Via）を使った構造において、チップの積層数が多くなるなどＴＳＶの数が増えると、ＴＳＶとシリコン基板との間の寄生容量の増大をまねく。   In a structure using TSV (Through-Silicon Via), an increase in the number of TSVs such as an increase in the number of stacked chips leads to an increase in parasitic capacitance between the TSV and the silicon substrate.

米国特許第７１１９４２８号明細書US Pat. No. 7,119,428

本発明の実施形態は、貫通電極部分の寄生容量低減が可能な半導体装置及びその製造方法を提供する。   Embodiments of the present invention provide a semiconductor device capable of reducing the parasitic capacitance of a through electrode portion and a manufacturing method thereof.

実施形態によれば、半導体装置は、第１チップと、第２チップと、第３チップと、を備えている。前記第１チップは、第１回路面と、前記第１回路面の反対側の第１裏面とを有する第１半導体層と、前記第１回路面に設けられた第１配線層と、前記第１裏面に設けられた第１裏面電極と、前記第１半導体層を貫通して設けられ、前記第１配線層と前記第１裏面電極に接続された第１貫通電極と、前記第１配線層の前記第１回路面とは反対の面に向かって前記第１配線層に接続され銅を主成分とする第１接合金属を有する。前記第２チップは、前記第１チップの前記第１配線層側に積層されている。前記第２チップは、前記第１配線層に対向した第２回路面と、前記第２回路面の反対側の第２裏面とを有する第２半導体層と、前記第２回路面に設けられ、前記第１チップの前記第１配線層と接続された第２配線層と、前記第２裏面に設けられた第２裏面電極と、前記第２半導体層を貫通して設けられ、前記第２配線層と前記第２裏面電極に接続された第２貫通電極と、前記第２配線層の前記第２回路面とは反対の面に向かって前記第２配線層に接続された銅を主成分とし前記第１接合金属と接合されている第２接合金属と、を有する。前記第３チップは、前記第２チップの前記第２裏面側に積層されている。前記第３チップは、第３回路面と、前記第３回路面の反対側に位置し、前記第２チップに対向した第３裏面とを有する第３半導体層と、前記第３回路面に設けられた第３配線層と、前記第３裏面に設けられた第３裏面電極と、前記第３半導体層を貫通して設けられ、前記第３配線層と前記第３裏面電極に接続されるとともに、前記第２チップの前記第２貫通電極と接続された第３貫通電極と、前記第３配線層の前記第３回路面とは反対の面に向かって前記第３配線層に接続され銅を主成分とする第３接合金属を有する。前記第１のはんだは、前記第２裏面電極と前記第３裏面電極の間に設けられ前記第２裏面電極と前記第３裏面電極とに接続される。前記第１チップと前記第２チップとの距離は、前記第２チップと前記第３チップとの距離よりも短い。   According to the embodiment, the semiconductor device includes a first chip, a second chip, and a third chip. The first chip includes a first semiconductor layer having a first circuit surface and a first back surface opposite to the first circuit surface; a first wiring layer provided on the first circuit surface; A first back electrode provided on one back surface, a first through electrode provided through the first semiconductor layer and connected to the first wiring layer and the first back electrode, and the first wiring layer And having a first bonding metal mainly composed of copper connected to the first wiring layer toward a surface opposite to the first circuit surface. The second chip is stacked on the first wiring layer side of the first chip. The second chip is provided on the second circuit surface, a second semiconductor layer having a second circuit surface facing the first wiring layer, and a second back surface opposite to the second circuit surface, A second wiring layer connected to the first wiring layer of the first chip; a second back electrode provided on the second back surface; and the second wiring provided through the second semiconductor layer. And a second through electrode connected to the second back electrode and a copper connected to the second wiring layer toward a surface opposite to the second circuit surface of the second wiring layer. And a second bonding metal bonded to the first bonding metal. The third chip is stacked on the second back side of the second chip. The third chip is provided on the third circuit surface, and a third semiconductor layer having a third circuit surface and a third back surface located on the opposite side of the third circuit surface and facing the second chip. The third wiring layer formed, the third back electrode provided on the third back surface, and the third semiconductor layer, and connected to the third wiring layer and the third back electrode. The third through electrode connected to the second through electrode of the second chip and the copper connected to the third wiring layer toward the surface opposite to the third circuit surface of the third wiring layer It has the 3rd joining metal which makes a main component. The first solder is provided between the second back electrode and the third back electrode, and is connected to the second back electrode and the third back electrode. The distance between the first chip and the second chip is shorter than the distance between the second chip and the third chip.

実施形態の半導体装置の模式断面図。1 is a schematic cross-sectional view of a semiconductor device according to an embodiment. 実施形態の半導体装置の模式断面図。1 is a schematic cross-sectional view of a semiconductor device according to an embodiment. 実施形態の半導体装置の模式断面図。1 is a schematic cross-sectional view of a semiconductor device according to an embodiment. 実施形態の半導体装置の製造方法を示す模式断面図。FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. 実施形態の半導体装置の製造方法を示す模式断面図。FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. 実施形態の半導体装置の製造方法を示す模式断面図。FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. 実施形態の半導体装置の製造方法を示す模式断面図。FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. 実施形態の半導体装置の製造方法を示す模式断面図。FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. 実施形態の半導体装置の製造方法を示す模式断面図。FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. 実施形態の半導体装置における複数のチップの接続関係を示す模式図。The schematic diagram which shows the connection relation of the some chip | tip in the semiconductor device of embodiment. 実施形態の半導体装置の模式断面図。1 is a schematic cross-sectional view of a semiconductor device according to an embodiment.

以下、図面を参照し、実施形態について説明する。なお、各図面中、同じ要素には同じ符号を付している。   Hereinafter, embodiments will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element in each drawing.

図１（ａ）は、実施形態の半導体装置の模式断面図である。   FIG. 1A is a schematic cross-sectional view of the semiconductor device of the embodiment.

実施形態の半導体装置は、複数の半導体チップ（以下、単にチップともいう）１１の積層体が、実装基板（インターポーザ）５１上に実装され、封止樹脂８０に覆われている。   In the semiconductor device of the embodiment, a stacked body of a plurality of semiconductor chips (hereinafter also simply referred to as chips) 11 is mounted on a mounting substrate (interposer) 51 and covered with a sealing resin 80.

図１（ａ）には、例えば８個のチップ１１が積層された構造を例示するが、チップ１１の積層数は任意である。複数のチップ１１は、厚さ、平面サイズ、厚み方向の層構造および材料などが同じ、例えばメモリチップである。   FIG. 1A illustrates a structure in which, for example, eight chips 11 are stacked, but the number of chips 11 stacked is arbitrary. The plurality of chips 11 are, for example, memory chips having the same thickness, planar size, layer structure and material in the thickness direction, and the like.

実施形態によれば、２つのチップ１１が回路面１２ａどうしをフェイストゥフェイスで対向させてボンディングされた構成の２チップ積層体１０が複数積層されている。   According to the embodiment, a plurality of two-chip stacked bodies 10 having a configuration in which two chips 11 are bonded with the circuit surfaces 12a facing each other face-to-face are stacked.

２チップ積層体１０における１対のチップ１１は、後述するようにウェーハトゥウェーハボンディングにより接合される。複数の２チップ積層体１０どうしは、バンプ接続している。   The pair of chips 11 in the two-chip laminate 10 are bonded by wafer-to-wafer bonding as will be described later. The plurality of two-chip laminated bodies 10 are bump-connected.

図１（ｂ）は、図１におけるＡ部の拡大模式断面図であり、２チップ積層体１０の部分断面を表す。   FIG. 1B is an enlarged schematic cross-sectional view of part A in FIG. 1 and represents a partial cross section of the two-chip laminate 10.

それぞれのチップ１１は、半導体層１２と、配線層１３と、貫通電極１８と、接合金属（または中間電極）２１とを有する。   Each chip 11 includes a semiconductor layer 12, a wiring layer 13, a through electrode 18, and a bonding metal (or intermediate electrode) 21.

半導体層１２には、例えばシリコン基板を用いる。あるいは、半導体層１２には、ＳＯＩ（Silicon On Insulator）構造におけるシリコン層を用いる。また、半導体層１２には、シリコン以外の例えばＳｉＣ、ＧａＮなどの層（基板）を用いてもよい。以下の説明では、半導体層１２をシリコン基板として説明する。   For example, a silicon substrate is used for the semiconductor layer 12. Alternatively, a silicon layer having an SOI (Silicon On Insulator) structure is used for the semiconductor layer 12. For the semiconductor layer 12, a layer (substrate) such as SiC or GaN other than silicon may be used. In the following description, the semiconductor layer 12 is described as a silicon substrate.

シリコン基板１２は、回路面１２ａとその反対側の裏面１２ｂとを有する。ここでの裏面１２ｂとは、回路面１２ａに対する裏面を表す。   The silicon substrate 12 has a circuit surface 12a and a back surface 12b on the opposite side. The back surface 12b here represents the back surface with respect to the circuit surface 12a.

回路面１２ａには、図示しないトランジスタなどを含む半導体集積回路が形成されている。例えば、メモリチップの場合、回路面１２ａ上に電荷蓄積層、制御電極などが形成されている。   A semiconductor integrated circuit including a transistor (not shown) is formed on the circuit surface 12a. For example, in the case of a memory chip, a charge storage layer, a control electrode, and the like are formed on the circuit surface 12a.

回路面１２ａ上には、半導体集積回路、制御電極と接続された配線層１３が設けられている。図には、多層配線を例示するが、配線層１３は単層であってもよい。配線層１３と回路面１２ａとの間、配線層１３どうしの間、および最上層の配線層１３の上には、層間絶縁層１４が設けられている。   A wiring layer 13 connected to the semiconductor integrated circuit and the control electrode is provided on the circuit surface 12a. In the figure, multilayer wiring is illustrated, but the wiring layer 13 may be a single layer. An interlayer insulating layer 14 is provided between the wiring layer 13 and the circuit surface 12 a, between the wiring layers 13, and on the uppermost wiring layer 13.

層間絶縁層１４は、例えば、酸化シリコン（ＳｉＯ）、窒化シリコン（ＳｉＮ）、酸窒化シリコン（ＳｉＯＮ）、炭化窒化シリコン（ＳｉＣＮ）、酸化炭化シリコン（ＳｉＯＣ）の少なくともいずれかを含む。   The interlayer insulating layer 14 includes, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon oxide carbide (SiOC).

配線層１３は、いわゆるオンチップ配線層であり、樹脂中に設けられた再配線層（RDL:Redistribution Layer）とは異なる。   The wiring layer 13 is a so-called on-chip wiring layer and is different from a redistribution layer (RDL) provided in the resin.

層間絶縁層１４の表面上には、樹脂層１５が設けられている。樹脂層１５には、例えばベンゾシクロブテン（ＢＣＢ）樹脂を用いる。あるいは、樹脂層１５には、ポリイミド樹脂、またはエポキシ樹脂を用いる。   A resin layer 15 is provided on the surface of the interlayer insulating layer 14. For the resin layer 15, for example, benzocyclobutene (BCB) resin is used. Alternatively, polyimide resin or epoxy resin is used for the resin layer 15.

シリコン基板１２には貫通電極１８が設けられている。また、シリコン基板１２の裏面１２ｂには、裏面電極１９が設けられている。貫通電極１８は、裏面電極１９が形成された位置でシリコン基板１２を貫通し、裏面電極１９と配線層１３とを接続している。貫通電極１８は、例えば、銅を主成分として含む金属を用いる。   A through electrode 18 is provided in the silicon substrate 12. A back electrode 19 is provided on the back surface 12 b of the silicon substrate 12. The through electrode 18 penetrates the silicon substrate 12 at a position where the back electrode 19 is formed, and connects the back electrode 19 and the wiring layer 13. For the through electrode 18, for example, a metal containing copper as a main component is used.

貫通電極１８とシリコン基板１２との間には、貫通電極１８とシリコン基板１２との直接的な導通を防ぐ絶縁膜１７が設けられている。絶縁膜１７には、例えば、シリコン酸化膜、シリコン窒化膜、またはシリコン酸窒化膜を用いる。   An insulating film 17 is provided between the through electrode 18 and the silicon substrate 12 to prevent direct conduction between the through electrode 18 and the silicon substrate 12. As the insulating film 17, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used.

樹脂層１５には、接合金属（または中間電極）２１が埋め込まれている。接合金属２１は、樹脂層１５、および層間絶縁層１４の一部を貫通して、配線層１３に接続している。接合金属２１には、例えば銅を主成分として含む金属を用いる。   A bonding metal (or intermediate electrode) 21 is embedded in the resin layer 15. The bonding metal 21 penetrates part of the resin layer 15 and the interlayer insulating layer 14 and is connected to the wiring layer 13. As the bonding metal 21, for example, a metal containing copper as a main component is used.

以上説明した構造を有するチップ１１どうしが回路面１２ａ（配線層１３）側を対向させて接合され、２チップ積層体１０が形成されている。   The chips 11 having the above-described structure are joined with the circuit surface 12 a (wiring layer 13) facing each other to form a two-chip laminated body 10.

互いのチップ１１の接合金属２１どうしが接合され、且つ樹脂層１５どうしが接合（接着）されている。   The joining metals 21 of the chips 11 are joined together, and the resin layers 15 are joined (adhered).

図１（ａ）において、例えば最下層の２チップ積層体１０における上側のチップ１１の裏面電極１９と、その上の２チップ積層体１０における下側のチップ１１の裏面電極１９との間にはバンプ３１が設けられている。バンプ３１は、例えば、はんだボール、または金属バンプであり、上下のチップ１１の裏面電極１９どうしを接続している。すなわち、複数の２チップ積層体１０どうしはバンプ接続されている。   In FIG. 1A, for example, between the back electrode 19 of the upper chip 11 in the lowermost two-chip laminated body 10 and the back electrode 19 of the lower chip 11 in the upper two-chip laminated body 10 Bumps 31 are provided. The bumps 31 are, for example, solder balls or metal bumps, and connect the back electrodes 19 of the upper and lower chips 11. That is, the plurality of two-chip laminated bodies 10 are bump-connected.

図１（ａ）において、最下層の２チップ積層体１０における下側のチップ１１の裏面１２ｂには、再配線層４１が設けられている。最下層のチップ１１の裏面電極１９は、再配線層４１と接続されている。再配線層４１は、樹脂中に設けられ、チップ１１の配線層（オンチップ配線層）１３と、実装基板５１の配線層との接続を担う。   In FIG. 1A, a rewiring layer 41 is provided on the back surface 12 b of the lower chip 11 in the lowermost two-chip stacked body 10. The back electrode 19 of the lowermost chip 11 is connected to the rewiring layer 41. The rewiring layer 41 is provided in the resin, and is responsible for connection between the wiring layer (on-chip wiring layer) 13 of the chip 11 and the wiring layer of the mounting substrate 51.

再配線層４１の下面にはバンプ（例えば、はんだボール、金属バンプ）３２が設けられ、そのバンプ３２を介して複数のチップ１１を含む積層体は、実装基板５１上にマウントされている。実装基板５１の裏面には、外部端子（例えば、はんだボール、金属バンプ）５２が設けられている。   Bumps (for example, solder balls, metal bumps) 32 are provided on the lower surface of the rewiring layer 41, and the stacked body including the plurality of chips 11 is mounted on the mounting substrate 51 via the bumps 32. External terminals (for example, solder balls, metal bumps) 52 are provided on the back surface of the mounting substrate 51.

実装基板５１上の積層体は、封止樹脂８０で覆われている。また、樹脂８５が、２チップ積層体１０と２チップ積層体１０との間に充填されている。すなわち、バンプ３１の接合部は樹脂８５で覆われ保護されている。   The laminated body on the mounting substrate 51 is covered with a sealing resin 80. A resin 85 is filled between the two-chip laminate 10 and the two-chip laminate 10. That is, the joint portion of the bump 31 is covered and protected by the resin 85.

２チップ積層体１０における回路面１２ａどうしを対向させて接合された２つのチップ１１間の樹脂層１５のフィラー含有量は、バンプ３１を介して接続された２つのチップ１１間の樹脂８５のフィラー含有量よりも少ない。あるいは、樹脂層１５はフィラーを含まない。ウェーハ同士の接合では、バンプを介した接合に比較してチップ間の距離が短く、樹脂の熱膨張による信頼性への影響が小さいため、熱膨張を抑制するフィラー量は樹脂８５よりも少なくてもよい（あるいはフィラーが無くてもよい）。   The filler content of the resin layer 15 between the two chips 11 bonded with the circuit surfaces 12a facing each other in the two-chip laminate 10 is the filler of the resin 85 between the two chips 11 connected via the bumps 31. Less than the content. Or the resin layer 15 does not contain a filler. In wafer-to-wafer bonding, the distance between chips is shorter than in bonding via bumps, and the effect on reliability due to thermal expansion of the resin is small. Therefore, the amount of filler that suppresses thermal expansion is less than that of the resin 85. (Or the filler may be omitted).

複数のチップ１１のそれぞれの半導体集積回路（メモリ素子も含む）は、配線層１３、接合金属２１、貫通電極１８、裏面電極１９、バンプ３１、再配線層４１、およびバンプ３２を介して、実装基板５１の配線層と電気的に接続されている。そして、実装基板５１の配線層は、外部端子５２を介して、外部回路と接続される。   Each of the semiconductor integrated circuits (including memory elements) of the plurality of chips 11 is mounted via the wiring layer 13, the bonding metal 21, the through electrode 18, the back electrode 19, the bump 31, the rewiring layer 41, and the bump 32. The wiring layer of the substrate 51 is electrically connected. The wiring layer of the mounting substrate 51 is connected to an external circuit via the external terminal 52.

複数のチップ１１は、メモリチップであり、図１０に示すように、共通のデータ入出力端子９０に対して並列接続（バス接続）される。   The plurality of chips 11 are memory chips, and are connected in parallel (bus connection) to a common data input / output terminal 90 as shown in FIG.

すなわち、貫通電極１８、接合金属２１およびバンプ３１によってチップ積層方向に形成される共通のデータバス９１に対して、複数のチップ１１のデータ入出力線が並列接続している。   That is, the data input / output lines of the plurality of chips 11 are connected in parallel to a common data bus 91 formed in the chip stacking direction by the through electrode 18, the bonding metal 21 and the bumps 31.

図１１は、図１（ａ）に示す半導体装置から、複数のチップ１１（複数の２チップ積層体１０）の積層体を抽出した模式断面図である。   FIG. 11 is a schematic cross-sectional view in which a stacked body of a plurality of chips 11 (a plurality of two-chip stacked bodies 10) is extracted from the semiconductor device illustrated in FIG.

図１１に示すように、互いの回路面１２ａどうしを対向させて積層された２つのチップ１１の回路面間ピッチをａ、互いの裏面どうしを対向させて積層された２つのチップ１１の回路面間ピッチをｂとすると、ａ＜ｂであり、また、ピッチａとピッチｂが複数チップの積層方向に交互に周期的に繰り返されている。   As shown in FIG. 11, the pitch between the circuit surfaces of the two chips 11 stacked with the circuit surfaces 12a facing each other is a, and the circuit surface of the two chips 11 stacked with the back surfaces facing each other. When the inter-pitch is b, a <b, and the pitch a and the pitch b are periodically repeated alternately in the stacking direction of the plurality of chips.

次に、図４〜図９を参照して、２チップ積層体１０の製造方法について説明する。図４〜図９に示す工程はウェーハ状態で進められ、図４〜図９にはウェーハＷ１、Ｗ２の一部断面を示している。   Next, a method for manufacturing the two-chip laminate 10 will be described with reference to FIGS. The processes shown in FIGS. 4 to 9 are performed in a wafer state, and FIGS. 4 to 9 show partial cross sections of the wafers W1 and W2.

まず、ウェーハプロセスで、シリコン基板１２上に、前述した要素を形成する。そして、２枚のウェーハＷ１、Ｗ２を回路面１２ａ側を対向させて貼り合わせる。   First, the above-described elements are formed on the silicon substrate 12 by a wafer process. Then, the two wafers W1 and W2 are bonded together with the circuit surface 12a facing each other.

図４には、貼り合わせ前の第１ウェーハＷ１と第２ウェーハＷ２を示す。第１ウェーハＷ１と第２ウェーハＷ２は、構造は同じで、貼り合わせ面を挟んで各要素が鏡像対称になっている。   FIG. 4 shows the first wafer W1 and the second wafer W2 before bonding. The first wafer W1 and the second wafer W2 have the same structure, and each element is mirror-image symmetric across the bonding surface.

第１ウェーハＷ１と第２ウェーハＷ２は、互いの対応する接合金属２１の位置を合わせて、図５に示すように貼り合わされる。加圧及び加熱下で２枚のウェーハＷ１、Ｗ２は貼り合わされ、接合金属２１どうしが接合されるとともに、樹脂層１５どうしが接着（ウェーハボンディング）される。   The first wafer W1 and the second wafer W2 are bonded together as shown in FIG. The two wafers W1 and W2 are bonded together under pressure and heat, the bonding metal 21 is bonded to each other, and the resin layer 15 is bonded (wafer bonding).

ウェーハボンディング後、図６に示すように、第１ウェーハＷ１のシリコン基板１２を裏面１２ｂ側から研削して薄化する。第１ウェーハＷ１のシリコン基板１２が薄くなっても、第２ウェーハＷ２のシリコン基板１２が支持体となる。あるいは、第１ウェーハＷ１のシリコン基板１２を支持体にして、先に第２ウェーハＷ２のシリコン基板１２を研削して薄化してもよい。   After the wafer bonding, as shown in FIG. 6, the silicon substrate 12 of the first wafer W1 is ground and thinned from the back surface 12b side. Even if the silicon substrate 12 of the first wafer W1 becomes thin, the silicon substrate 12 of the second wafer W2 becomes a support. Alternatively, the silicon substrate 12 of the first wafer W1 may be used as a support, and the silicon substrate 12 of the second wafer W2 may be ground and thinned first.

研削前のシリコン基板１２は例えば７００μｍ以上であり、研削により、シリコン基板１２は、貫通電極を形成する場合は例えば３０〜５０μｍ程度に、貫通電極を形成しない場合は例えば１００〜５００μｍ程度に薄化される。   The silicon substrate 12 before grinding is, for example, 700 μm or more. By grinding, the silicon substrate 12 is thinned to, for example, about 30 to 50 μm when the through electrode is formed, and is thinned to, for example, about 100 to 500 μm when the through electrode is not formed. Is done.

第１ウェーハＷ１のシリコン基板１２を薄化した後、図６に示すように、シリコン基板１２を貫通して第１ウェーハＷ１の配線層１３に達するビア１６を形成する。例えば、ＲＩＥ（Reactive Ion Etching）などのエッチングによりビア１６が形成される。   After the silicon substrate 12 of the first wafer W1 is thinned, as shown in FIG. 6, vias 16 that penetrate the silicon substrate 12 and reach the wiring layer 13 of the first wafer W1 are formed. For example, the via 16 is formed by etching such as RIE (Reactive Ion Etching).

図７に示すように、ビア１６の内壁、およびビア１６周囲のシリコン基板１２の裏面１２ｂには絶縁膜１７が形成される。そして、絶縁膜１７を介してビア１６内に貫通電極１８が埋め込まれる。また、シリコン基板１２の裏面１２ｂには貫通電極１８と接続した裏面電極１９が形成される。裏面電極１９とシリコン基板１２の裏面１２ｂとの間にも絶縁膜１７が介在される。   As shown in FIG. 7, an insulating film 17 is formed on the inner wall of the via 16 and the back surface 12 b of the silicon substrate 12 around the via 16. Then, the through electrode 18 is embedded in the via 16 via the insulating film 17. A back electrode 19 connected to the through electrode 18 is formed on the back surface 12 b of the silicon substrate 12. An insulating film 17 is also interposed between the back electrode 19 and the back surface 12 b of the silicon substrate 12.

次に、図８に示すように、貫通電極１８が形成された第１ウェーハＷ１のシリコン基板１２の裏面１２ｂ側に支持体１００を貼り付ける。図８において、図７と上下を逆にして第１ウェーハＷ１及び第２ウェーハＷ２を示している。   Next, as shown in FIG. 8, the support body 100 is affixed on the back surface 12b side of the silicon substrate 12 of the 1st wafer W1 in which the penetration electrode 18 was formed. In FIG. 8, the first wafer W1 and the second wafer W2 are shown upside down from FIG.

支持体１００は、例えばガラス基板などの剛体である。支持体１００は接着層１０１を介して第１ウェーハＷ１のシリコン基板１２に貼り付けられる。   The support body 100 is a rigid body such as a glass substrate. The support 100 is attached to the silicon substrate 12 of the first wafer W1 through the adhesive layer 101.

支持体１００によって第１ウェーハＷ１および第２ウェーハＷ２が支持された状態で、第２ウェーハＷ２のシリコン基板１２を裏面１２ｂ側から研削して薄化する。   In a state where the first wafer W1 and the second wafer W2 are supported by the support body 100, the silicon substrate 12 of the second wafer W2 is ground and thinned from the back surface 12b side.

第２ウェーハＷ２のシリコン基板１２を薄化した後、第１ウェーハＷ１に対するプロセスと同様に、シリコン基板１２を貫通して第２ウェーハＷ２の配線層１３に達するビアを形成する。   After thinning the silicon substrate 12 of the second wafer W2, vias reaching the wiring layer 13 of the second wafer W2 through the silicon substrate 12 are formed in a manner similar to the process for the first wafer W1.

そして、図９に示すように、第２ウェーハＷ２のビア１６の内壁、およびビア１６周囲のシリコン基板１２の裏面１２ｂに絶縁膜１７が形成される。そして、絶縁膜１７を介してビア１６内に貫通電極１８が埋め込まれる。また、シリコン基板１２の裏面１２ｂには貫通電極１８と接続した裏面電極１９が形成される。裏面電極１９とシリコン基板１２の裏面１２ｂとの間にも絶縁膜１７が介在される。また、必要に応じて、裏面電極１９上にバンプ３１が形成される。   Then, as shown in FIG. 9, an insulating film 17 is formed on the inner wall of the via 16 of the second wafer W <b> 2 and the back surface 12 b of the silicon substrate 12 around the via 16. Then, the through electrode 18 is embedded in the via 16 via the insulating film 17. A back electrode 19 connected to the through electrode 18 is formed on the back surface 12 b of the silicon substrate 12. An insulating film 17 is also interposed between the back electrode 19 and the back surface 12 b of the silicon substrate 12. Further, bumps 31 are formed on the back electrode 19 as necessary.

その後、第１ウェーハＷ１および第２ウェーハＷ２の接合体をダイシングし、支持体１００を除去（剥離）することで、個片化された２チップ積層体１０が得られる。   Thereafter, the joined body of the first wafer W1 and the second wafer W2 is diced, and the support body 100 is removed (peeled), whereby the separated two-chip laminated body 10 is obtained.

例えば、支持体１００がダイシングテープに貼り付けられた状態で、第２ウェーハＷ２および第１ウェーハＷ１がダイシングされる。あるいは、支持体１００を剥離してから第１ウェーハＷ１および第２ウェーハＷ２をダイシングしてもよい。   For example, the second wafer W <b> 2 and the first wafer W <b> 1 are diced in a state where the support body 100 is attached to a dicing tape. Alternatively, the first wafer W1 and the second wafer W2 may be diced after the support 100 is peeled off.

実施形態の２チップ積層体１０は、個片化した２チップのチップトゥチップボンディングではなく、ウェーハトゥウェーハボンディングの後のダイシングにより得られる。したがって、２チップ積層体１０は、連続した側面を有する直方体形状に形成される。   The two-chip laminated body 10 of the embodiment can be obtained by dicing after wafer-to-wafer bonding, not by chip-to-chip bonding of two separated chips. Therefore, the two-chip laminated body 10 is formed in a rectangular parallelepiped shape having continuous side surfaces.

個片化された複数の２チップ積層体１０は、図１（ａ）に示すように、実装基板５１上に積層され、複数の２チップ積層体１０どうしの間には樹脂８５が充填される。あるいは、複数の２チップ積層体１０を、樹脂フィルムを介して貼り合わせて積層してもよい。   As shown in FIG. 1A, the plurality of separated two-chip laminates 10 are laminated on a mounting substrate 51, and a resin 85 is filled between the plurality of two-chip laminates 10. . Alternatively, a plurality of two-chip laminates 10 may be bonded and laminated via a resin film.

また、図２（ａ）、図２（ｂ）、図３（ａ）に示すように、２チップ積層体１０に対して、１つのチップ１１がバンプ３１を介して積層された構造でもよい。   Further, as shown in FIGS. 2A, 2 </ b> B, and 3 </ b> A, a structure in which one chip 11 is stacked with bumps 31 on the two-chip stacked body 10 may be used.

ＴＳＶ（Through-Silicon Via）構造において、基板を薄くすれば貫通電極の表面積が小さくなり、絶縁膜を挟んで対向する貫通電極と基板との間の寄生容量を低減できる。しかしながら、基板が薄くなると、チップどうしのボンディング、チップと実装基板とのボンディングなどの組み立てプロセスにおいてハンドリングが困難になる問題が生じる。   In a TSV (Through-Silicon Via) structure, if the substrate is thinned, the surface area of the through electrode is reduced, and the parasitic capacitance between the through electrode and the substrate facing each other with the insulating film interposed therebetween can be reduced. However, when the substrate becomes thinner, there arises a problem that handling becomes difficult in an assembly process such as bonding between chips and bonding between a chip and a mounting substrate.

そこで、以上説明した実施形態によれば、２枚のウェーハＷ１、Ｗ２を回路面１２ａ側を対向させてウェーハトゥウェーハボンディングした後、一方のウェーハＷ２のシリコン基板１２を支持体として、他方のウェーハＷ１のシリコン基板１２を薄化して貫通電極１８を形成する。その後、一方のウェーハＷ１のシリコン基板１２側に支持体（剛体）１００を貼り付けた後、他方のウェーハＷ２のシリコン基板１２を薄化して、ウェーハＷ２にも貫通電極１８を形成する。   Therefore, according to the embodiment described above, after wafer-to-wafer bonding of the two wafers W1 and W2 with the circuit surface 12a facing each other, the silicon wafer 12 of one wafer W2 is used as a support, and the other wafer is used. The through silicon via 12 is formed by thinning the silicon substrate 12 of W1. Thereafter, a support (rigid body) 100 is attached to the silicon substrate 12 side of one wafer W1, and then the silicon substrate 12 of the other wafer W2 is thinned to form the through electrode 18 also in the wafer W2.

そのため、ハンドリングの困難性をきたすことなく、２チップ積層体１０のそれぞれの基板１２を薄化した上でＴＳＶ構造を形成することができる。参照例として、チップトゥチップで２チップを積層した構造に比べて、実施形態の２チップ積層体１０によれば基板１２の厚さを約１／２にすることができる。   Therefore, the TSV structure can be formed after thinning the respective substrates 12 of the two-chip laminate 10 without causing difficulty in handling. As a reference example, the thickness of the substrate 12 can be reduced to about ½ according to the two-chip stacked body 10 of the embodiment as compared to a structure in which two chips are stacked by chip-to-chip.

したがって、絶縁膜１７を挟んでシリコン基板１２に対向する貫通電極１８の表面積を参照例に比べて約１／２にすることが可能となり、貫通電極１８と基板１２間の寄生容量を約１／２に低減することができる。   Accordingly, the surface area of the through electrode 18 facing the silicon substrate 12 with the insulating film 17 interposed therebetween can be reduced to about ½ compared to the reference example, and the parasitic capacitance between the through electrode 18 and the substrate 12 can be reduced to about 1 /. It can be reduced to 2.

特に、記憶容量の大容量化にともないチップ１１の積層数が増大すると、ＴＳＶの数も増え、その寄生容量の影響も大きくなる傾向にあるが、実施形態によれば、基板１２の薄化によりＴＳＶの寄生容量を低減することで、結果として消費電力の低減を図れる。   In particular, as the number of stacked chips 11 increases as the storage capacity increases, the number of TSVs also increases and the influence of parasitic capacitance tends to increase. However, according to the embodiment, the substrate 12 is thinned. By reducing the parasitic capacitance of TSV, the power consumption can be reduced as a result.

また、２チップ積層体１０は、接合面を挟んで断面構造が鏡像対称にある同じチップ１１どうしがボンディングされた構造であるため、それぞれのチップ１１に発生する反りが相殺されて、２チップ積層体１０としては反りの小さいものが得られる。   Further, the two-chip laminated body 10 has a structure in which the same chips 11 whose cross-sectional structures are mirror-image symmetrical are bonded to each other with the bonding surface interposed therebetween. A body 10 having a small warp is obtained.

図１（ａ）には、例えば、４組の２チップ積層体１０の積層構造を例示したが、２組または３組の２チップ積層体１０の積層構造でもよく、また、５組以上の２チップ積層体１０を積層させてもよい。   In FIG. 1A, for example, a laminated structure of four sets of two-chip laminated bodies 10 is illustrated, but a laminated structure of two sets or three sets of two-chip laminated bodies 10 may be used, and five or more sets of 2 The chip stack 10 may be stacked.

また、図２（ａ）に示すように、再配線層４１を上に向けて複数チップ１１の積層体を実装基板５１にボンディングし、最上層の再配線層４１と、実装基板５１とをワイヤ６１によってボンディングしてもよい。   Further, as shown in FIG. 2A, the stacked body of the plurality of chips 11 is bonded to the mounting substrate 51 with the rewiring layer 41 facing upward, and the uppermost rewiring layer 41 and the mounting substrate 51 are connected to the wire. 61 may be used for bonding.

また、図２（ｂ）に示すように、実装基板５１を用いずに、複数のチップ１１の積層体を再配線層４１を介して直接外部端子５２に接続させてもよい。   In addition, as illustrated in FIG. 2B, the stacked body of the plurality of chips 11 may be directly connected to the external terminal 52 through the rewiring layer 41 without using the mounting substrate 51.

また、図３（ａ）に示すように、最下層のチップ１１の下の再配線層４１の下にロジックチップ７１を搭載してもよい。ロジックチップ７１はバンプ（例えば、はんだボール、金属バンプ）７２を介して再配線層４１に接合している。ロジックチップ７１は、再配線層４１を介して、例えば最下層のチップ１１（貫通電極、配線層）に電気的に接続している。   Further, as shown in FIG. 3A, a logic chip 71 may be mounted under the redistribution layer 41 under the lowermost chip 11. The logic chip 71 is bonded to the rewiring layer 41 via bumps (for example, solder balls, metal bumps) 72. The logic chip 71 is electrically connected to, for example, the lowermost chip 11 (through electrode, wiring layer) via the rewiring layer 41.

ロジックチップ７１は、各メモリチップ１１を制御するＩＦ（interface）／コントローラチップである。   The logic chip 71 is an IF (interface) / controller chip that controls each memory chip 11.

また、図３（ｂ）に示すように、貫通電極１８がないチップ１１と、貫通電極１８を持つチップ１１とが接合金属２１及び樹脂層１５を介して接合された２チップ積層体１０’が含まれていてもよい。   Further, as shown in FIG. 3B, a two-chip laminated body 10 ′ in which the chip 11 without the through electrode 18 and the chip 11 with the through electrode 18 are bonded via the bonding metal 21 and the resin layer 15 is provided. It may be included.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

１０…２チップ積層体、１１…チップ、１２…シリコン基板、１２ａ…回路面、１２ｂ…裏面、１３…配線層、１５…樹脂層、１６…ビア、１７…絶縁膜、１８…貫通電極、１９…裏面電極、２１…接合金属、３１…バンプ、５１…実装基板、７１…ロジックチップ、８０…樹脂、１００…支持体   DESCRIPTION OF SYMBOLS 10 ... Two-chip laminated body, 11 ... Chip, 12 ... Silicon substrate, 12a ... Circuit surface, 12b ... Back surface, 13 ... Wiring layer, 15 ... Resin layer, 16 ... Via, 17 ... Insulating film, 18 ... Through electrode, 19 ... Back electrode, 21 ... Junction metal, 31 ... Bump, 51 ... Mounting substrate, 71 ... Logic chip, 80 ... Resin, 100 ... Support

Claims (8)

第１回路面と、前記第１回路面の反対側の第１裏面とを有する第１半導体層と、前記第１回路面に設けられた第１配線層と、前記第１裏面に設けられた第１裏面電極と、前記第１半導体層を貫通して設けられ、前記第１配線層と前記第１裏面電極に接続された第１貫通電極と、前記第１配線層の前記第１回路面とは反対の面に向かって前記第１配線層に接続され銅を主成分とする第１接合金属を有する第１チップと、
前記第１チップの前記第１配線層側に積層された第２チップであって、前記第１配線層に対向した第２回路面と、前記第２回路面の反対側の第２裏面とを有する第２半導体層と、前記第２回路面に設けられ、前記第１チップの前記第１配線層と接続された第２配線層と、前記第２裏面に設けられた第２裏面電極と、前記第２半導体層を貫通して設けられ、前記第２配線層と前記第２裏面電極に接続された第２貫通電極と、前記第２配線層の前記第２回路面とは反対の面に向かって前記第２配線層に接続された銅を主成分とし前記第１接合金属と接合されている第２接合金属と、を有する第２チップと、
前記第２チップの前記第２裏面側に積層された第３チップであって、第３回路面と、前記第３回路面の反対側に位置し、前記第２チップに対向した第３裏面とを有する第３半導体層と、前記第３回路面に設けられた第３配線層と、前記第３裏面に設けられた第３裏面電極と、前記第３半導体層を貫通して設けられ、前記第３配線層と前記第３裏面電極に接続されるとともに、前記第２チップの前記第２貫通電極と接続された第３貫通電極と、前記第３配線層の前記第３回路面とは反対の面に向かって前記第３配線層に接続され銅を主成分とする第３接合金属を有する第３チップと、
前記第２裏面電極と前記第３裏面電極の間に設けられ前記第２裏面電極と前記第３裏面電極とに接続された第１のはんだと、
を備え、前記第１チップと前記第２チップとの距離は、前記第２チップと前記第３チップとの距離よりも短い半導体装置。 A first semiconductor layer having a first circuit surface and a first back surface opposite to the first circuit surface; a first wiring layer provided on the first circuit surface; and provided on the first back surface. A first back electrode, a first through electrode provided through the first semiconductor layer and connected to the first wiring layer and the first back electrode; and the first circuit surface of the first wiring layer. A first chip having a first bonding metal composed mainly of copper and connected to the first wiring layer toward the opposite surface;
A second chip stacked on the first wiring layer side of the first chip, the second circuit surface facing the first wiring layer, and a second back surface opposite to the second circuit surface. A second semiconductor layer having a second wiring layer provided on the second circuit surface and connected to the first wiring layer of the first chip; a second back electrode provided on the second back surface; A second through electrode provided through the second semiconductor layer and connected to the second wiring layer and the second back surface electrode; and a surface opposite to the second circuit surface of the second wiring layer. A second chip having a second bonding metal mainly composed of copper connected to the second wiring layer and bonded to the first bonding metal;
A third chip stacked on the second back surface side of the second chip, the third circuit surface, and a third back surface located on the opposite side of the third circuit surface and facing the second chip; A third semiconductor layer comprising: a third wiring layer provided on the third circuit surface; a third back electrode provided on the third back surface; provided through the third semiconductor layer; A third through electrode connected to the third wiring layer and the third back electrode and connected to the second through electrode of the second chip is opposite to the third circuit surface of the third wiring layer. A third chip having a third bonding metal mainly composed of copper and connected to the third wiring layer toward the surface of
A first solder provided between the second back electrode and the third back electrode and connected to the second back electrode and the third back electrode;
And a distance between the first chip and the second chip is shorter than a distance between the second chip and the third chip. 前記第３チップの前記第３配線層側に積層された第４チップであって、前記第３配線層に対向した第４回路面と、前記第４回路面の反対側の第４裏面とを有する第４半導体層と、前記第４回路面に設けられ、前記第３チップの前記第３配線層と接続された第４配線層と、前記第４裏面に設けられた第４裏面電極と、前記第４半導体層を貫通して設けられ、前記第４配線層と前記第４裏面電極に接続された第４貫通電極と、前記第４配線層の前記第４回路面とは反対の面に向かって前記第４配線層に接続された銅を主成分とし前記第３接合金属と接合されている第４接合金属と、を有する第４チップと、
前記第４チップの前記第４裏面側に積層された第５チップであって、第５回路面と、前記第５回路面の反対側に位置し、前記第４チップに対向した第５裏面とを有する第５半導体層と、前記第５回路面に設けられた第５配線層と、前記第５裏面に設けられた第５裏面電極と、前記第５半導体層を貫通して設けられ、前記第５配線層と前記第５裏面電極に接続されるとともに、前記第４チップの前記第４貫通電極と接続された第５貫通電極と、前記第５配線層の前記第５回路面とは反対の面に向かって前記第５配線層に接続され銅を主成分とする第５接合金属を有する第５チップと、
前記第４裏面電極と前記第５裏面電極の間に設けられ前記第４裏面電極と前記第５裏面電極とに接続された第２のはんだと、
をさらに備え、前記第３チップと前記第４チップとの距離は、前記第４チップと前記第５チップとの距離よりも短く、前記第２チップと前記第３チップとの距離よりも短い請求項１に記載の半導体装置。 A fourth chip stacked on the third wiring layer side of the third chip, wherein a fourth circuit surface facing the third wiring layer and a fourth back surface opposite to the fourth circuit surface A fourth semiconductor layer, a fourth wiring layer provided on the fourth circuit surface and connected to the third wiring layer of the third chip, a fourth back electrode provided on the fourth back surface, A fourth penetrating electrode provided through the fourth semiconductor layer and connected to the fourth wiring layer and the fourth back electrode; and a surface opposite to the fourth circuit surface of the fourth wiring layer. A fourth chip having a fourth bonding metal mainly composed of copper connected to the fourth wiring layer and bonded to the third bonding metal;
A fifth chip stacked on the fourth back surface side of the fourth chip, the fifth circuit surface, and a fifth back surface located on the opposite side of the fifth circuit surface and facing the fourth chip; A fifth semiconductor layer having a fifth wiring layer provided on the fifth circuit surface, a fifth back electrode provided on the fifth back surface, and penetrating the fifth semiconductor layer, The fifth through electrode connected to the fifth wiring layer and the fifth back electrode and connected to the fourth through electrode of the fourth chip is opposite to the fifth circuit surface of the fifth wiring layer. A fifth chip having a fifth bonding metal mainly composed of copper and connected to the fifth wiring layer toward the surface of
A second solder provided between the fourth back electrode and the fifth back electrode and connected to the fourth back electrode and the fifth back electrode;
The distance between the third chip and the fourth chip is shorter than the distance between the fourth chip and the fifth chip, and shorter than the distance between the second chip and the third chip. Item 14. The semiconductor device according to Item 1. 前記第１チップの前記第１裏面側に設けられ、前記第１貫通電極に接続され、前記第１チップ、前記第２チップおよび前記第３チップを制御するロジックチップをさらに備えた請求項１または２に記載の半導体装置。   The logic chip which is provided in the 1st back side of the 1st chip, is connected to the 1st penetration electrode, and controls the 1st chip, the 2nd chip, and the 3rd chip. 2. The semiconductor device according to 2. 前記第１チップと前記第２チップとの積層体は、連続した側面を有する直方体形状であり、前記第３チップと前記第４チップとの積層体は、連続した側面を有する直方体形状である請求項２に記載の半導体装置。   The stacked body of the first chip and the second chip has a rectangular parallelepiped shape having continuous side surfaces, and the stacked body of the third chip and the fourth chip has a rectangular parallelepiped shape having continuous side surfaces. Item 3. The semiconductor device according to Item 2. 前記第２チップと前記第３チップとの間に充填された第１の樹脂と、前記第４チップと前記第５チップとの間に充填された第２の樹脂と、をさらに備え、
前記第１チップは、前記第１配線層の前記第１回路面とは反対側の面に設けられた第１の樹脂層をさらに備え、
前記第１接合金属は、前記第１の樹脂層を貫通して設けられ、
前記第２チップは、前記第２配線層の前記第２回路面とは反対側の面に設けられた第２の樹脂層をさらに備え、
前記第２接合金属は、前記第２の樹脂層を貫通して設けられ、
前記第３チップは、前記第３配線層の前記第３回路面とは反対側の面に設けられた第３の樹脂層をさらに備え、
前記第３接合金属は、前記第３の樹脂層を貫通して設けられ、
前記第４チップは、前記第４配線層の前記第４回路面とは反対側の面に設けられた第４の樹脂層をさらに備え、
前記第４接合金属は、前記第４の樹脂層を貫通して設けられ、
前記第５チップは、前記第５配線層の前記第５回路面とは反対側の面に設けられた第５の樹脂層をさらに備え、
前記第５接合金属は、前記第５の樹脂層を貫通して設けられ、
前記第１乃至第５の樹脂層のフィラー含有量は、前記第１または第２の樹脂のフィラー含有量よりも少ない請求項２に記載の半導体装置。 A first resin filled between the second chip and the third chip; and a second resin filled between the fourth chip and the fifth chip;
The first chip further includes a first resin layer provided on a surface opposite to the first circuit surface of the first wiring layer,
The first bonding metal is provided through the first resin layer,
The second chip further includes a second resin layer provided on a surface opposite to the second circuit surface of the second wiring layer,
The second bonding metal is provided through the second resin layer,
The third chip further includes a third resin layer provided on a surface of the third wiring layer opposite to the third circuit surface,
The third bonding metal is provided through the third resin layer,
The fourth chip further includes a fourth resin layer provided on a surface opposite to the fourth circuit surface of the fourth wiring layer,
The fourth bonding metal is provided through the fourth resin layer,
The fifth chip further includes a fifth resin layer provided on a surface opposite to the fifth circuit surface of the fifth wiring layer,
The fifth bonding metal is provided through the fifth resin layer,
The semiconductor device according to claim 2, wherein a filler content of the first to fifth resin layers is less than a filler content of the first or second resin. 前記第１チップの前記第１裏面に設けられた再配線層と、
前記再配線層を介して前記第１チップの第１配線層と接続された実装基板と、をさらに備え
前記再配線層はバンプを介して前記実装基板に接続されている請求項１〜５のいずれか１つに記載の半導体装置。 A rewiring layer provided on the first back surface of the first chip;
The mounting substrate connected to the first wiring layer of the first chip via the rewiring layer, further comprising: the rewiring layer connected to the mounting substrate via a bump. The semiconductor device according to any one of the above. 前記実装基板のバンプ形成面と反対側の面に、前記第１チップと対向する位置よりも外側に設けられている外部端子を、さらに有する請求項６に記載の半導体装置。   The semiconductor device according to claim 6, further comprising an external terminal provided on a surface opposite to the bump forming surface of the mounting substrate, on an outer side than a position facing the first chip. 第１回路面と前記第１回路面の反対側の第１裏面とを有する第１基板と、前記第１回路面に設けられた第１配線層と、前記第１配線層上に設けられ、前記第１配線層と接続された銅を主成分とする第１接合金属と、を有する第１ウェーハの前記第１回路面と、
第２回路面と前記第２回路面の反対側の第２裏面とを有する第２基板と、前記第２回路面に設けられた第２配線層と、前記第２配線層上に設けられ、前記第２配線層と接続された銅を主成分とする第２接合金属と、を有する第２ウェーハの前記第２回路面と、
を対向させ、前記第１接合金属と前記第２接合金属どうしを加圧及び加熱下で接合させて、前記第１ウェーハと前記第２ウェーハとを貼り合わせ、
前記第１ウェーハと前記第２ウェーハとが貼り合わされた状態で、前記第１基板を前記第１裏面側から研削し、
前記研削により薄化された前記第１基板に、前記第１基板を貫通して前記第１配線層に達する第１貫通電極を形成し、
前記第１裏面に前記第１貫通電極と接続した第１裏面電極を形成し、
前記第１裏面側に支持体を貼り付けた状態で、前記第２基板を前記第２裏面側から研削し、
前記研削により薄化された前記第２基板に、前記第２基板を貫通して前記第２配線層に達する第２貫通電極を形成し、
前記第２裏面に前記第２貫通電極と接続した第２裏面電極を形成し、
前記第２裏面電極にはんだを形成し、
前記第２裏面電極を形成した後、前記支持体を除去、および前記第１ウェーハと前記第２ウェーハとの接合体を複数のチップに個片化し、
前記個片化された複数のチップのうち第１のチップの前記第１ウェーハの前記第１裏面と前記個片化された複数のチップのうち第２のチップの前記第２ウェーハの前記第２裏面が対向するように前記第１チップを前記第２チップへ前記はんだを介して積層する
半導体装置の製造方法であって、
前記第１のチップの前記第１基板と前記第１のチップの前記第２基板との距離は、前記第１のチップの前記第２基板と前記第２のチップの前記第１基板との距離よりも短い半導体装置の製造方法。 A first substrate having a first circuit surface and a first back surface opposite to the first circuit surface; a first wiring layer provided on the first circuit surface; and a first wiring layer provided on the first wiring layer; The first circuit surface of the first wafer having a first bonding metal mainly composed of copper connected to the first wiring layer;
A second substrate having a second circuit surface and a second back surface opposite to the second circuit surface; a second wiring layer provided on the second circuit surface; and provided on the second wiring layer; The second circuit surface of the second wafer having a second bonding metal mainly composed of copper connected to the second wiring layer;
And bonding the first and second bonding metals together under pressure and heating, and bonding the first and second wafers together,
In a state where the first wafer and the second wafer are bonded together, the first substrate is ground from the first back surface side,
Forming a first through electrode penetrating the first substrate and reaching the first wiring layer on the first substrate thinned by the grinding;
Forming a first back electrode connected to the first through electrode on the first back surface;
With the support attached to the first back side, the second substrate is ground from the second back side,
Forming a second through electrode that penetrates the second substrate and reaches the second wiring layer on the second substrate thinned by the grinding;
Forming a second back electrode connected to the second through electrode on the second back surface;
Forming solder on the second back electrode;
After forming the second back electrode, the support is removed, and the joined body of the first wafer and the second wafer is separated into a plurality of chips,
Of the plurality of singulated chips, the first back surface of the first wafer of the first chip and the second of the second wafer of the second chip among the plurality of singulated chips. A method of manufacturing a semiconductor device, wherein the first chip is stacked on the second chip via the solder so that the back surfaces thereof face each other.
The distance between the first substrate of the first chip and the second substrate of the first chip is the distance between the second substrate of the first chip and the first substrate of the second chip. A method of manufacturing a semiconductor device shorter than
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