JP2018026437A - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
- Publication number
- JP2018026437A JP2018026437A JP2016156803A JP2016156803A JP2018026437A JP 2018026437 A JP2018026437 A JP 2018026437A JP 2016156803 A JP2016156803 A JP 2016156803A JP 2016156803 A JP2016156803 A JP 2016156803A JP 2018026437 A JP2018026437 A JP 2018026437A
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- Prior art keywords
- layer
- insulating film
- wiring
- insulating
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title claims description 45
- 239000011347 resin Substances 0.000 claims abstract description 119
- 229920005989 resin Polymers 0.000 claims abstract description 119
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims description 101
- 229910000679 solder Inorganic materials 0.000 claims description 97
- 238000000034 method Methods 0.000 claims description 76
- 238000010030 laminating Methods 0.000 claims description 7
- 238000009413 insulation Methods 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 648
- 239000011888 foil Substances 0.000 description 57
- 239000000758 substrate Substances 0.000 description 54
- 229910052751 metal Inorganic materials 0.000 description 46
- 239000002184 metal Substances 0.000 description 46
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 45
- 239000010949 copper Substances 0.000 description 40
- 230000004048 modification Effects 0.000 description 36
- 238000012986 modification Methods 0.000 description 36
- 229910052802 copper Inorganic materials 0.000 description 33
- 230000008569 process Effects 0.000 description 33
- 230000004888 barrier function Effects 0.000 description 31
- 239000000463 material Substances 0.000 description 31
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 27
- 238000005530 etching Methods 0.000 description 22
- 238000005520 cutting process Methods 0.000 description 17
- 239000000945 filler Substances 0.000 description 14
- 238000007789 sealing Methods 0.000 description 14
- 239000011889 copper foil Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 13
- 239000004593 Epoxy Substances 0.000 description 11
- 238000007772 electroless plating Methods 0.000 description 11
- 239000000654 additive Substances 0.000 description 9
- 229910052759 nickel Inorganic materials 0.000 description 9
- 229920001187 thermosetting polymer Polymers 0.000 description 9
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 238000003825 pressing Methods 0.000 description 7
- 239000012790 adhesive layer Substances 0.000 description 6
- 239000007864 aqueous solution Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 229910052718 tin Inorganic materials 0.000 description 6
- 230000003064 anti-oxidating effect Effects 0.000 description 5
- 239000004744 fabric Substances 0.000 description 5
- 238000003672 processing method Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 4
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 239000005011 phenolic resin Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000003963 antioxidant agent Substances 0.000 description 3
- 230000003078 antioxidant effect Effects 0.000 description 3
- -1 azole compound Chemical class 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 2
- 229920006231 aramid fiber Polymers 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 2
- 150000003949 imides Chemical class 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000004745 nonwoven fabric Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000002759 woven fabric Substances 0.000 description 2
- KAESVJOAVNADME-UHFFFAOYSA-N 1H-pyrrole Natural products C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 description 1
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229920000049 Carbon (fiber) Polymers 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 239000004917 carbon fiber Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 235000011837 pasties Nutrition 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002335 surface treatment layer Substances 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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Abstract
【解決手段】本配線基板は、第1絶縁膜の一方の面に第2絶縁膜が積層され、前記第1絶縁膜の他方の面が外部に露出する絶縁層と、前記第1絶縁膜に埋め込まれ、所定面が前記第1絶縁膜の他方の面から露出する第1配線層と、を有し、前記第1絶縁膜は樹脂のみから構成され、前記第2絶縁膜は補強部材に樹脂を含浸させた構成とされている。
【選択図】図19
Description
[第1の実施の形態に係る配線基板の構造]
まず、第1の実施の形態に係る配線基板の構造について説明する。図1は、第1の実施の形態に係る配線基板を例示する図であり、図1(a)は断面図、図1(b)は部分底面図である。
次に、第1の実施の形態に係る配線基板の製造方法について説明する。図2及び図3は、第1の実施の形態に係る配線基板の製造工程を例示する図である。本実施の形態では、支持体上に複数の配線基板となる部分を作製し支持体を除去後個片化して各配線基板とする工程の例を示すが、支持体上に1個ずつ配線基板を作製し支持体を除去する工程としてもよい。
第1の実施の形態の変形例1では、配線層10の上面が第1絶縁膜21から露出する例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例2では、配線層10の上面が第1絶縁膜21から突出する例を示す。なお、第1の実施の形態の変形例2において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第2の実施の形態では、3層構造の配線基板の例を示す。なお、第2の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
配線基板の応用例1では、第1の実施の形態及び第2の実施の形態に係る配線基板に半導体チップが搭載(フリップチップ実装)された半導体パッケージの例を示す。なお、配線基板の応用例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
配線基板の応用例2では、半導体パッケージ上に更に他の半導体パッケージが搭載された所謂POP(Package on package)構造の半導体パッケージの例を示す。なお、配線基板の応用例2において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第3の実施の形態では、微細配線を有する配線基板の例を示す。なお、第3の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
まず、第3の実施の形態に係る配線基板の構造について説明する。図15は、第3の実施の形態に係る配線基板を例示する断面図である。図15を参照するに、第3の実施の形態に係る配線基板1Fは、配線基板1(図1参照)の絶縁層20上に絶縁層410、配線層420、絶縁層430、配線層440、絶縁層450、配線層460を順次積層した構造である。なお、図15では、配線層10、絶縁層20等が図1とは上下を反転した状態で描かれている。
次に、第3の実施の形態に係る配線基板の製造方法について説明する。図16及び図17は、第3の実施の形態に係る配線基板の製造工程を例示する図である。本実施の形態では、支持体上に複数の配線基板となる部分を作製し支持体を除去後個片化して各配線基板とする工程の例を示すが、支持体上に1個ずつ配線基板を作製し支持体を除去する工程としてもよい。
配線基板の応用例3では、第3の実施の形態に係る配線基板に半導体チップが搭載(フリップチップ実装)された半導体パッケージの例を示す。なお、配線基板の応用例3において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第4の実施の形態では、配線層及び絶縁層が1層の配線基板の例を示す。なお、第4の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
まず、第4の実施の形態に係る配線基板の構造について説明する。図19は、第4の実施の形態に係る配線基板を例示する断面図であり、図19(a)は全体図、図19(b)は図19(a)のA部の部分拡大図である。図19を参照するに、第4の実施の形態に係る配線基板1Gは、配線層40並びにソルダーレジスト層50及び60を有していない点が、配線基板1(図1参照)と相違する。
次に、第4の実施の形態に係る配線基板の製造方法について説明する。図20〜図22は、第4の実施の形態に係る配線基板の製造工程を例示する図である。本実施の形態では、支持体上に複数の配線基板となる部分を作製し支持体を除去後個片化して各配線基板とする工程の例を示すが、支持体上に1個ずつ配線基板を作製し支持体を除去する工程としてもよい。
第4の実施の形態の変形例1では、配線基板1Gの製造方法の他の例を示す。なお、第4の実施の形態の変形例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第4の実施の形態の変形例2では、配線層10の一方の面と絶縁層20の一方の面との位置関係が第4の実施の形態とは異なる例を示す。なお、第4の実施の形態の変形例2において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第4の実施の形態の変形例3では、絶縁層20の他方の面に支持体(キャリア)を設けた例を示す。なお、第4の実施の形態の変形例3において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
配線基板の応用例4では、第4の実施の形態に係る配線基板に半導体チップが搭載(フリップチップ実装)された半導体パッケージの例を示す。なお、配線基板の応用例4において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
5、5A、5B、5C、5D 半導体パッケージ
10、40、80、420、440、460 配線層
10a パッド
10b 配線パターン
20、20A、70、410、430、450 絶縁層
20x、50x、60x 開口部
20y 凹部
21 第1絶縁膜
22 第2絶縁膜
23 第3絶縁膜
30 補強部材
50、60 ソルダーレジスト層
70x、410x、430x、450x ビアホール
91 粘着層
95、300、900 支持体
100、210、250 半導体チップ
110、130、220、260、280 バンプ
120 アンダーフィル樹脂
140 はんだバンプ
150、240 封止樹脂
230 はんだボール
231 銅コアボール
232 はんだ
270 チップコンデンサ
910 プリプレグ
920、920A キャリア付き金属箔
921、921A 薄箔
922 厚箔
930 バリア層
940 レジスト層
Claims (18)
- 第1絶縁膜の一方の面に第2絶縁膜が積層され、前記第1絶縁膜の他方の面が外部に露出する絶縁層と、
前記第1絶縁膜に埋め込まれ、所定面が前記第1絶縁膜の他方の面から露出する第1配線層と、を有し、
前記第1絶縁膜は樹脂のみから構成され、
前記第2絶縁膜は補強部材に樹脂を含浸させた構成とされている配線基板。 - 前記絶縁層は、前記第1配線層の前記所定面の反対面を露出する開口部を備え、
前記開口部に露出する前記所定面の反対面は、外部接続用パッドである請求項1記載の配線基板。 - 前記開口部の前記第1絶縁膜に形成された部分に、前記開口部の内壁を前記第1絶縁膜側に後退させる凹部が形成されている請求項2記載の配線基板。
- 前記第2絶縁膜の前記第1絶縁膜の一方の面と接する面の反対面に形成された配線パターン、及び前記開口部内に形成され、前記配線パターンと前記第1配線層とを接続するビア配線、を含む第2配線層を有する請求項2又は3記載の配線基板。
- 前記第1絶縁膜は、前記第1配線層の側面と、前記所定面の反対面を被覆し、
前記ビア配線は、前記第2絶縁膜及び前記第1絶縁膜を貫通し、前記所定面の反対面に接続されている請求項4記載の配線基板。 - 前記第1絶縁膜は、前記第1配線層の側面のみを被覆し、
前記ビア配線は、前記第2絶縁膜のみを貫通し、前記所定面の反対面に接続されている請求項4記載の配線基板。 - 前記所定面の反対面は、前記第1絶縁膜の一方の面から前記第2絶縁膜内に突出している請求項6記載の配線基板。
- 前記第2配線層の配線パターンを被覆するように、前記第2絶縁膜に積層された他の絶縁層と、
前記他の絶縁層に積層され、前記第2配線層の配線パターンと接続される第3配線層と、を有する請求項4乃至7の何れか一項記載の配線基板。 - 前記第1絶縁膜の他方の面に、前記第1配線層の複数のパッドの所定面を一括で露出する開口部を備えたソルダーレジスト層が積層されている請求項1乃至8の何れか一項記載の配線基板。
- 前記第1絶縁膜の他方の面は、半導体チップを搭載するチップ搭載面である請求項1乃至9の何れか一項記載の配線基板。
- 前記第1絶縁膜の他方の面上に、他の絶縁層と配線層が積層されている請求項1乃至8の何れか一項記載の配線基板。
- 支持体の上面に第1配線層を形成する工程と、
前記支持体の上面に、前記第1配線層を被覆するように、樹脂のみから構成された半硬化状態の第1絶縁膜を形成する工程と、
前記第1絶縁膜の一方の面上に、補強部材に樹脂を含浸させた構成とされた半硬化状態の第2絶縁膜を積層する工程と、
前記第1絶縁膜及び前記第2絶縁膜を硬化させ、前記第1絶縁膜上に前記第2絶縁膜が積層された絶縁層を作製する工程と、を有する配線基板の製造方法。 - 支持体の上面に第1配線層を形成する工程と、
樹脂のみから構成された半硬化状態の第1絶縁膜、及び前記第1絶縁膜の一方の面上に積層された、補強部材に樹脂を含浸させた構成とされた半硬化状態の第2絶縁膜、を有する絶縁層を準備する工程と、
前記第1絶縁膜を前記支持体側に向けて、前記支持体の上面に前記第1配線層を被覆するように前記絶縁層を貼り付け、前記絶縁層を硬化させる工程と、を有する配線基板の製造方法。 - 前記絶縁層を貫通して前記第1配線層の上面を露出する開口部を形成する工程を有する請求項12又は13記載の配線基板の製造方法。
- 前記開口部の前記第1絶縁膜に形成された部分に、前記開口部の内壁を前記第1絶縁膜側に後退させる凹部を形成する工程を有する請求項14記載の配線基板の製造方法。
- 前記第2絶縁膜上に形成された配線パターン、及び前記開口部内に形成され、前記配線パターンと前記第1配線層とを接続するビア配線、を含む第2配線層を形成する工程を有する請求項14又は15記載の配線基板の製造方法。
- 前記支持体を除去する工程を有する請求項12乃至16の何れか一項記載の配線基板の製造方法。
- 前記第1絶縁膜の他方の面上に、他の絶縁層と配線層を積層する工程を有する請求項17記載の配線基板の製造方法。
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JP2020047735A (ja) * | 2018-09-18 | 2020-03-26 | 新光電気工業株式会社 | 配線基板、積層型配線基板、半導体装置 |
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CN110556356A (zh) * | 2018-06-01 | 2019-12-10 | 夏普株式会社 | 功率模块 |
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JP2022030237A (ja) * | 2020-08-06 | 2022-02-18 | 新光電気工業株式会社 | 配線基板の製造方法、絶縁シート |
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