JP2017511976A - スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ - Google Patents
スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ Download PDFInfo
- Publication number
- JP2017511976A JP2017511976A JP2016553573A JP2016553573A JP2017511976A JP 2017511976 A JP2017511976 A JP 2017511976A JP 2016553573 A JP2016553573 A JP 2016553573A JP 2016553573 A JP2016553573 A JP 2016553573A JP 2017511976 A JP2017511976 A JP 2017511976A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- fet
- interposer
- terminal
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 239000011810 insulating material Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 description 8
- 230000001360 synchronised effect Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
Claims (11)
- 電力供給システムであって、
垂直にアセンブルされるスタックであって、QFNリードフレーム、対向する側にFET端子を備えた第1のチップ、平坦なインターポーザ、及び一つの側にFET端子を備えた第2のチップを順次含む、前記垂直にアセンブルされるスタック、
を含み、
前記リードフレームが、リード、及び前記スタックから離れて面する第1の表面と前記スタックに面する第2の表面とを備えたパッドを有し、パッドの前記第2の表面がポケットとして窪んだ部分を有し、前記ポケットが、前記ポケットにおいて半導体チップを取り付けるために適した深さ及びアウトラインを有し、前記パッドが、前記電力供給システムの接地された出力端子に連結され、
前記第1のチップが、窪んだ前記ポケットに取り付けられる第1のFETのソース及びゲート端子、及びパッドの窪んでいない前記第2の表面と共面である第1のFETのドレイン端子を有し、
前記インターポーザが、前記第1のチップに面する平坦な第3の表面、前記第2のチップに面する反対の平坦な第4の表面、及び前記第3及び第4の表面間の均一な第1の高さを有し、前記インターポーザの金属が、ギャップにより分離される複数のトレースにパターニングされ、前記複数のトレースが、前記第1の高さの金属、及び前記第1の高さより小さい第2の高さの金属を含み、前記ギャップ及び前記第1及び前記第2の高さ間の差を絶縁性材料が充填する、前記垂直にアセンブルされるスタック、
前記複数のトレースの第1のトレースが、前記電力供給システムの入力端子に連結され、第2のFETのドレイン端子に取り付けられる前記第4の表面を有し、
前記複数のトレースの第2のトレースが、前記電力供給システムのスイッチノード端子に連結され、前記第1のFETの前記ドレイン端子に取り付けられる前記第3の表面、及び前記第2のFETのソース端子に取り付けられる前記第4の表面を有する、
電力供給システム。 - 請求項1に記載の電力供給システムであって、更に、前記リードフレームの前記第1の表面とリードとを封止されないまま残すパッケージを含む、電力供給システム。
- 請求項2に記載の電力供給システムであって、前記FET端子とは反対の前記第2のチップの側が封止されない、電力供給システム。
- 請求項2に記載の電力供給システムであって、前記封止されない第1のリードフレーム表面が熱エネルギーを拡散するために適している、電力供給システム。
- 請求項3に記載の電力供給システムであって、前記第2のチップの前記封止されない表面が熱エネルギーを拡散するために適している、電力供給システム。
- 請求項1に記載の電力供給システムであって、前記第1及び前記第2のチップのゲートが、インターポーザ金属の第3のトレースに連結される、電力供給システム。
- 請求項6に記載の電力供給システムであって、前記第2のチップが更に前記電力供給システムのドライバ・コントローラ回路要素と統合され、前記ドライバ・コントローラ回路の端子が、インターポーザ金属の第4のトレースに連結される、電力供給システム。
- 電力供給システムを製造する方法であって、
リードと、第1及び第2の表面を備えたパッドとを有するリードフレームを提供することであって、前記第2の表面がポケットのために窪んだ部分を有し、前記ポケットが、半導体チップを取り付けるために適した深さ及びアウトラインを有すること、
一つの側に第1のFETのソース及びゲート端子、及び反対の側に第1のFETのドレイン端子を備えた第1のチップを提供すること、
前記第1のチップの前記FETのソース端子を、前記パッドの窪んだ前記第2の表面に取り付けること、
絶縁性ゾーンを備えて交互に並ぶ金属性トレースのネットワークを備えた第3及び第4の表面を有する平坦なインターポーザを提供すること、
それぞれのトレースを前記パッド及びリード及び前記第1のFETのドレイン端子に接続することにより前記リードフレームの前記第2の表面上にその第3の表面を備えた前記インターポーザを置くこと、
同じ側に、第2のFETのソース、ドレイン、及びゲート端子と、集積されたドライバ・コントローラ回路要素の端子とを有する第2のチップを提供すること、及び
前記第2のFETの前記ソース、ドレイン、及びゲート端子と、前記ドライバ・コントローラ回路要素の前記端子とをそれぞれのトレースに接続することにより、前記インターポーザの前記第4の表面上に前記第2のチップを置き、垂直にスタックされた電力供給システムを完成すること、
を含む、方法。 - 請求項8に記載の方法であって、前記インターポーザを提供する前に、
第1の高さ、第1の平面における第1の表面、及び平行な第2の平面における第2の表面を有する平坦な金属のシートを提供すること、
前記金属のシートを、ギャップにより分離される複数のトレースにパターニングすること、
或るトレースの部分を前記第1の高さより小さい第2の高さまで薄化すること、及び
絶縁性ゾーンを備えて交互に並ぶ金属性トレースのネットワークを備えた第3及び第4の表面を有する平坦なインターポーザをつくるために、前記第1及び前記第2の平面により限定される絶縁性材料で前記ギャップと前記薄化されたトレース部分とを充填すること、
を更に含む、方法。 - 請求項8に記載の方法であって、前記第2のチップを置いた後、前記垂直にスタックされたシステムをパッケージング化合物に封止し、前記リードフレームの前記第1の表面を封止されないまま残すことを更に含む、方法。
- 請求項8に記載の方法であって、前記第2のチップを置いた後、前記垂直にスタックされたシステムをパッケージング化合物に封止し、前記リードフレームの前記第1の表面と、前記FET端子とは反対の前記第2のチップの表面とを封止されないまま残すことを更に含む、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/185,502 US9136256B2 (en) | 2014-02-20 | 2014-02-20 | Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips |
US14/185,502 | 2014-02-20 | ||
PCT/US2015/016739 WO2015127159A1 (en) | 2014-02-20 | 2015-02-20 | Converter having partially thinned leadframe with stacked chips and interposer |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2017511976A true JP2017511976A (ja) | 2017-04-27 |
JP2017511976A5 JP2017511976A5 (ja) | 2018-04-05 |
JP6534677B2 JP6534677B2 (ja) | 2019-06-26 |
Family
ID=53798782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016553573A Active JP6534677B2 (ja) | 2014-02-20 | 2015-02-20 | スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ |
Country Status (5)
Country | Link |
---|---|
US (2) | US9136256B2 (ja) |
EP (1) | EP3108503B1 (ja) |
JP (1) | JP6534677B2 (ja) |
CN (1) | CN106030788B (ja) |
WO (1) | WO2015127159A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8587099B1 (en) * | 2012-05-02 | 2013-11-19 | Texas Instruments Incorporated | Leadframe having selective planishing |
US10312184B2 (en) * | 2015-11-04 | 2019-06-04 | Texas Instruments Incorporated | Semiconductor systems having premolded dual leadframes |
US20200135632A1 (en) * | 2018-10-24 | 2020-04-30 | Texas Instruments Incorporated | Die isolation on a substrate |
CN109545697B (zh) * | 2018-12-26 | 2024-06-18 | 桂林电子科技大学 | 半导体封装方法及半导体封装结构 |
US10964629B2 (en) | 2019-01-18 | 2021-03-30 | Texas Instruments Incorporated | Siderail with mold compound relief |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7335972B2 (en) | 2003-11-13 | 2008-02-26 | Sandia Corporation | Heterogeneously integrated microsystem-on-a-chip |
DE102005055761B4 (de) * | 2005-11-21 | 2008-02-07 | Infineon Technologies Ag | Leistungshalbleiterbauelement mit Halbleiterchipstapel in Brückenschaltung und Verfahren zur Herstellung desselben |
US20080036078A1 (en) | 2006-08-14 | 2008-02-14 | Ciclon Semiconductor Device Corp. | Wirebond-less semiconductor package |
US8263434B2 (en) | 2009-07-31 | 2012-09-11 | Stats Chippac, Ltd. | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP |
US20120326287A1 (en) * | 2011-06-27 | 2012-12-27 | National Semiconductor Corporation | Dc/dc convertor power module package incorporating a stacked controller and construction methodology |
US20120228696A1 (en) * | 2011-03-07 | 2012-09-13 | Texas Instruments Incorporated | Stacked die power converter |
US8669650B2 (en) * | 2011-03-31 | 2014-03-11 | Alpha & Omega Semiconductor, Inc. | Flip chip semiconductor device |
US9508633B2 (en) | 2011-08-22 | 2016-11-29 | Texas Instruments Incorporated | High performance power transistor having ultra-thin package |
US20130082383A1 (en) | 2011-10-03 | 2013-04-04 | Texas Instruments Incorporated | Electronic assembly having mixed interface including tsv die |
US9184122B2 (en) * | 2012-06-06 | 2015-11-10 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer and method of manufacture thereof |
-
2014
- 2014-02-20 US US14/185,502 patent/US9136256B2/en active Active
-
2015
- 2015-02-20 WO PCT/US2015/016739 patent/WO2015127159A1/en active Application Filing
- 2015-02-20 JP JP2016553573A patent/JP6534677B2/ja active Active
- 2015-02-20 CN CN201580008988.9A patent/CN106030788B/zh active Active
- 2015-02-20 EP EP15751635.2A patent/EP3108503B1/en active Active
- 2015-08-11 US US14/823,487 patent/US9355946B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP6534677B2 (ja) | 2019-06-26 |
US20150235999A1 (en) | 2015-08-20 |
EP3108503A4 (en) | 2017-11-22 |
EP3108503B1 (en) | 2019-04-10 |
WO2015127159A1 (en) | 2015-08-27 |
EP3108503A1 (en) | 2016-12-28 |
US9355946B2 (en) | 2016-05-31 |
US9136256B2 (en) | 2015-09-15 |
CN106030788A (zh) | 2016-10-12 |
CN106030788B (zh) | 2019-03-08 |
US20150348890A1 (en) | 2015-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10930582B2 (en) | Semiconductor device having terminals directly attachable to circuit board | |
US9425132B2 (en) | Stacked synchronous buck converter having chip embedded in outside recess of leadframe | |
US9779967B2 (en) | Ultra-thin power transistor and synchronous buck converter having customized footprint | |
JP2015530748A (ja) | 低いオン抵抗を有する、垂直にスタックされたパワーfet及び同期バックコンバータ | |
CN108155168B (zh) | 电子器件 | |
JP6534677B2 (ja) | スタックされたチップ及びインターポーザを備えた部分的に薄化されたリードフレームを有するコンバータ | |
CN116053148A (zh) | 具有双侧冷却的功率模块封装 | |
CN107546191B (zh) | 具有单列直插引线模块的半导体功率器件及其制备方法 | |
US20240030200A1 (en) | Semiconductor package and method | |
US20220293525A1 (en) | Packaged half-bridge circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180219 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180219 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190508 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190529 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6534677 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |