JP2017212431A - Capacitor and circuit board including the same - Google Patents
Capacitor and circuit board including the same Download PDFInfo
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- JP2017212431A JP2017212431A JP2017054481A JP2017054481A JP2017212431A JP 2017212431 A JP2017212431 A JP 2017212431A JP 2017054481 A JP2017054481 A JP 2017054481A JP 2017054481 A JP2017054481 A JP 2017054481A JP 2017212431 A JP2017212431 A JP 2017212431A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 43
- 230000000149 penetrating effect Effects 0.000 claims abstract description 5
- 230000009467 reduction Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 48
- 238000000034 method Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
Abstract
Description
本発明は、キャパシタ及びこれを含む回路基板に関する。 The present invention relates to a capacitor and a circuit board including the capacitor.
キャパシタ（ｃａｐａｃｉｔｏｒ）は、電気回路における電気を貯蔵する装置であって、離隔している導体板の間に誘電体が形成され、２つの導体板と誘電体との境界部分に電荷が貯蔵されることができる。 A capacitor is a device that stores electricity in an electric circuit, and a dielectric is formed between conductor plates that are separated from each other, and electric charges are stored at a boundary portion between the two conductor plates and the dielectric. it can.
キャパシタは、電子製品の軽薄短小化、高効率化への要求に対応するために回路基板に内蔵することができる。また、キャパシタは、回路基板に内蔵されるその他の電子素子に電気的に接続することになるので、電気的特性の向上及び回路の密集度を考慮して様々な方式により印刷回路基板に内蔵するように設計されている。 Capacitors can be built into circuit boards to meet the demands for electronic products to be lighter, thinner, and more efficient. In addition, since the capacitor is electrically connected to other electronic elements incorporated in the circuit board, the capacitor is incorporated in the printed circuit board by various methods in consideration of improvement in electrical characteristics and circuit density. Designed to be
本発明の一実施例によれば、回路基板の薄型化を実現するために誘電体層を貫通するビアが相互対向するように配置され、相互異なる極性を有する電極を形成することにより、キャパシタが内蔵された回路基板を実現することができる。 According to one embodiment of the present invention, in order to reduce the thickness of a circuit board, vias penetrating through a dielectric layer are arranged so as to face each other, and electrodes having different polarities are formed. A built-in circuit board can be realized.
本願で用いた用語は、ただ特定の実施例を説明するために用いたものであって、本発明を限定するものではない。単数の表現は、文の中で明らかに表現しない限り、複数の表現を含む。 The terms used in the present application are merely used to describe particular embodiments, and are not intended to limit the present invention. A singular expression includes the plural expression unless it is explicitly expressed in a sentence.
本出願で、ある部分がある構成要素を「含む」とするとき、これは、特別に反対の記載がない限り、他の構成要素を除外するのではなく、他の構成要素をさらに含むことができることを意味する。また、明細書の全般にわたって、「上に」とは、対象部分の上または下に位置することを意味し、必ずしも重力方向を基準にして上側に位置することを意味するものではない。 In this application, when a part “includes” a component, it does not exclude other components but specifically includes other components unless specifically stated to the contrary. Means you can. Further, throughout the specification, “on” means located above or below the target portion, and does not necessarily mean located above the gravity direction.
また、結合と言うことは、各構成要素の間の接合関係において、各構成要素の間に物理的に直接接合される場合のみを意味するのではなく、他の構成が各構成要素の間に介在されて、その他の構成に構成要素がそれぞれ接合されている場合まで包括する概念で使うようにする。また、「結合」とは、各構成要素の間の接触関係において、各構成要素の間に物理的に直接接触する場合のみを意味するものではなく、他の構成が各構成要素の間に介在され、この「他の構成」に構成要素がそれぞれ接触している場合まで包括する概念として使用する。 In addition, the term “coupled” does not mean only the case where each component is physically directly joined in the joining relationship between the components, but other configurations are arranged between the components. It is used in a concept that is comprehensive until it is interposed and other components are joined to each other. In addition, the term “coupled” does not mean that in the contact relationship between the components, the components are physically directly in contact with each other, and other configurations are interposed between the components. It is used as a concept encompassing even when components are in contact with the “other configurations”.
図面に示された各構成の大きさ及び厚さは、説明の便宜上任意に示したものであり、本発明が必ずしもそれらに限定されることはない。 The size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited thereto.
以下、本発明に係るキャパシタ及びこれを含む回路基板の実施例を添付図面に基づいて詳細に説明し、添付図面に基づいて説明するに当たり、同一または対応する構成要素には同一の図面符号を付し、これに対する重複説明を省略する。 Hereinafter, embodiments of a capacitor and a circuit board including the capacitor according to the present invention will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals. In addition, redundant explanation for this will be omitted.
本発明の実施例に係る回路基板は、電子素子等が装着されるメインボード（ｍａｉｎ ｂｏａｒｄ）、パッケージ基板（ｐａｃｋａｇｅ ｓｕｂｓｔｒａｔｅ）、パッケージ（ｐａｃｋａｇｅ）を含む概念である。 The circuit board according to the embodiment of the present invention is a concept including a main board, a package substrate, and a package on which electronic elements are mounted.
（第１実施例）
図１は、本発明の第１実施例に係る回路基板１０００の例示図である。図２は、本発明の第１実施例に係る回路基板１０００の一部分を示す図である。図３は、本発明の第１実施例に係る回路基板１０００の一部分の分解斜視図である。図４は、本発明の第１実施例に係る回路基板１０００の一部分の断面図である。
(First embodiment)
FIG. 1 is an exemplary view of a circuit board 1000 according to a first embodiment of the present invention. FIG. 2 is a view showing a part of the circuit board 1000 according to the first embodiment of the present invention. FIG. 3 is an exploded perspective view of a part of the circuit board 1000 according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view of a portion of the circuit board 1000 according to the first embodiment of the present invention.
図１から図４を参照すると、本発明の第１実施例に係る回路基板１０００は、単層キャパシタ１００を含み、キャパシタ１００は、誘電体層Ｌ、第１電極１１１、第２電極１２１を含む。 1 to 4, a circuit board 1000 according to a first embodiment of the present invention includes a single layer capacitor 100, and the capacitor 100 includes a dielectric layer L, a first electrode 111, and a second electrode 121. .
第１電極１１１は、誘電体層Ｌを貫通する第１ビア１１を含むことができ、第１ビア１１に電気的に接続する第１導電性パターン２１をさらに含むことができる。 The first electrode 111 may include a first via 11 that penetrates the dielectric layer L, and may further include a first conductive pattern 21 that is electrically connected to the first via 11.
第１導電性パターン２１は、第１ビア１１上に形成されることができる（図３参照）。 The first conductive pattern 21 can be formed on the first via 11 (see FIG. 3).
第２電極１２１は誘電体層Ｌを貫通し、第１ビア１１と対向する第２ビア１２を含むことができ、第２ビア１２に電気的に接続する第２導電性パターン２２をさらに含むことができる。 The second electrode 121 may include a second via 12 that penetrates the dielectric layer L and faces the first via 11, and further includes a second conductive pattern 22 that is electrically connected to the second via 12. Can do.
第２導電性パターン２２は、第２ビア１２上に形成されることができる（図３参照）。 The second conductive pattern 22 may be formed on the second via 12 (see FIG. 3).
一方、第１ビア１１または第２ビア１２は、複数形成可能である。 On the other hand, a plurality of first vias 11 or second vias 12 can be formed.
図２及び図３を参照すると、本発明の第１実施例に係る回路基板１０００において、キャパシタ１００は、第１ビア１１及び第２ビア１２の一部が内部電極として形成され、それ以外の第１ビア１１、第２ビア１２、第１導電性パターン２１及び第２導電性パターン２２は、外部電極として形成されることができる。 Referring to FIGS. 2 and 3, in the circuit board 1000 according to the first embodiment of the present invention, the capacitor 100 includes a first via 11 and a part of the second via 12 as internal electrodes. The first via 11, the second via 12, the first conductive pattern 21, and the second conductive pattern 22 can be formed as external electrodes.
第１電極１１１と第２電極１２１は、相互異なる極性の電源が印加され、例えば、第１電極１１１には陽極の、第２電極１２１には陰極の電源が印加されることができる。 The first electrode 111 and the second electrode 121 may be supplied with power having different polarities. For example, the first electrode 111 may be supplied with an anode, and the second electrode 121 may be supplied with a cathode.
第１ビア１１及び第２ビア１２に相互異なる極性の電源が印加されると、第１ビア１１及び第２ビア１２と誘電体層Ｌとの境界面には、相互極性の異なる電荷が蓄積され得る。 When power supplies having different polarities are applied to the first via 11 and the second via 12, charges having different polarities are accumulated at the boundary surfaces between the first via 11 and the second via 12 and the dielectric layer L. obtain.
誘電体層Ｌに蓄積される電荷の量（静電容量、単位：ファラッド、Ｆ）は、ビア１１、１２の積層面積Ｔ１が大きいほど、第１ビア１１と第２ビア１２との相互間隔Ｗ１が狭いほど増加する。 The amount of charge accumulated in the dielectric layer L (capacitance, unit: farad, F) is such that the larger the stacked area T1 of the vias 11, 12, the greater the mutual interval W1 between the first via 11 and the second via 12. The narrower it is, the more it increases.
キャパシタ１００の静電容量を制御するために、第１ビア１１と第２ビア１２との間隔Ｗ１、第１ビア１１及び第２ビア１２の厚さＴ１は、異なるように形成されることができる。 In order to control the capacitance of the capacitor 100, the interval W1 between the first via 11 and the second via 12 and the thickness T1 of the first via 11 and the second via 12 can be formed differently. .
同様に、第１導電性パターン２１と第２導電性パターン２２との間隔Ｗ２及び厚さＴ２は、異なるように形成されることができ、ビア１１、１２の間の間隔Ｗ１及び厚さＴ１と同一に形成されることができる。 Similarly, the interval W2 and the thickness T2 between the first conductive pattern 21 and the second conductive pattern 22 can be formed differently, and the interval W1 and the thickness T1 between the vias 11 and 12 can be different. Can be formed identically.
さらに、誘電体層Ｌは、比誘電率が大きい物質であるほどキャパシタ１００の静電容量が増加し、必要によってセラミック、タンタル、シリコンフィルム等誘電性質を有するものであれば、制限されずに用いることができる。 Furthermore, as the dielectric layer L is a substance having a higher relative dielectric constant, the capacitance of the capacitor 100 increases. If necessary, the dielectric layer L is used without limitation as long as it has dielectric properties such as ceramic, tantalum, and silicon film. be able to.
図４を参照すると、本発明の第１実施例に係る回路基板１０００は、最外層にキャパシタ１００を形成することができる。 Referring to FIG. 4, in the circuit board 1000 according to the first embodiment of the present invention, the capacitor 100 can be formed in the outermost layer.
回路基板１０００が電子素子等を実装するためのパッケージ基板である場合、キャパシタ１００を実装するためのソルダー、ワイヤ等の既存方式を用いずに回路基板１０００に形成することができる。 When the circuit board 1000 is a package board for mounting an electronic element or the like, it can be formed on the circuit board 1000 without using an existing method such as a solder or a wire for mounting the capacitor 100.
また、キャパシタ１００上に電子素子を配置し、キャパシタ１００と電子素子との接続距離を最小化することができる。 Further, an electronic element can be arranged on the capacitor 100, and the connection distance between the capacitor 100 and the electronic element can be minimized.
(第２実施例)
図５は、本発明の第２実施例に係る回路基板２０００を示す図である。
(Second embodiment)
FIG. 5 is a diagram illustrating a circuit board 2000 according to the second embodiment of the present invention.
図５を参照すると、本発明の第２実施例に係る回路基板２０００においてキャパシタ１００は、内層に形成することができる。 Referring to FIG. 5, in the circuit board 2000 according to the second embodiment of the present invention, the capacitor 100 can be formed in the inner layer.
キャパシタ１００は、回路基板２０００の内層に形成され、キャパシタ１００を中心にして下部と上部にそれぞれ絶縁層Ｉ１、Ｉ２、Ｉ３と絶縁層Ｉ４、Ｉ５が形成されることができる。 The capacitor 100 is formed in the inner layer of the circuit board 2000, and the insulating layers I1, I2, I3 and the insulating layers I4, I5 can be formed in the lower and upper portions around the capacitor 100, respectively.
キャパシタ１００の上部または下部に形成される絶縁層の数は、必要によって変更することが可能である。 The number of insulating layers formed above or below the capacitor 100 can be changed as necessary.
能動素子が回路基板２０００に内蔵される場合、能動素子との信号伝達距離を最小化するために、キャパシタ１００は回路基板の内層に形成することができる。 When the active element is embedded in the circuit board 2000, the capacitor 100 can be formed in the inner layer of the circuit board in order to minimize the signal transmission distance with the active element.
（第３実施例）
図６は、本発明の第３実施例に係る回路基板３０００の一部を示す図である。
(Third embodiment)
FIG. 6 is a view showing a part of a circuit board 3000 according to the third embodiment of the present invention.
図６を参照すると、第３実施例に係る回路基板３０００において、第１ビア１１と第２第２ビア１２のすべてが内部電極を形成する。 Referring to FIG. 6, in the circuit board 3000 according to the third embodiment, all of the first via 11 and the second second via 12 form an internal electrode.
図３と比較すると、第３実施例に係る回路基板３０００は、第１実施例に係る回路基板１０００に比べて内部電極の面積をより広く形成することができる。 Compared to FIG. 3, the circuit board 3000 according to the third embodiment can be formed with a larger area of the internal electrode than the circuit board 1000 according to the first embodiment.
結果的に、キャパシタ１００に形成される第１導電性パターン２１及び第２導電性パターン２２のパターン形成方法により、キャパシタの静電容量の大きさは異なるように形成されることができる。 As a result, the capacitance of the capacitor can be formed differently according to the pattern forming method of the first conductive pattern 21 and the second conductive pattern 22 formed on the capacitor 100.
（第４実施例）
図７Ａから図７Ｄは、本発明の第４実施例に係る回路基板４０００の一部を示す図である。
(Fourth embodiment)
7A to 7D are views showing a part of a circuit board 4000 according to a fourth embodiment of the present invention.
図７Ａから図７Ｄを参照すると、第４実施例に係る回路基板４０００において誘電体層ＬＯ１、ＬＩ、ＬＯ２は、３層で形成されたキャパシタ１００を含む。 7A to 7D, in the circuit board 4000 according to the fourth embodiment, the dielectric layers LO1, LI, and LO2 include a capacitor 100 formed of three layers.
第４実施例に係る回路基板４０００においてキャパシタ１００は、誘電体層ＬＯ１、ＬＩ、ＬＯ２と、第３電極１３１と、第４電極１４１と、を含む。 In the circuit board 4000 according to the fourth embodiment, the capacitor 100 includes dielectric layers LO1, LI, and LO2, a third electrode 131, and a fourth electrode 141.
誘電体層Ｌは、内層、第１外層及び第２外層の複数層で形成されることができる。 The dielectric layer L can be formed of a plurality of layers of an inner layer, a first outer layer, and a second outer layer.
第４実施例に示すように、誘電体層ＬＯ１、ＬＩ、ＬＯ２が３層である場合、積層順に第１外層ＬＯ１、内層ＬＩ、第２外層ＬＯ２となることができる。 As shown in the fourth embodiment, when the dielectric layers LO1, LI, and LO2 are three layers, the first outer layer LO1, the inner layer LI, and the second outer layer LO2 can be formed in the stacking order.
第３電極１３１は、内層ＬＩ及び上記第２外層ＬＯ２を貫通して形成される第３ビア１３を含む。 The third electrode 131 includes a third via 13 formed through the inner layer LI and the second outer layer LO2.
第４電極１４１は、内層及び上記第１外層ＬＯ１を貫通して形成され、第３ビア１３と対向して形成される第４ビア１４を含む。 The fourth electrode 141 includes a fourth via 14 that is formed through the inner layer and the first outer layer LO <b> 1 and is formed to face the third via 13.
第３電極１３１と第４電極１４１とは、相互異なる極性の電源が接続され、第３ビア１３と第４ビア１４に電位差を形成することができる。例えば、第３電極１３１には陽極、第４電極１４１には陰極が形成されて電位差を形成することができる。 The third electrode 131 and the fourth electrode 141 are connected to power supplies having different polarities, and a potential difference can be formed between the third via 13 and the fourth via 14. For example, an anode can be formed on the third electrode 131 and a cathode can be formed on the fourth electrode 141 to form a potential difference.
第３電極１３１は、第３ビア１３に電気的に接続される第３導電性パターン２３をさらに含むことができる。 The third electrode 131 may further include a third conductive pattern 23 that is electrically connected to the third via 13.
第４電極１４１は、第４ビア１４に電気的に接続される第４導電性パターン２４をさらに含むことができる。 The fourth electrode 141 may further include a fourth conductive pattern 24 that is electrically connected to the fourth via 14.
第３ビア１３または第４ビア１４は、スタックビアであってもよく、高容量の静電容量のために第３ビア１３と第４ビア１４との間隔を最小化することができる。 The third via 13 or the fourth via 14 may be a stacked via, and the distance between the third via 13 and the fourth via 14 can be minimized due to a high capacitance.
また、第３導電性パターン２３と第４導電性パターン２４の厚さを異なるものにして静電容量値を制御することができる。 Further, the capacitance values can be controlled by making the thicknesses of the third conductive pattern 23 and the fourth conductive pattern 24 different.
（第５実施例）
図８は、本発明の第５実施例に係る回路基板５０００の一部を示す図である。
(5th Example)
FIG. 8 is a view showing a part of a circuit board 5000 according to the fifth embodiment of the present invention.
図８を参照すると、内層は複数で形成されることができる。 Referring to FIG. 8, a plurality of inner layers may be formed.
第５実施例に係る回路基板５０００において内層が８層である場合、層の順に第１外層ＬＯ１、内層ＬＩ１〜ＬＩ８、第２外層ＬＯ２となることができる。 In the circuit board 5000 according to the fifth embodiment, when the inner layer is eight layers, the first outer layer LO1, the inner layers LI1 to LI8, and the second outer layer LO2 can be formed in the order of the layers.
本発明の第５実施例に係る回路基板５０００は、必要によって、示された誘電体層の以外にキャパシタの上部または下部に絶縁層をさらに含むことができる。 The circuit board 5000 according to the fifth embodiment of the present invention may further include an insulating layer above or below the capacitor, if necessary, in addition to the dielectric layer shown.
第５実施例によれば、第３電極１３１は、内層ＬＩ１〜ＬＩ８、及び上記第２外層ＬＯ２を貫通して形成される第３ビア１３を含む。 According to the fifth embodiment, the third electrode 131 includes the inner vias LI1 to LI8 and the third via 13 formed through the second outer layer LO2.
第５実施例によれば、第４電極１４１は、内層ＬＩ１〜ＬＩ８、及び上記第１外層ＬＯ１を貫通して形成され、第３ビア１３と対向して形成される第４ビア１４を含む。 According to the fifth embodiment, the fourth electrode 141 includes the fourth via 14 formed through the inner layers LI <b> 1 to LI <b> 8 and the first outer layer LO <b> 1 and facing the third via 13.
第５実施例に係る回路基板５０００において、静電容量は、内層に形成された第３ビア１３と第４ビア１４との間の間隔により変えることができる。 In the circuit board 5000 according to the fifth embodiment, the capacitance can be changed by the distance between the third via 13 and the fourth via 14 formed in the inner layer.
（その他の実施例）
図９は、本発明のその他の実施例に係る複数層で形成された回路基板の平面透視図である。
(Other examples)
FIG. 9 is a plan perspective view of a circuit board formed of a plurality of layers according to another embodiment of the present invention.
図９を参照すると、キャパシタの形状は、直方体以外に様々な形状を有することができる。 Referring to FIG. 9, the capacitor may have various shapes other than a rectangular parallelepiped.
図９を参照すると、その他の実施例に係る印刷回路基板は、積層された誘電体層上にビア工程を行った後、様々な形状にラウティングしてキャパシタ単位に分離することができる。分離されたキャパシタは、パッケージ基板及びその他の基板等に装着されることができる。 Referring to FIG. 9, the printed circuit board according to another embodiment may be separated into capacitors by performing a via process on the stacked dielectric layers and then routing to various shapes. The separated capacitor can be mounted on a package substrate and other substrates.
上述したように、本発明の実施例に係る回路基板及びキャパシタは、ビア加工を介してキャパシタの電極を形成することができ、ビアの間隔、厚さ、積層数に応じて静電容量値を変化させることができる。 As described above, the circuit board and the capacitor according to the embodiment of the present invention can form the electrode of the capacitor through via processing, and the capacitance value can be set according to the interval between the vias, the thickness, and the number of stacked layers. Can be changed.
さらに、導電性パターンに形成されるメッキの厚さ、形状などを異なるものに形成することで静電容量値を変化させることができる。 Further, the capacitance value can be changed by forming the plating formed on the conductive pattern in different thicknesses and shapes.
また、印刷回路基板のビア、導電性パターンによりキャパシタを形成することで、キャパシタを配置するためのソルダー、ワイヤなどの電気的接続工程を行わなくてもよく、回路基板とキャパシタ、その他の電子素子との電気的接続信頼性をより高めることができる。 In addition, by forming a capacitor with vias and conductive patterns on a printed circuit board, it is not necessary to perform an electrical connection process such as a solder and a wire for arranging the capacitor. The electrical connection reliability can be further improved.
以上、本発明においては具体的な構成要素等の特定事項、限定された実施例及び図面に基づいて説明したが、これは本発明をより容易に理解するために提供されたものであって、本発明は上記の実施例により限定されず、本発明が属する分野で通常的な知識を有する者であれば上記の記載から多様な修正及び変形が可能であることを理解できよう。 As described above, the present invention has been described based on specific matters such as specific components, limited examples, and drawings, which are provided for easier understanding of the present invention. The present invention is not limited to the above embodiments, and those skilled in the art to which the present invention belongs can understand that various modifications and variations can be made from the above description.
したがって、本発明の思想は、説明された実施例に局限されて決められてはならず、後述する特許請求の範囲のみならず、この特許請求の範囲と均等または等価的変形があるあらゆるものなどは、本発明の思想の範疇に属するといえよう。 Therefore, the idea of the present invention should not be limited to the embodiments described, and should be determined not only by the claims described below, but also by any equivalent or equivalent modification to the claims. Can be said to belong to the category of the idea of the present invention.
１００ キャパシタ
１１ 第１ビア
１２ 第２ビア
１３ 第３ビア
１４ 第４ビア
２１ 第１導電性パターン
２２ 第２導電性パターン
２３ 第３導電性パターン
２４ 第４導電性パターン
１１１ 第１電極
１２１ 第２電極
１３１ 第３電極
１４１ 第４電極
１０００、２０００、３０００、４０００、５０００ 回路基板
100 Capacitor 11 First Via 12 Second Via 13 Third Via 14 Fourth Via 21 First Conductive Pattern 22 Second Conductive Pattern 23 Third Conductive Pattern 24 Fourth Conductive Pattern 111 First Electrode 121 Second Electrode 131 Third electrode 141 Fourth electrode 1000, 2000, 3000, 4000, 5000 Circuit board
Claims (21)
前記誘電体層を貫通する第１ビアを含む第１電極と、
前記誘電体層を貫通し、前記第１ビアと対向する第２ビアを含む第２電極と、を含み、
前記第１電極及び前記第２電極は、相互異なる極性を有する、回路基板。 A dielectric layer;
A first electrode including a first via penetrating the dielectric layer;
A second electrode that penetrates through the dielectric layer and includes a second via facing the first via;
The circuit board, wherein the first electrode and the second electrode have different polarities.
前記第１ビアに電気的に接続する第１導電性パターンを含む請求項１または請求項２に記載の回路基板。 The first electrode is
The circuit board according to claim 1, further comprising a first conductive pattern electrically connected to the first via.
前記第２ビアに電気的に接続する第２導電性パターンを含む請求項１または請求項２に記載の回路基板。 The second electrode is
The circuit board according to claim 1, further comprising a second conductive pattern electrically connected to the second via.
前記誘電体層は、前記複数の絶縁層上に形成される請求項１または請求項２に記載の回路基板。 A plurality of insulating layers;
The circuit board according to claim 1, wherein the dielectric layer is formed on the plurality of insulating layers.
前記誘電体層は、前記複数の絶縁層の内層に形成される請求項１または請求項２に記載の回路基板。 A plurality of insulating layers;
The circuit board according to claim 1, wherein the dielectric layer is formed in an inner layer of the plurality of insulating layers.
前記内層及び前記第１外層を貫通して形成される第３ビアを含む第３電極と、
前記内層及び前記第２外層を貫通して形成され、前記第３ビアと対向して形成される第４ビアを含む第４電極と、を含む回路基板。 A dielectric layer formed of an inner layer, a first outer layer and a second outer layer;
A third electrode including a third via formed through the inner layer and the first outer layer;
And a fourth electrode formed through the inner layer and the second outer layer and including a fourth via formed to face the third via.
前記第３ビアに電気的に接続する第３導電性パターンを含む請求項９または請求項１０に記載の回路基板。 The third electrode is
The circuit board according to claim 9, further comprising a third conductive pattern electrically connected to the third via.
前記第４ビアに電気的に接続する第４導電性パターンを含む請求項９または請求項１０に記載の回路基板。 The fourth electrode is
The circuit board according to claim 9, further comprising a fourth conductive pattern electrically connected to the fourth via.
前記誘電体層を貫通する第１ビアを含む第１電極と、
前記誘電体層を貫通し、前記第１ビアと対向する第２ビアを含む第２電極と、を含むキャパシタ。 A first electrode including a dielectric layer and a first via penetrating the dielectric layer;
And a second electrode including a second via penetrating the dielectric layer and facing the first via.
前記第１ビアに電気的に接続する第１導電性パターンを含む請求項１４または請求項１５に記載のキャパシタ。 The first electrode is
The capacitor according to claim 14, further comprising a first conductive pattern electrically connected to the first via.
前記第２ビアに電気的に接続する第２導電性パターンを含む請求項１４または請求項１５に記載のキャパシタ。 The second electrode is
The capacitor according to claim 14, further comprising a second conductive pattern electrically connected to the second via.
前記内層及び前記第１外層を貫通し形成される第３ビアを含む第３電極と、
前記内層及び前記第２外層を貫通して形成され、前記第３ビアと対向して形成される第４ビアを含む第４電極と、を含むキャパシタ。 A dielectric layer formed of an inner layer, a first outer layer and a second outer layer;
A third electrode including a third via formed through the inner layer and the first outer layer;
And a fourth electrode including a fourth via formed through the inner layer and the second outer layer and formed opposite to the third via.
前記第３ビアに電気的に接続する第３導電性パターンを含む請求項１８または請求項１９に記載のキャパシタ。 The third electrode is
The capacitor according to claim 18, comprising a third conductive pattern electrically connected to the third via.
前記第４ビアに電気的に接続する第４導電性パターンを含む請求項１８または請求項１９に記載のキャパシタ。 The fourth electrode is
The capacitor according to claim 18, further comprising a fourth conductive pattern electrically connected to the fourth via.
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