JP2017152484A - Wiring board - Google Patents

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JP2017152484A
JP2017152484A JP2016032240A JP2016032240A JP2017152484A JP 2017152484 A JP2017152484 A JP 2017152484A JP 2016032240 A JP2016032240 A JP 2016032240A JP 2016032240 A JP2016032240 A JP 2016032240A JP 2017152484 A JP2017152484 A JP 2017152484A
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wiring
wiring board
semiconductor element
insulating
conductor
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学 一瀬
Manabu Ichinose
学 一瀬
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Kyocera Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a wiring board without a solder resist layer, in which the wet spread of sealing resin is prevented in a favorable manner.SOLUTION: A wiring board 20 includes an insulating base 1 which is formed by stacking a plurality of insulating layers 1a to 1i and includes a mount part 20A on which a semiconductor element S is mounted, and a wiring conductor 2 including conductive layers 2a to 2j formed on a surface of the insulating layers 1a to 1i. Around the mount part 20A, a solid pattern 11 including the conductive layer 2a covered with the uppermost insulating layer 1a is disposed. In the uppermost insulating layer 1a, a groove 12 with the solid pattern 11 serving as a bottom surface is formed close to the mount part 20A.SELECTED DRAWING: Figure 1

Description

本発明は、半導体素子を搭載するための配線基板に関するものである。   The present invention relates to a wiring board for mounting a semiconductor element.

半導体素子を搭載するための配線基板は、絶縁層と配線導体とが交互に複数積層されているとともに、最表層にソルダーレジスト層が被着された多層構造をしている。配線基板の上面中央部には、半導体素子が搭載される搭載部が形成されている。搭載部には、配線導体の一部から成る複数の半導体素子接続パッドが格子状の並びに配列されている。配線基板の下面は、外部電気回路基板との接続面になっている。この接続面には、配線導体の一部から成る複数の外部接続パッドが格子状の並びに配列されている。半導体素子接続パッドと外部接続パッドとは、所定のもの同士が配線基板内部の配線導体を介して電気的に接続されている。半導体素子接続パッドには、半導体素子の電極端子がフリップチップ接続される。外部接続パッドと外部電気回路基板とは、半田ボール接続される。   A wiring board for mounting a semiconductor element has a multilayer structure in which a plurality of insulating layers and wiring conductors are alternately stacked, and a solder resist layer is deposited on the outermost layer. A mounting portion on which a semiconductor element is mounted is formed at the center of the upper surface of the wiring board. In the mounting portion, a plurality of semiconductor element connection pads made of a part of the wiring conductor are arranged in a grid. The lower surface of the wiring board is a connection surface with an external electric circuit board. A plurality of external connection pads made of a part of the wiring conductor are arranged in a grid on the connection surface. A predetermined number of semiconductor element connection pads and external connection pads are electrically connected to each other via a wiring conductor inside the wiring board. The semiconductor element electrode pads are flip-chip connected to the electrode terminals of the semiconductor element. The external connection pads and the external electric circuit board are connected by solder balls.

フリップチップ接続では、半導体素子の下面に形成された電極端子と半導体素子接続パッドとを半田バンプを介して接続する。フリップチップ接続された半導体素子と配線基板との間には、隙間が形成される。この隙間は、アンダーフィルと呼ばれる封止樹脂により充填される。封止樹脂を充填するには、未硬化の液状の熱硬化性樹脂を半導体素子と配線基板との隙間に注入した後、熱硬化させる方法が採用される。ところが、液状の樹脂を注入する際、あるいは注入した後、樹脂の一部が搭載部の周囲に大きく濡れ広がってしまうことがある。   In the flip-chip connection, the electrode terminals formed on the lower surface of the semiconductor element and the semiconductor element connection pads are connected via solder bumps. A gap is formed between the flip-chip connected semiconductor element and the wiring board. This gap is filled with a sealing resin called underfill. In order to fill the sealing resin, a method of injecting an uncured liquid thermosetting resin into the gap between the semiconductor element and the wiring substrate and then thermosetting is employed. However, when or after the liquid resin is injected, a part of the resin may be greatly spread around the mounting portion.

そこで、搭載部の周囲のソルダーレジスト層に溝を設けて封止樹脂の濡れ広がりを防止することが提案されている。しかしながら、最表面にソルダーレジスト層を設けない配線基板もあり、この場合、最表層の絶縁層上に溝を例えばレーザ加工により設ける必要がある。この場合、溝の深さのコントロールが難しく、封止樹脂の濡れ広がりを溝で良好に止めることが困難となる。   Therefore, it has been proposed to provide a groove in the solder resist layer around the mounting portion to prevent the sealing resin from spreading out. However, some wiring boards do not have a solder resist layer on the outermost surface. In this case, it is necessary to provide grooves on the outermost insulating layer by, for example, laser processing. In this case, it is difficult to control the depth of the groove, and it becomes difficult to satisfactorily stop the wetting and spreading of the sealing resin with the groove.

特開２００４−３４９３９９号公報JP 2004-349399 A

本発明が解決しようとする課題は、ソルダーレジスト層のない配線基板において、封止樹脂の濡れ広がりを良好に防止することが可能な配線基板を提供することにある。   The problem to be solved by the present invention is to provide a wiring board that can satisfactorily prevent the wetting and spreading of the sealing resin in a wiring board without a solder resist layer.

本発明の配線基板は、複数の絶縁層が積層されて成り、上面に半導体素子が搭載される搭載部を有する絶縁基体と、前記各絶縁層の表面に被着された導体層から成る配線導体とを具備して成る配線基板であって、前記搭載部の周囲に、最上層の前記絶縁層で被覆された前記導体層から成るベタ状パターンが配置されているとともに、最上層の前記絶縁層に、前記ベタ状パターンを底面とする溝が前記搭載部に近接して形成されていることを特徴とするものである。   The wiring substrate of the present invention comprises a wiring conductor comprising a plurality of insulating layers laminated, an insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface, and a conductor layer deposited on the surface of each insulating layer. And a solid pattern made of the conductor layer covered with the uppermost insulating layer is disposed around the mounting portion, and the uppermost insulating layer In addition, a groove having the solid pattern as a bottom surface is formed in the vicinity of the mounting portion.

本発明の配線基板によれば、搭載部の周囲に最上層の絶縁層で被覆された導体層から成るベタ状パターンが配置されているとともに、最上層の絶縁層に、ベタ状パターンを底面とする溝が搭載部に近接して形成されていることから、ベタ状パターンがストッパー層となって溝の深さを一定とすることができるとともに、溝の底面を形成するベタ状パターンと封止樹脂との濡れ性が良好なため、ソルダーレジスト層のない配線基板において、封止樹脂の濡れ広がりを良好に防止することが可能な配線基板を提供することができる。   According to the wiring board of the present invention, the solid pattern composed of the conductor layer covered with the uppermost insulating layer is disposed around the mounting portion, and the solid pattern is formed on the uppermost insulating layer as the bottom surface. Since the groove to be formed is formed close to the mounting portion, the solid pattern can be a stopper layer to make the depth of the groove constant, and the solid pattern that forms the bottom surface of the groove and sealing Since the wettability with the resin is good, it is possible to provide a wiring board capable of satisfactorily preventing the sealing resin from spreading in a wiring board having no solder resist layer.

図１は、本発明の配線基板の実施形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図２は、本発明の配線基板の実施形態の一例を示す概略上面図である。FIG. 2 is a schematic top view showing an example of an embodiment of a wiring board according to the present invention. 図３は、本発明の配線基板の実施形態の一例に半導体素子を搭載するとともに半導体素子と配線基板との間に封止樹脂を充填した状態を示す概略断面図である。FIG. 3 is a schematic cross-sectional view showing a state in which a semiconductor element is mounted on an example of an embodiment of a wiring board of the present invention and a sealing resin is filled between the semiconductor element and the wiring board.

次に、本発明の配線基板の実施形態の一例を、図１〜図３を参照して詳細に説明する。図１は、本発明の実施形態の一例である配線基板２０を示す概略断面図である。図１において、１は絶縁基体、２は配線導体である。主としてこれらの絶縁基体１と配線導体２とで配線基板２０が形成されている。   Next, an example of an embodiment of the wiring board of the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing a wiring board 20 which is an example of an embodiment of the present invention. In FIG. 1, 1 is an insulating substrate and 2 is a wiring conductor. A wiring substrate 20 is mainly formed by the insulating base 1 and the wiring conductor 2.

本例の配線基板２０においては、絶縁基体１は、複数の絶縁層１ａ〜１ｉを含んでいる。また、配線導体２は、複数の導体層２ａ〜２ｊを含んでいる。   In the wiring board 20 of this example, the insulating base 1 includes a plurality of insulating layers 1a to 1i. The wiring conductor 2 includes a plurality of conductor layers 2a to 2j.

絶縁基体１の上面中央部には搭載部２０Ａが設けられている。搭載部２０Ａは、半導体素子Ｓを搭載するための四角形状の領域である。搭載部２０Ａには、多数の半導体素子接続パッド３が二次元的な並びに配列されている。半導体素子接続パッド３には、半導体素子Ｓの電極端子Ｔがフリップチップ接続により接続される。   A mounting portion 20 </ b> A is provided at the center of the upper surface of the insulating substrate 1. The mounting portion 20A is a quadrangular region for mounting the semiconductor element S. A large number of semiconductor element connection pads 3 are arranged two-dimensionally on the mounting portion 20A. The electrode terminal T of the semiconductor element S is connected to the semiconductor element connection pad 3 by flip chip connection.

絶縁基体１の下面は、外部電気回路基板との接続面となっている。絶縁基体１の下面には、その略全領域にわたり多数の外部接続パッド４が二次元的な並びに配列されている。外部接続パッド４は、外部電気回路基板の配線導体に接続される。   The lower surface of the insulating substrate 1 is a connection surface with an external electric circuit board. On the lower surface of the insulating base 1, a large number of external connection pads 4 are arranged two-dimensionally over substantially the entire area. The external connection pad 4 is connected to the wiring conductor of the external electric circuit board.

絶縁基体１を構成する絶縁層１ｅは、本例の配線基板２０におけるコア部材である。絶縁層１ｅは、例えばガラス繊維束を縦横に織り込んだガラス織物にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて成る。絶縁層１ｅの厚みは、０．１〜１ｍｍ程度である。絶縁層１ｅには、その上面から下面にかけて多数のスルーホール５が形成されている。スルーホール５内には、スルーホール導体６が被着されている。このスルーホール導体６を介して絶縁層１ｅ上下面の配線導体２ｅと２ｆとが接続されている。   The insulating layer 1e constituting the insulating base 1 is a core member in the wiring board 20 of this example. The insulating layer 1e is formed, for example, by impregnating a glass fabric in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The thickness of the insulating layer 1e is about 0.1 to 1 mm. A large number of through holes 5 are formed in the insulating layer 1e from the upper surface to the lower surface. A through-hole conductor 6 is deposited in the through-hole 5. The wiring conductors 2e and 2f on the upper and lower surfaces of the insulating layer 1e are connected through the through-hole conductor 6.

このような絶縁層１ｅは、ガラス織物に未硬化の熱硬化性樹脂を含浸させた絶縁シートを熱硬化させた後、これに上面から下面にかけてドリル加工を施すことにより製作される。絶縁層１ａ上下面の配線導体２ｅ，２ｆは、絶縁層１ｅ用の絶縁シートの上下全面に銅箔を貼着しておくとともにこの銅箔をシートの硬化後にエッチング加工することにより所定のパターンに形成される。スルーホール５内のスルーホール導体６は、絶縁層１ｅにスルーホール５を設けた後に、このスルーホール５内面に無電解めっき法および電解めっき法により銅めっき膜を析出させることにより形成される。配線導体２ｅ，２ｆの厚みは、５０〜２０μｍ程度である。   Such an insulating layer 1e is manufactured by thermally curing an insulating sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling the insulating sheet from the upper surface to the lower surface. The wiring conductors 2e and 2f on the upper and lower surfaces of the insulating layer 1a are formed into a predetermined pattern by attaching a copper foil to the entire upper and lower surfaces of the insulating sheet for the insulating layer 1e and etching the copper foil after the sheet is cured. It is formed. The through-hole conductor 6 in the through-hole 5 is formed by depositing a copper plating film on the inner surface of the through-hole 5 by electroless plating and electrolytic plating after providing the through-hole 5 in the insulating layer 1e. The thickness of the wiring conductors 2e and 2f is about 50 to 20 μm.

さらに、スルーホール導体６が被着されたスルーホール５は、その内部が孔埋め樹脂７で充填されている。孔埋め樹脂７は、エポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る。孔埋め樹脂７は、スルーホール５を塞ぐことによりスルーホール５の直上および直下に配線導体２ｅ，２ｆおよび絶縁層１ｄ，１ｆを形成可能とするためのものである。孔埋め樹脂７は、未硬化のペースト状の熱硬化性樹脂をスルーホール５内にスクリーン印刷法により充填し、それを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。   Further, the inside of the through hole 5 to which the through hole conductor 6 is attached is filled with a hole filling resin 7. The hole-filling resin 7 is made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The hole-filling resin 7 is for making it possible to form the wiring conductors 2e and 2f and the insulating layers 1d and 1f directly above and below the through-hole 5 by closing the through-hole 5. The hole-filling resin 7 is formed by filling an uncured paste-like thermosetting resin into the through-hole 5 by a screen printing method, thermally curing it, and then polishing its upper and lower surfaces substantially flatly. The

絶縁層１ｅの上下面に積層された各絶縁層１ａ〜１ｄ，１ｆ〜１ｉは、エポキシ樹脂等の熱硬化性樹脂から成る。絶縁層１ａ〜１ｄ，１ｆ〜１ｉの厚みは、それぞれ５〜２０μｍ程度である。絶縁層１ａ〜１ｄ，１ｆ〜１ｉは、各層の上面から下面にかけて複数のビアホール８を有している。ビアホール８内にはビアホール導体９が充填されている。そして、上層の配線導体２ａ〜２ｄ，２ｇ〜２ｉと下層の配線導体２ｂ〜２ｅ，２ｈ〜２ｊとがビアホール導体９を介して互いに接続されている。   The insulating layers 1a to 1d and 1f to 1i laminated on the upper and lower surfaces of the insulating layer 1e are made of a thermosetting resin such as an epoxy resin. The thicknesses of the insulating layers 1a to 1d and 1f to 1i are about 5 to 20 μm, respectively. The insulating layers 1a to 1d and 1f to 1i have a plurality of via holes 8 from the upper surface to the lower surface of each layer. A via hole conductor 9 is filled in the via hole 8. The upper wiring conductors 2 a to 2 d and 2 g to 2 i and the lower wiring conductors 2 b to 2 e and 2 h to 2 j are connected to each other through the via-hole conductor 9.

このような各絶縁層１ａ〜１ｄ，１ｆ〜１ｉは、厚みが５〜２０μｍ程度の未硬化の熱硬化性樹脂から成る絶縁フィルムを絶縁層１ｅの上下面または絶縁層１ｂ〜１ｄ，１ｆ〜１ｈ表面に貼着し、これを熱硬化させるとともにレーザ加工によりビアホール８を穿孔することによって形成される。各絶縁層１ａ〜１ｄ，１ｆ〜１ｉの表面の配線導体２ａ〜２ｄ，２ｈ〜２ｊおよびビアホール８内のビアホール導体９は、各絶縁層１ａ〜１ｄ，１ｆ〜１ｉを形成する毎に各絶縁層１ａ〜１ｄ，１ｆ〜１ｉの表面およびビアホール８内に銅めっきを被着させることによって形成される。銅めっきの被着には、周知のセミアディティブ法を用いる。配線導体２ａ〜２ｄ，２ｈ〜２ｊの厚みは、５〜１０μｍ程度である。   Each of the insulating layers 1a to 1d and 1f to 1i is made of an insulating film made of an uncured thermosetting resin having a thickness of about 5 to 20 μm, and the upper and lower surfaces of the insulating layer 1e or the insulating layers 1b to 1d and 1f to 1h. It is formed by sticking to the surface, thermosetting it, and drilling the via hole 8 by laser processing. The wiring conductors 2a to 2d and 2h to 2j on the surfaces of the insulating layers 1a to 1d and 1f to 1i and the via-hole conductor 9 in the via hole 8 are formed each time the insulating layers 1a to 1d and 1f to 1i are formed. It is formed by depositing copper plating on the surfaces 1a to 1d and 1f to 1i and in the via holes 8. A well-known semi-additive method is used for copper plating deposition. The thickness of the wiring conductors 2a to 2d and 2h to 2j is about 5 to 10 μm.

本例の配線基板２０においては、半導体素子接続パッド３および外部接続パッド４を含む配線導体２には、信号用と接地用と電源用とがある。信号用の半導体素子接続パッド３は、その多くが搭載部２０Ａの外周部に配設されている。接地用の半導体素子接続パッド３および電源用の半導体素子接続パッド３は、その多くが搭載部２０Ａの中央部に配設されている。これに対応して信号用の外部接続パッド４は、その多くが絶縁基体１の下面外周部に配設されている。また、接地用の外部接続パッド４および電源用の外部接続パッド４は、絶縁基体１の下面中央部および外周部に配設されている。   In the wiring board 20 of this example, the wiring conductor 2 including the semiconductor element connection pad 3 and the external connection pad 4 includes a signal, a ground, and a power source. Most of the signal semiconductor element connection pads 3 are arranged on the outer peripheral portion of the mounting portion 20A. Most of the grounding semiconductor element connection pads 3 and the power supply semiconductor element connection pads 3 are arranged at the center of the mounting portion 20A. Correspondingly, most of the signal external connection pads 4 are arranged on the outer peripheral portion of the lower surface of the insulating substrate 1. The grounding external connection pad 4 and the power supply external connection pad 4 are disposed at the center and the outer periphery of the lower surface of the insulating substrate 1.

信号用の半導体素子接続パッド３と信号用の外部接続パッド４とは、信号用の配線導体２により互いに接続されている。信号用の配線導体２は、絶縁層１ｂ〜１ｄの表面を搭載部２０Ａに対応する領域から絶縁基体１の外周部に向けて延びる帯状パターン１０を有している。この帯状パターン１０と信号用の半導体素子接続パッド３とは、搭載部２０Ａに対応する領域において、ビアホール導体９を介して接続されている。また、この帯状パターン１０と信号用の外部接続パッド４とは、絶縁基体１の外周部において、スルーホール導体６およびビアホール導体９を介して接続されている。   The signal semiconductor element connection pad 3 and the signal external connection pad 4 are connected to each other by a signal wiring conductor 2. The signal wiring conductor 2 has a belt-like pattern 10 extending from the region corresponding to the mounting portion 20 </ b> A toward the outer peripheral portion of the insulating base 1 on the surface of the insulating layers 1 b to 1 d. The strip pattern 10 and the signal semiconductor element connection pad 3 are connected via a via-hole conductor 9 in a region corresponding to the mounting portion 20A. Further, the belt-like pattern 10 and the signal external connection pad 4 are connected to each other through the through-hole conductor 6 and the via-hole conductor 9 on the outer peripheral portion of the insulating substrate 1.

接地用の半導体素子接続パッド３と接地用の外部接続パッド４とは、接地用の配線導体２により互いに接続されている。電源用の半導体素子接続パッド３と電源用の外部接続パッド４とは、電源用の配線導体２により互いに接続されている。接地用の配線導体２および電源用の配線導体２は、広面積のベタ状パターン１１を有している。ベタ状パターン１１の一部は、信号用の配線導体２の左右および上下に配置されている。このベタ状パターン１１は、絶縁層１ａ〜１ｉの表面に形成されている。ベタ状パターン１１は、搭載部２０Ａに対応する領域から絶縁基体１の外周部にかけての広い領域にわたり形成されている。このベタ状パターン１１と接地用または電源用の半導体素子接続パッド３とは、搭載部２０Ａの直下において、ビアホール導体９を介して接続されている。また、このベタ状パターン１１と接地用または電源用の外部接続パッド４とは、絶縁基体１の中央部から外周部にかけた領域において、スルーホール導体６およびビアホール導体９を介して接続されている。   The semiconductor element connection pad 3 for grounding and the external connection pad 4 for grounding are connected to each other by a wiring conductor 2 for grounding. The semiconductor element connection pad 3 for power supply and the external connection pad 4 for power supply are connected to each other by a wiring conductor 2 for power supply. The grounding wiring conductor 2 and the power supply wiring conductor 2 have a solid pattern 11 having a large area. Part of the solid pattern 11 is disposed on the left and right and top and bottom of the signal wiring conductor 2. The solid pattern 11 is formed on the surfaces of the insulating layers 1a to 1i. The solid pattern 11 is formed over a wide region from the region corresponding to the mounting portion 20 </ b> A to the outer peripheral portion of the insulating base 1. The solid pattern 11 and the grounding or power supply semiconductor element connection pad 3 are connected via a via-hole conductor 9 immediately below the mounting portion 20A. Further, the solid pattern 11 and the external connection pad 4 for grounding or power supply are connected via a through-hole conductor 6 and a via-hole conductor 9 in a region extending from the central portion to the outer peripheral portion of the insulating substrate 1. .

さらに、本例の配線基板２０においては、最上層の絶縁層１ａに、ベタ状パターン１１を底面とする溝１２が搭載部２０Ａに近接して形成されている。この溝１２は、図２に示すように、搭載部２０Ａを囲繞する枠状に形成されている。溝１２は、幅が０．２〜１ｍｍ程度、深さが５〜２０μｍ程度である。この溝１２は、最上層の絶縁層１ａにレーザ加工を施すことによって形成される。溝１２を形成する際に、絶縁層１ａの下のベタ状パターン１１がレーザ加工に対するストッパー層として機能することにより、絶縁層１ａの厚みに対応した一定深さの溝１２が形成される。また、レーザ加工により溝１２の底面を形成するベタ状パターン１１の表面が溶融して算術平均粗さで１００ｎｍ以下の平滑な面となる。   Furthermore, in the wiring board 20 of this example, the groove 12 having the solid pattern 11 as the bottom surface is formed in the uppermost insulating layer 1a in the vicinity of the mounting portion 20A. As shown in FIG. 2, the groove 12 is formed in a frame shape surrounding the mounting portion 20A. The groove 12 has a width of about 0.2 to 1 mm and a depth of about 5 to 20 μm. The groove 12 is formed by performing laser processing on the uppermost insulating layer 1a. When the groove 12 is formed, the solid pattern 11 under the insulating layer 1a functions as a stopper layer for laser processing, so that the groove 12 having a constant depth corresponding to the thickness of the insulating layer 1a is formed. Further, the surface of the solid pattern 11 that forms the bottom surface of the groove 12 is melted by laser processing to form a smooth surface with an arithmetic average roughness of 100 nm or less.

そして、本例の配線基板２０においては、図３に示すように、半導体素子Ｓの電極端子Ｔをフリップチップ接続するとともに、半導体素子Ｓと配線基板２０との隙間にアンダーフィルと呼ばれる封止樹脂Ｕを充填することにより、製品としての半導体装置となる。このとき、本例の配線基板２０によれば、最上層の絶縁層１ａに、ベタ状パターン１１を底面とする溝１２が搭載部２０Ａに近接して一定の深さで形成されていることから、溝１２により封止樹脂Ｕの濡れ広がりを良好に防止することが可能な配線基板２０を提供することができる。   In the wiring board 20 of this example, as shown in FIG. 3, the electrode terminals T of the semiconductor element S are flip-chip connected, and a sealing resin called underfill is formed in the gap between the semiconductor element S and the wiring board 20. By filling U, a semiconductor device as a product is obtained. At this time, according to the wiring board 20 of this example, the groove 12 having the solid pattern 11 as the bottom surface is formed in the uppermost insulating layer 1a at a certain depth close to the mounting portion 20A. In addition, the wiring substrate 20 capable of satisfactorily preventing the sealing resin U from spreading by the grooves 12 can be provided.

さらに、溝１２の底面を形成するベタ状パターン１１の算術平均粗さが１００ｎｍ以下の平滑な面であることにより、溝１２底面と封止樹脂Ｕとの濡れ性が良好となる。それにより、溝１２底面において封止樹脂Ｕが良好に濡れ広がって半導体素子Ｓと溝１２との間に封止樹脂Ｕの良好な形状のメニスカスが形成される。その結果、封止樹脂Ｕに印加される応力がメニスカスにおいて良好に分散され、封止樹脂Ｕに剥がれやクラックが発生することが有効に防止される。   Furthermore, the wettability between the bottom surface of the groove 12 and the sealing resin U is improved because the arithmetic average roughness of the solid pattern 11 forming the bottom surface of the groove 12 is a smooth surface of 100 nm or less. As a result, the sealing resin U wets and spreads well on the bottom surface of the groove 12, and a meniscus having a good shape of the sealing resin U is formed between the semiconductor element S and the groove 12. As a result, the stress applied to the sealing resin U is well dispersed in the meniscus, and it is effectively prevented that the sealing resin U is peeled off or cracked.

１・・・・・・・絶縁基体
１ａ〜１ｉ・・・絶縁層
２・・・・・・・配線導体
２ａ〜２ｊ・・・導体層
１１・・・・・・・ベタ状パターン
１２・・・・・・・溝
２０・・・・・・・配線基板
２０Ａ・・・・・・搭載部
Ｓ・・・・・・・半導体素子 DESCRIPTION OF SYMBOLS 1 .... Insulation base | substrate 1a-1i ... Insulation layer 2 ....... Wiring conductor 2a-2j ... Conductor layer 11 ... Solid pattern 12 ... ························· 20 ········································· Semiconductor element

Claims (2)

複数の絶縁層が積層されて成り、上面に半導体素子が搭載される搭載部を有する絶縁基体と、前記各絶縁層の表面に被着された導体層から成る配線導体とを具備して成る配線基板であって、前記搭載部の周囲に、最上層の前記絶縁層で被覆された前記導体層から成るベタ状パターンが配置されているとともに、最上層の前記絶縁層に、前記ベタ状パターンを底面とする溝が前記搭載部に近接して形成されていることを特徴とする配線基板。   A wiring comprising a plurality of insulating layers laminated, an insulating base having a mounting portion on which a semiconductor element is mounted on the upper surface, and a wiring conductor comprising a conductor layer deposited on the surface of each insulating layer A solid pattern comprising the conductor layer covered with the uppermost insulating layer is disposed around the mounting portion, and the solid pattern is disposed on the uppermost insulating layer. A wiring board, wherein a groove serving as a bottom surface is formed close to the mounting portion. 前記溝の底面を形成する前記ベタ状パターンの算術平均粗さが１００ｎｍ以下であることを特徴とする請求項１記載の配線基板。   2. The wiring board according to claim 1, wherein an arithmetic average roughness of the solid pattern forming the bottom surface of the groove is 100 nm or less.
JP2016032240A 2016-02-23 2016-02-23 Wiring board Pending JP2017152484A (en)

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JP2019062064A (en) * 2017-09-26 2019-04-18 カシオ計算機株式会社 Circuit board, electronic apparatus, and manufacturing method of circuit board
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