JP2017120851A - Semiconductor device and manufacturing method for the same - Google Patents

Semiconductor device and manufacturing method for the same Download PDF

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JP2017120851A
JP2017120851A JP2015257332A JP2015257332A JP2017120851A JP 2017120851 A JP2017120851 A JP 2017120851A JP 2015257332 A JP2015257332 A JP 2015257332A JP 2015257332 A JP2015257332 A JP 2015257332A JP 2017120851 A JP2017120851 A JP 2017120851A
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semiconductor layer
semiconductor device
insulating film
layer
semiconductor
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健太郎 江田
Kentaro Eda
健太郎 江田
武 用正
Takeshi Mochimasa
武 用正
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing leak of an electric current into a semiconductor layer from a conductive layer passing through a structure having at least the semiconductor layer, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device comprises a conductive body, an insulation film and an insulation region. The conductive body passes through front and rear surfaces of a structure having at least a semiconductor layer. The insulation film is provided on a side surface of the conductive body. The insulation region is provided on a surface layer of one surface of the structure in the insulation film. The structure has a recessed part on a surface of a position at which the conductive body is provided, and the insulation region is provided in the recessed part.SELECTED DRAWING: Figure 2

Description

本実施形態は、半導体装置および半導体装置の製造方法に関する。   The present embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device.

従来、半導体層を有する構造体の表裏を貫通する電極を備える半導体装置がある。電極は、導電体であるため、側面に絶縁膜が設けられ、半導体層と電気的に絶縁される。しかしながら、かかる半導体装置は、電極の側面に設けられる絶縁膜のうち、半導体層を有する構造体の表層に位置する部分の膜厚が製造工程の過程で他の部分より薄くなって耐電圧特性が劣化し、電極から半導体層へ電流がリークすることがある。   2. Description of the Related Art Conventionally, there is a semiconductor device including an electrode penetrating the front and back of a structure having a semiconductor layer. Since the electrode is a conductor, an insulating film is provided on the side surface and is electrically insulated from the semiconductor layer. However, in such a semiconductor device, the insulating film provided on the side surface of the electrode has a withstand voltage characteristic because the film thickness of the portion located on the surface layer of the structure having the semiconductor layer is thinner than the other portions during the manufacturing process. It may deteriorate and current may leak from the electrode to the semiconductor layer.

特開２０１２−２０９４４０号公報JP 2012-209440 A

一つの実施形態は、少なくとも半導体層を有する構造体を貫通する導電体から半導体層への電流のリークを抑制することができる半導体装置および半導体装置の製造方法を提供することを目的とする。   An object of one embodiment is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress current leakage from a conductor penetrating at least a structure having a semiconductor layer to the semiconductor layer.

実施形態に係る半導体装置は、導電体と、絶縁膜と、絶縁領域とを備える。導電体は、少なくとも半導体層を有する構造体の表裏を貫通する。絶縁膜は、前記導電体の側面に設けられる。絶縁領域は、前記絶縁膜における前記構造体の一表面の表層に設けられる。   The semiconductor device according to the embodiment includes a conductor, an insulating film, and an insulating region. The conductor penetrates at least the front and back of the structure having the semiconductor layer. The insulating film is provided on the side surface of the conductor. The insulating region is provided on a surface layer of one surface of the structure in the insulating film.

実施形態に係る半導体装置を示す説明図。Explanatory drawing which shows the semiconductor device which concerns on embodiment. 実施形態に係る半導体装置の模式的な断面図。1 is a schematic cross-sectional view of a semiconductor device according to an embodiment. 実施形態に係る半導体装置の製造工程を示す説明図。Explanatory drawing which shows the manufacturing process of the semiconductor device which concerns on embodiment. 実施形態に係る半導体装置の製造工程を示す説明図。Explanatory drawing which shows the manufacturing process of the semiconductor device which concerns on embodiment. 実施形態に係る半導体装置の製造工程を示す説明図。Explanatory drawing which shows the manufacturing process of the semiconductor device which concerns on embodiment. 実施形態に係る半導体装置の製造工程を示す説明図。Explanatory drawing which shows the manufacturing process of the semiconductor device which concerns on embodiment.

以下に添付図面を参照して、実施形態に係る半導体装置および半導体装置の製造方法を詳細に説明する。なお、この実施形態により本発明が限定されるものではない。以下では、実施形態に係る半導体装置が、裏面照射型のイメージセンサである場合を例に挙げて説明するが、これは一例である。本実施形態は、少なくとも半導体層を有する構造体の表裏を貫通する導電体を備える任意の半導体装置に対して適用することができる。   Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device will be explained below in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment. Hereinafter, a case where the semiconductor device according to the embodiment is a back-illuminated image sensor will be described as an example, but this is an example. This embodiment can be applied to any semiconductor device including a conductor that penetrates at least the front and back of a structure having a semiconductor layer.

図１は、実施形態に係る半導体装置を示す説明図である。図１に示すように、実施形態に係る半導体装置１は、撮像領域となる画素アレイ２と、画素アレイ２の周囲に設けられ、半導体層を有する構造体の表裏を貫通する複数の導電体（以下、「電極３」と記載する）とを備える。   FIG. 1 is an explanatory diagram illustrating a semiconductor device according to an embodiment. As shown in FIG. 1, a semiconductor device 1 according to an embodiment includes a pixel array 2 that is an imaging region, and a plurality of conductors that are provided around the pixel array 2 and penetrate the front and back of a structure having a semiconductor layer ( Hereinafter, it is described as “electrode 3”.

画素アレイ２は、撮像画像の各画素に対応して行列状に設けられる複数の光電変換素子を備える。光電変換素子は、入射光を光電変換し、各画素の輝度を示す画素信号として出力する。電極３は、所謂ＴＳＶ（Through Silicon Via）であり、例えば、画素アレイ２からＩＳＰ(Image Signal Processor)への信号電荷の転送などに使用される。   The pixel array 2 includes a plurality of photoelectric conversion elements provided in a matrix corresponding to each pixel of the captured image. The photoelectric conversion element photoelectrically converts incident light and outputs a pixel signal indicating the luminance of each pixel. The electrode 3 is a so-called TSV (Through Silicon Via), and is used, for example, for signal charge transfer from the pixel array 2 to an ISP (Image Signal Processor).

本実施形態では、かかる電極３近傍の構造を改良することによって半導体装置１の耐電圧特性を向上させ、電極３から半導体層への電流のリークを抑制する。次に、図２を参照して、半導体装置１における電極３近傍の構造について説明する。図２は、実施形態に係る半導体装置１の模式的な断面図である。なお、図２には、半導体装置１における電極３近傍部分の模式的な断面を選択的に示している。   In the present embodiment, the withstand voltage characteristic of the semiconductor device 1 is improved by improving the structure in the vicinity of the electrode 3, and current leakage from the electrode 3 to the semiconductor layer is suppressed. Next, the structure in the vicinity of the electrode 3 in the semiconductor device 1 will be described with reference to FIG. FIG. 2 is a schematic cross-sectional view of the semiconductor device 1 according to the embodiment. FIG. 2 selectively shows a schematic cross section of the vicinity of the electrode 3 in the semiconductor device 1.

図２に示すように、半導体装置１は、順次積層される層間絶縁膜４、半導体層５、保護膜６、およびハードマスク７を備える。層間絶縁膜４は、例えば、ＴＥＯＳ（テトラエトキシシラン）を材料として使用して成膜される酸化シリコン層である。   As shown in FIG. 2, the semiconductor device 1 includes an interlayer insulating film 4, a semiconductor layer 5, a protective film 6, and a hard mask 7 that are sequentially stacked. The interlayer insulating film 4 is a silicon oxide layer formed using, for example, TEOS (tetraethoxysilane) as a material.

半導体層５は、例えば、Ｐ型またはＮ型の不純物がドープされたシリコン層、もしくは、ノンドープのシリコン層である。保護膜６は、例えば、窒化シリコン膜である。ハードマスク７は、例えば、シラン化合物である。   The semiconductor layer 5 is, for example, a silicon layer doped with P-type or N-type impurities, or a non-doped silicon layer. The protective film 6 is, for example, a silicon nitride film. The hard mask 7 is, for example, a silane compound.

また、層間絶縁膜４は、内部に、例えば、画素アレイ２から信号電荷を読み出す読出トランジスタのゲート８や、多層配線（図示略）などが設けられる。ゲート８は、例えば、ポリシリコンによって形成される。   In addition, the interlayer insulating film 4 is provided with, for example, a gate 8 of a read transistor that reads out signal charges from the pixel array 2, a multilayer wiring (not shown), and the like. The gate 8 is made of polysilicon, for example.

半導体層５、保護膜６、およびハードマスク７を含む構造体は、内部に、かかる構造体の表裏を貫通する電極３が設けられる。なお、図２に示す電極３が設けられる構造体は一例であり、少なくとも半導体層５を有するものであれば、保護膜６およびハードマスク７以外の構成要素となる層や薄膜を備えるものであってもよい。   The structure including the semiconductor layer 5, the protective film 6, and the hard mask 7 is provided with electrodes 3 that penetrate the front and back of the structure. The structure provided with the electrode 3 shown in FIG. 2 is an example, and if it has at least the semiconductor layer 5, it includes a layer or a thin film that is a constituent element other than the protective film 6 and the hard mask 7. May be.

電極３は、例えば、銅などの導電性部材によって形成されるＴＳＶであり、ここでは、下端がゲート８に接続され、上端にボンディングパッド１２が設けられる。ボンディングパッド１２は、例えば、アルミニウムなどの金属によって形成され、金線などのボンディングワイヤによって、例えば、ＩＳＰなどの周辺回路と接続される。   The electrode 3 is a TSV formed of, for example, a conductive member such as copper. Here, the lower end is connected to the gate 8 and the bonding pad 12 is provided at the upper end. The bonding pad 12 is formed of, for example, a metal such as aluminum, and is connected to a peripheral circuit such as an ISP by a bonding wire such as a gold wire.

また、電極３は、側面に絶縁膜１０が設けられる。絶縁膜１０は、例えば、窒化シリコン膜であり、電極３と半導体層５とを電気的に絶縁する。なお、半導体層５は、ゲート８に当接する位置に、ＳＴＩ（Shallow Trench Isolation）９が設けられる。ＳＴＩ９は、半導体層５に形成されるトレンチ内に、酸化シリコンが埋め込まれた領域であり、半導体層５とゲート８とを電気的に絶縁する。   The electrode 3 is provided with an insulating film 10 on the side surface. The insulating film 10 is, for example, a silicon nitride film, and electrically insulates the electrode 3 from the semiconductor layer 5. The semiconductor layer 5 is provided with an STI (Shallow Trench Isolation) 9 at a position in contact with the gate 8. The STI 9 is a region where silicon oxide is embedded in a trench formed in the semiconductor layer 5, and electrically insulates the semiconductor layer 5 and the gate 8.

ここで、絶縁膜１０は、図２に示すように、製造工程の過程で半導体層の表層に位置する部分の膜厚ｄ１が、深層部に位置する部分の膜厚より薄くなる場合がある。なお、絶縁膜１０の膜厚が薄くなる製造工程の詳細については後述する。   Here, as shown in FIG. 2, in the insulating film 10, the film thickness d <b> 1 of the portion located in the surface layer of the semiconductor layer may be thinner than the thickness of the portion located in the deep layer portion in the course of the manufacturing process. The details of the manufacturing process for reducing the thickness of the insulating film 10 will be described later.

かかる場合、絶縁膜１０は、半導体層５の表層に位置する部分の耐圧特性が劣化する。これにより、絶縁膜１０だけでは、電極３と半導体層５との間を十分に絶縁することが困難となる。   In such a case, the insulating film 10 deteriorates the breakdown voltage characteristics of the portion located in the surface layer of the semiconductor layer 5. Accordingly, it is difficult to sufficiently insulate between the electrode 3 and the semiconductor layer 5 with the insulating film 10 alone.

そこで、半導体装置１は、絶縁膜１０における半導体層５側の表面のうち、半導体層５の表層に位置する表面に設けられる絶縁領域１１を備える。絶縁領域１１は、例えば、酸化シリコンによって形成され、電極３の側面を被覆する絶縁膜１０の半導体層５における表層部分のさらに外周を囲む。   Therefore, the semiconductor device 1 includes the insulating region 11 provided on the surface of the insulating film 10 on the surface of the semiconductor layer 5 among the surfaces on the semiconductor layer 5 side. The insulating region 11 is formed of, for example, silicon oxide and surrounds the outer periphery of the surface layer portion of the semiconductor layer 5 of the insulating film 10 that covers the side surface of the electrode 3.

これにより、半導体装置１は、半導体層５の表層部分における電極３から半導体層５までの距離ｄ２が、絶縁膜１０の薄くなった部分の膜厚ｄ１よりも長くなる。なお、ここでの距離は、半導体層５の深さ方向を法線とする面の面方向の距離である。   Thereby, in the semiconductor device 1, the distance d <b> 2 from the electrode 3 to the semiconductor layer 5 in the surface layer portion of the semiconductor layer 5 is longer than the film thickness d <b> 1 of the thinned portion of the insulating film 10. Here, the distance is a distance in a plane direction of a plane whose normal is the depth direction of the semiconductor layer 5.

かかる半導体装置１によれば、製造工程の過程で半導体層５の表層に位置する部分の膜厚ｄ１が、深層に位置する部分の膜厚より薄くなったとしても、絶縁膜１０と絶縁領域１１とによって、電極３と半導体層５との間を十分に絶縁することがでる。したがって、半導体装置１は、半導体層５を有する構造体の表裏を貫通する電極３から半導体層５への電流のリークを抑制することができる。   According to the semiconductor device 1, the insulating film 10 and the insulating region 11 are provided even if the thickness d1 of the portion located in the surface layer of the semiconductor layer 5 becomes thinner than the thickness located in the deep layer during the manufacturing process. Thus, the electrode 3 and the semiconductor layer 5 can be sufficiently insulated. Therefore, the semiconductor device 1 can suppress current leakage from the electrode 3 penetrating the front and back of the structure including the semiconductor layer 5 to the semiconductor layer 5.

また、図２に示すように、半導体層５は、電極３が設けられる位置の表面に、凹部を備える。そして、絶縁領域１１は、かかる半導体層５の凹部に設けられ、絶縁膜１０と半導体層５との間を隙間なく埋める。これにより、絶縁領域１１は、半導体層５の表層部分における電極３と半導体層５との間をより確実に絶縁することができる。   As shown in FIG. 2, the semiconductor layer 5 includes a recess on the surface where the electrode 3 is provided. The insulating region 11 is provided in the recess of the semiconductor layer 5 and fills the space between the insulating film 10 and the semiconductor layer 5 without a gap. Thereby, the insulating region 11 can more reliably insulate between the electrode 3 and the semiconductor layer 5 in the surface layer portion of the semiconductor layer 5.

また、絶縁領域１１は、絶縁膜１０側の側面が半導体層５の表面側から半導体層５の内部側へ向かって下り勾配に傾斜し、半導体層５側の側面が半導体層５の深さ方向と平行である。かかる形状の絶縁領域１１は、例えば、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）のゲート側面に絶縁膜のサイドウォールスペーサを形成する工程を流用することができるので、煩雑な製造工程を追加することなく形成が可能である。   The insulating region 11 has a side surface on the insulating film 10 side inclined from the surface side of the semiconductor layer 5 toward the inner side of the semiconductor layer 5, and a side surface on the semiconductor layer 5 side in the depth direction of the semiconductor layer 5. And parallel. For example, the insulating region 11 having such a shape can utilize a process of forming a sidewall spacer of an insulating film on a gate side surface of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) without adding a complicated manufacturing process. Formation is possible.

また、絶縁領域１１は、窒化シリコンよりも比誘電率が小さな酸化シリコンによって形成される。これにより、絶縁領域１１は、窒化シリコンによって形成される場合に比べて、隣接する電極３間の寄生容量を低く抑えることができる。   The insulating region 11 is formed of silicon oxide having a relative dielectric constant smaller than that of silicon nitride. Thereby, the insulating region 11 can suppress the parasitic capacitance between the adjacent electrodes 3 to be lower than that in the case where the insulating region 11 is formed of silicon nitride.

次に、図３〜図６を参照して、半導体装置１の製造方法について説明する。図３〜図６は、実施形態に係る半導体装置１の製造工程を示す説明図である。ここでは、半導体装置１の製造工程のうち、図２に示す電極３近傍の構造を形成する工程について詳述し、その他の製造工程については、簡単に説明する。   Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. 3-6 is explanatory drawing which shows the manufacturing process of the semiconductor device 1 which concerns on embodiment. Here, of the manufacturing steps of the semiconductor device 1, the step of forming the structure near the electrode 3 shown in FIG. 2 will be described in detail, and the other manufacturing steps will be briefly described.

半導体装置１を製造する場合には、まず、シリコン基板などの半導体基板を用意し、半導体基板における画素アレイ２（図１参照）の形成領域に複数の光電変換素子を形成する。さらに、半導体基板に、読み出しトランジスタのソースおよびドレインなどといった半導体素子用の不純物拡散領域を形成する。   When manufacturing the semiconductor device 1, first, a semiconductor substrate such as a silicon substrate is prepared, and a plurality of photoelectric conversion elements are formed in the formation region of the pixel array 2 (see FIG. 1) on the semiconductor substrate. Further, impurity diffusion regions for semiconductor elements such as the source and drain of the reading transistor are formed in the semiconductor substrate.

その後、半導体基板における表側表層の素子分離や絶縁が必要とされる位置に、適宜ＳＴＩ９（図２参照）を形成する。続いて、半導体基板の表側にトランジスタなどの半導体素子や多層配線を形成した後、半導体基板を裏側から研削および研磨して、半導体基板の裏面側に光電変換素子の受光面を形成する。これにより、半導体基板は、薄化されて半導体層５（図２参照）となる。   Thereafter, STI 9 (see FIG. 2) is appropriately formed at a position where element isolation or insulation on the front surface layer is required on the semiconductor substrate. Subsequently, after forming a semiconductor element such as a transistor or a multilayer wiring on the front side of the semiconductor substrate, the semiconductor substrate is ground and polished from the back side to form a light receiving surface of the photoelectric conversion element on the back side of the semiconductor substrate. Thus, the semiconductor substrate is thinned to become the semiconductor layer 5 (see FIG. 2).

その後、半導体層５の裏面に保護膜６およびハードマスク７（図２参照）を順次積層した後、ハードマスク７に所定のパターニングを施してエッチングを行う。これにより、半導体層５裏面の電極３（図２参照）が形成される位置から保護膜６を除去して、図３に（ａ）で示す構造体を形成する。このため、図３に（ａ）で示す構造体では、半導体層５の下面が表面となり、半導体層５の上面が裏面となる。   Thereafter, a protective film 6 and a hard mask 7 (see FIG. 2) are sequentially stacked on the back surface of the semiconductor layer 5, and then the hard mask 7 is subjected to predetermined patterning and etching. Thereby, the protective film 6 is removed from the position where the electrode 3 (see FIG. 2) on the back surface of the semiconductor layer 5 is formed, and the structure shown in FIG. 3A is formed. Therefore, in the structure shown in FIG. 3A, the lower surface of the semiconductor layer 5 is the front surface, and the upper surface of the semiconductor layer 5 is the back surface.

続いて、図３に（ｂ）で示すように、ハードマスク７をマスクとして使用し、例えば、ＲＩＥ（Reactive Ion Etching）などのエッチングを行うことにより、半導体層５の裏面側の表面に、平面視円形状または矩形状の凹部２１を形成する。   Subsequently, as shown in FIG. 3B, by using the hard mask 7 as a mask and performing etching such as RIE (Reactive Ion Etching), the surface on the back surface side of the semiconductor layer 5 is planarized. A concave portion 21 having a circular shape or a rectangular shape is formed.

ここでは、最終的に形成する電極３（図２参照）の半導体層５内部を貫通する部分の幅よりも幅が大きく、半導体層５の表面から表層まで達する深さの凹部２１を形成する。なお、凹部２１の平面視形状は、平面視円形状または矩形状に限定されるものではなく、例えば、スリット状であってもよい。   Here, a recess 21 having a width larger than the width of the portion of the electrode 3 (see FIG. 2) to be finally formed penetrating through the semiconductor layer 5 and reaching the surface layer from the surface of the semiconductor layer 5 is formed. In addition, the planar view shape of the recessed part 21 is not limited to a planar view circular shape or a rectangular shape, For example, a slit shape may be sufficient.

そして、図３に（ｃ）で示すように、凹部２１およびハードマスク７の表面に、例えば、ＣＶＤ（Chemical Vapor Deposition）によって、酸化シリコン膜１３を形成する。その後、図４に（ａ）で示すように、例えば、ＲＩＥによるエッチバックを行うことによって、凹部２１底面上およびハードマスク７上の酸化シリコン膜１３を除去し、凹部２１側面に酸化シリコン膜１３を残すことによって、絶縁領域１１を形成する。   Then, as shown in FIG. 3C, the silicon oxide film 13 is formed on the surface of the recess 21 and the hard mask 7 by, for example, CVD (Chemical Vapor Deposition). 4A, the silicon oxide film 13 on the bottom surface of the recess 21 and on the hard mask 7 is removed by performing etch back by RIE, for example, and the silicon oxide film 13 on the side surface of the recess 21 is removed. The insulating region 11 is formed by leaving

これにより、絶縁領域１１は、露出している部分の側面が半導体層５のハードマスク７の表面側から半導体層５の内部側へ向かって下り勾配に傾斜し、ハードマスク７および半導体層５に接触する側の側面が半導体層５の深さ方向と平行となる。   As a result, the insulating region 11 has a side surface of the exposed portion inclined downwardly from the surface side of the hard mask 7 of the semiconductor layer 5 toward the inner side of the semiconductor layer 5. The side surface on the contact side is parallel to the depth direction of the semiconductor layer 5.

このように、絶縁領域１１は、例えば、ＭＯＳＦＥＴのゲート側面に絶縁膜のサイドウォールスペーサを形成する工程と同様の工程を流用して形成が可能なので、煩雑な製造工程を追加することなく形成が可能である。   As described above, the insulating region 11 can be formed by diverting a process similar to the process of forming the sidewall spacer of the insulating film on the gate side surface of the MOSFET, for example, and thus can be formed without adding a complicated manufacturing process. Is possible.

続いて、図４に（ｂ）で示すように、例えば、ＲＩＥによる異方性エッチングを行うことによって、凹部２１の底面から半導体層５の他方の表面（ここでは、ＳＴＩ９の上面）まで達する平面視円形状または矩形状の開口２２を形成する。   Subsequently, as shown in FIG. 4B, for example, a plane reaching from the bottom surface of the recess 21 to the other surface of the semiconductor layer 5 (here, the top surface of the STI 9) by performing anisotropic etching by RIE. A circular or rectangular opening 22 is formed.

このときのＲＩＥによって、ハードマスク７は、膜厚が多少薄くなる。なお、開口２２の平面視形状は、円形状または矩形状に限定されるものではなく、例えば、スリット状であってもよい。   By RIE at this time, the film thickness of the hard mask 7 becomes somewhat thin. In addition, the planar view shape of the opening 22 is not limited to a circular shape or a rectangular shape, and may be a slit shape, for example.

続いて、図４に（ｃ）で示すように、開口２２の内周面、絶縁領域１１およびハードマスク７の表面に、窒化シリコン膜を形成することによって絶縁膜１０を形成する。その後、図５に（ａ）で示すように、例えばＲＩＥによって、開口２２の底面上の絶縁膜１０を除去する。   Subsequently, as shown in FIG. 4C, the insulating film 10 is formed by forming a silicon nitride film on the inner peripheral surface of the opening 22, the insulating region 11, and the surface of the hard mask 7. Thereafter, as shown in FIG. 5A, the insulating film 10 on the bottom surface of the opening 22 is removed by, for example, RIE.

続いて、図５に（ｂ）で示すように、ＳＴＩ９の表面が露出した部分に対してＲＩＥを行い、その後、ウェットエッチングを行うことによって、ゲート８の表面を露出させる。これにより、ＲＩＥによるゲート８の表面荒れをウェットエッチングによって回復することができる。このときのＲＩＥによって、絶縁膜１０のうち、半導体層５の表層に位置する部分の膜厚が他の部分よりも薄くなる。   Subsequently, as shown in FIG. 5B, RIE is performed on the portion where the surface of the STI 9 is exposed, and then wet etching is performed to expose the surface of the gate 8. Thereby, the surface roughness of the gate 8 caused by RIE can be recovered by wet etching. By RIE at this time, the film thickness of the part located in the surface layer of the semiconductor layer 5 among the insulating films 10 becomes thinner than other parts.

続いて、図５に（ｃ）で示すように、スパッタリングまたは電界めっきによって、絶縁膜１０によって囲まれる開口２２内の空間、および絶縁膜１０上に、例えば、銅などの導電部材１４を積層する。その後、図６に（ａ）で示すように、例えば、ウェットエッチングを行い、絶縁膜１０上の導電部材１４を除去することによって電極３を形成する。   Subsequently, as shown in FIG. 5C, a conductive member 14 such as copper is laminated on the space in the opening 22 surrounded by the insulating film 10 and the insulating film 10 by sputtering or electroplating. . Thereafter, as shown in FIG. 6A, for example, wet etching is performed, and the conductive member 14 on the insulating film 10 is removed to form the electrode 3.

ここで、半導体層５の表層では、絶縁膜１０の膜厚が他の部分よりも薄くなっているが、電極３と半導体層５との間には、薄くなった絶縁膜１０だけでなく、絶縁領域１１が介在するので、電極３から半導体層５への電流のリークを抑制することができる。   Here, in the surface layer of the semiconductor layer 5, the thickness of the insulating film 10 is thinner than other portions, but not only the thinned insulating film 10 between the electrode 3 and the semiconductor layer 5, Since the insulating region 11 is interposed, current leakage from the electrode 3 to the semiconductor layer 5 can be suppressed.

続いて、図６に（ｂ）で示すように、例えば、ＣＭＰ（Chemical Mechanical Polishing）によって、ハードマスク７上の絶縁膜１０を除去し、その後、図６に（ｃ）で示すように、ハードマスク７および電極３上に、例えば、アルミニウムなどの導電部材１５を積層する。最後に、導電部材１５のうち、電極３上の部分を除く不要な部分の導電部材１５を除去することによってボンディングパッド１２を形成して、図２に示す半導体装置１が完成する。   Subsequently, as shown in FIG. 6B, the insulating film 10 on the hard mask 7 is removed by, for example, CMP (Chemical Mechanical Polishing), and then, as shown in FIG. A conductive member 15 such as aluminum is laminated on the mask 7 and the electrode 3. Finally, unnecessary portions of the conductive member 15 except for the portions on the electrodes 3 are removed to form the bonding pads 12, thereby completing the semiconductor device 1 shown in FIG.

上述したように、実施形態に係る半導体装置は、少なくとも半導体層を有する構造体の表裏を貫通する導電体の側面に設けられる絶縁膜を備え、絶縁膜における構造体の一表面の表層に設けられる絶縁領域を備える。   As described above, the semiconductor device according to the embodiment includes the insulating film provided on the side surface of the conductor penetrating at least the front and back of the structure including the semiconductor layer, and is provided on the surface layer of one surface of the structure in the insulating film. Insulating region is provided.

これにより、半導体装置は、製造工程の過程で、半導体層を有する構造体の表層に位置する絶縁膜の膜厚が他の部分よりも薄くなっても、半導体層を有する構造体の表層部分では、導電体と半導体層との間に、絶縁膜だけでなく絶縁領域が介在する。したがって、半導体装置は、導電体から半導体層への電流のリークを抑制することができる。   Accordingly, in the semiconductor device, the surface layer portion of the structure including the semiconductor layer is not formed even when the thickness of the insulating film located on the surface layer of the structure including the semiconductor layer is thinner than the other portion during the manufacturing process. In addition to the insulating film, an insulating region is interposed between the conductor and the semiconductor layer. Therefore, the semiconductor device can suppress current leakage from the conductor to the semiconductor layer.

なお、上述した実施形態では、一つのボンディングパッドに対して、一つの電極が接続される場合を例に挙げたが、これは一例であり、一つのボンディングパッドに対して、半導体層内に併設される複数の電極が接続される構成であってもよい。   In the above-described embodiment, the case where one electrode is connected to one bonding pad is described as an example. However, this is an example, and one bonding pad is provided in the semiconductor layer. The structure by which a plurality of electrodes to be connected may be connected.

これにより、仮に、いくつかの電極が断線したとしても、断線していない他の電極によって、半導体層の表裏を導通させることができる。また、一つのボンディングパッドに複数本の電極を接続することにより、半導体層の表裏を導通させる配線抵抗を低減することができる。   Thereby, even if some electrodes are disconnected, the front and back of the semiconductor layer can be made conductive by other electrodes that are not disconnected. Further, by connecting a plurality of electrodes to one bonding pad, it is possible to reduce the wiring resistance for conducting the front and back of the semiconductor layer.

なお、実施形態に係る半導体装置の各構成要素の材料は、上記したものに限定されるものではない。例えば、電極やボンディングパッド等の導電体の材料は、金、白金、アルミニウム、タングステンなどの導電部材、または、これらのうち、少なくとも一つを含む部材であってもよい。絶縁膜の材料は、酸化シリコンであってもよい。絶縁領域の材料は、窒化シリコンであってもよい。   In addition, the material of each component of the semiconductor device according to the embodiment is not limited to the above. For example, the material of the conductor such as an electrode or a bonding pad may be a conductive member such as gold, platinum, aluminum, tungsten, or a member including at least one of them. The material of the insulating film may be silicon oxide. The material of the insulating region may be silicon nitride.

本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

１ 半導体装置、 ２ 画素アレイ、 ３ 電極、 ４ 層間絶縁膜、 ５ 半導体層、 ６ 保護膜、 ７ ハードマスク、 ８ ゲート、 １０ 絶縁膜、 １１ 絶縁領域、 １２ ボンディングパッド、 １３ 酸化シリコン膜、 １４，１５ 導電部材、 ２１ 凹部、 ２２ 開口。   DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Pixel array, 3 Electrode, 4 Interlayer insulating film, 5 Semiconductor layer, 6 Protective film, 7 Hard mask, 8 Gate, 10 Insulating film, 11 Insulating region, 12 Bonding pad, 13 Silicon oxide film, 14, 15 conductive members, 21 recesses, 22 openings.

Claims (5)

少なくとも半導体層を有する構造体の表裏を貫通する導電体と、
前記導電体の側面に設けられる絶縁膜と、
前記絶縁膜における前記構造体の一表面の表層に設けられる絶縁領域と
を備えることを特徴とする半導体装置。 A conductor penetrating the front and back of the structure having at least a semiconductor layer;
An insulating film provided on a side surface of the conductor;
An insulating region provided on a surface layer of one surface of the structure in the insulating film. 前記構造体は、
前記導電体が設けられる位置の前記一表面に凹部を有し、
前記絶縁領域は、
前記凹部に設けられる
ことを特徴とする請求項１に記載の半導体装置。 The structure is
Having a recess on the one surface where the conductor is provided;
The insulating region is
The semiconductor device according to claim 1, wherein the semiconductor device is provided in the recess. 前記絶縁領域は、
前記絶縁膜側の側面が前記構造体の前記一表面側から前記構造体の内部側へ向かって下り勾配に傾斜し、前記構造体側の側面が前記構造体の深さ方向と平行である
ことを特徴とする請求項１または請求項２に記載の半導体装置。 The insulating region is
The side surface on the insulating film side is inclined downwardly from the one surface side of the structure toward the inner side of the structure, and the side surface on the structure side is parallel to the depth direction of the structure. 3. The semiconductor device according to claim 1, wherein the semiconductor device is characterized. 前記絶縁領域は、
酸化シリコンによって形成される
ことを特徴とする請求項１〜３のいずれか一つに記載の半導体装置。 The insulating region is
The semiconductor device according to claim 1, wherein the semiconductor device is formed of silicon oxide. 少なくとも半導体層を有する構造体の一方の表面に凹部を形成することと、
前記凹部の側面に絶縁領域を形成することと、
前記凹部の底面から前記構造体の他方の表面まで達する開口を形成することと、
前記絶縁領域および前記開口の側面に絶縁膜を形成することと、
前記絶縁膜によって囲まれる空間に導電体を形成することと
を含むことを特徴とする半導体装置の製造方法。 Forming a recess on one surface of a structure having at least a semiconductor layer;
Forming an insulating region on a side surface of the recess;
Forming an opening reaching from the bottom surface of the recess to the other surface of the structure;
Forming an insulating film on a side surface of the insulating region and the opening;
Forming a conductor in a space surrounded by the insulating film. A method for manufacturing a semiconductor device, comprising:
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JP2022109893A (en) * 2021-01-15 2022-07-28 台湾積體電路製造股▲ふん▼有限公司 Image sensor and manufacturing method thereof
EP3876265A4 (en) * 2018-10-31 2022-08-24 Hamamatsu Photonics K.K. Damascene interconnect structure, actuator device, and method of manufacturing damascene interconnect structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3876265A4 (en) * 2018-10-31 2022-08-24 Hamamatsu Photonics K.K. Damascene interconnect structure, actuator device, and method of manufacturing damascene interconnect structure
EP4235775A3 (en) * 2018-10-31 2023-11-08 Hamamatsu Photonics K.K. Damascene interconnect structure, actuator device, and method of manufacturing damascene interconnect structure
US11987493B2 (en) 2018-10-31 2024-05-21 Hamamatsu Photonics K.K. Damascene interconnect structure, actuator device, and method of manufacturing damascene interconnect structure
JP2022109893A (en) * 2021-01-15 2022-07-28 台湾積體電路製造股▲ふん▼有限公司 Image sensor and manufacturing method thereof
JP7350106B2 (en) 2021-01-15 2023-09-25 台湾積體電路製造股▲ふん▼有限公司 Image sensor and its manufacturing method
US11908878B2 (en) 2021-01-15 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Image sensor and manufacturing method thereof

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