JP2017107898A - Semiconductor device - Google Patents
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Abstract
Description
本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.
従来、半導体装置は、例えば、特許文献１に記載されているように、外部リードと接続されるような比較的厚い厚さで形成されたボンディングパッドと、内部回路に伝えられる電源電圧と接地電位を伝達する電源幹線とを、基板の同一面側に構成し、かかる電源幹線の下層に上記電源幹線と対応する上記内部回路を構成する半導体領域との間を接続する銅配線層からなる複数の配線層を、高密度で配置してあった。 2. Description of the Related Art Conventionally, as described in Patent Document 1, for example, a semiconductor device has a bonding pad formed with a relatively thick thickness that is connected to an external lead, a power supply voltage transmitted to an internal circuit, and a ground potential. A plurality of copper wiring layers that are formed on the same surface side of the substrate, and are connected to the lower layer of the power supply trunk line between the power supply trunk line and the corresponding semiconductor region constituting the internal circuit. The wiring layer was arranged with high density.
ところで、電気自動車（ＥＶ）用電源、太陽光発電用パワーコンディショナ、通信基地局などの情報通信機器電源または産業用電源等に用いられる制御用パワー半導体装置においては、特許文献１等で取り扱っている信号処理系半導体装置と比較して、扱う電力が極めて大きくなるために、電源供給線の断面積を大きくして、その発熱量を低減させなければならない。 By the way, the power semiconductor device for control used for the power source for electric vehicles (EV), the power conditioner for photovoltaic power generation, the power source of information communication equipment such as a communication base station, or the industrial power source is dealt with in Patent Document 1 and the like. Compared with a conventional signal processing semiconductor device, since the power to be handled becomes extremely large, the cross-sectional area of the power supply line must be increased to reduce the heat generation amount.
ところが、従来の半導体装置は、特許文献１で代表されるように、電源幹線、半導体領域及び配線層等を、基板の同一面側の限定された平面積内に高密度で配置する必要があったため、電源幹線（電源供給線）の断面積を拡大することが、物理的に困難である。 However, as represented by Patent Document 1, in the conventional semiconductor device, it is necessary to arrange the power supply trunk line, the semiconductor region, the wiring layer, and the like at a high density within a limited plane area on the same surface side of the substrate. Therefore, it is physically difficult to increase the cross-sectional area of the power trunk line (power supply line).
本発明の課題は、平面積増大を抑制しつつ、電源供給線の断面積を増大させ、発熱を抑制した半導体装置を提供することである。 An object of the present invention is to provide a semiconductor device in which heat generation is suppressed by increasing a cross-sectional area of a power supply line while suppressing an increase in a flat area.
上述した課題を解決するため、本発明に係る半導体装置は、半導体基板と、半導体回路部と、電源供給導体と、縦導体とを含む。前記半導体回路部は、半導体素子部及びその配線部を含む。前記半導体素子部及び前記配線部は前記半導体基板の一面側に設けられている。 In order to solve the above-described problems, a semiconductor device according to the present invention includes a semiconductor substrate, a semiconductor circuit unit, a power supply conductor, and a vertical conductor. The semiconductor circuit portion includes a semiconductor element portion and a wiring portion thereof. The semiconductor element portion and the wiring portion are provided on one surface side of the semiconductor substrate.
前記電源供給導体は、前記半導体基板の他面に設けられている。前記縦導体は、前記半導体基板の前記一面側から他面側に導かれ、前記半導体素子部及び前記配線部と前記電源供給導体とを電気接続する。 The power supply conductor is provided on the other surface of the semiconductor substrate. The vertical conductor is led from the one surface side to the other surface side of the semiconductor substrate, and electrically connects the semiconductor element portion and the wiring portion to the power supply conductor.
上述したように、本発明に係る半導体装置では、半導体回路部を構成する半導体素子部及び配線部が、前記半導体基板の一面側に設けられている。一方、前記電源供給導体は、前記半導体基板の他面に設けられている。この構成によれば、半導体基板の一面側では、半導体回路部の配置密度を上げる一方、半導体基板の他面側では、半導体回路部による影響を受けることなく、電源供給線の断面積を増大させ、発熱を抑制し得る。すなわち、半導体基板の両面を有効に活用し、基板平面積の増大を抑制しつつ、電源供給線の断面積を増大させ、発熱を抑制し得る。電源供給導体は、その断面積が、配線部の断面積よりも大きい。 As described above, in the semiconductor device according to the present invention, the semiconductor element portion and the wiring portion constituting the semiconductor circuit portion are provided on one surface side of the semiconductor substrate. On the other hand, the power supply conductor is provided on the other surface of the semiconductor substrate. According to this configuration, the arrangement density of the semiconductor circuit portion is increased on one surface side of the semiconductor substrate, while the cross-sectional area of the power supply line is increased on the other surface side of the semiconductor substrate without being affected by the semiconductor circuit portion. , Can suppress fever. That is, it is possible to effectively use both surfaces of the semiconductor substrate and increase the cross-sectional area of the power supply line while suppressing an increase in the substrate plane area, thereby suppressing heat generation. The cross-sectional area of the power supply conductor is larger than the cross-sectional area of the wiring part.
しかも、電源供給導体は、半導体回路部のある半導体基板の一面側とは反対側の他面に設けられているから、半導体回路部による制限を受けることなく、電源供給導体に対してヒートシンクを熱結合させ、放熱性を向上させることができる。 In addition, since the power supply conductor is provided on the other surface opposite to the one surface side of the semiconductor substrate having the semiconductor circuit portion, the heat sink heats up the power supply conductor without being restricted by the semiconductor circuit portion. It can combine and can improve heat dissipation.
また、本発明に係る半導体装置は、縦導体を含んでおり、縦導体は、半導体基板の一面側から他面側に導かれ、半導体素子部及び配線部と電源供給導体とを電気接続する。この構造によれば、電源供給線及び縦導体を経由して、半導体回路部に電力を供給することができる。 The semiconductor device according to the present invention includes a vertical conductor, and the vertical conductor is guided from one surface side of the semiconductor substrate to the other surface side to electrically connect the semiconductor element portion and the wiring portion to the power supply conductor. According to this structure, power can be supplied to the semiconductor circuit unit via the power supply line and the vertical conductor.
電源供給導体は、半導体基板の他面に設けられた凹部内に半導体基板から電気絶縁して設けられていることが好ましい。この構造によれば、半導体基板の他面側では、電源供給導体の断面積を、凹部の深さ、横幅及び縦幅に応じて拡大すると共に、半導体基板の一面側の全面を、半導体回路部形成のために供することができる。 The power supply conductor is preferably provided in a recess provided on the other surface of the semiconductor substrate and electrically insulated from the semiconductor substrate. According to this structure, on the other surface side of the semiconductor substrate, the cross-sectional area of the power supply conductor is enlarged according to the depth, width, and vertical width of the recess, and the entire surface on one surface side of the semiconductor substrate is Can be used for forming.
電気絶縁は、半導体基板の他面に設けられた凹部内に充填されたナノコンポジット構造の電気絶縁層によって実現することが好ましい。緻密な電気絶縁層を構成することができるからである。ここに、ナノコンポジット構造とは、電気絶縁層９の内部に、電気絶縁層９の主成分とは異なる１μｍ以下（ｎｍサイズ）の微粒子を含んでいる構造をいう。 The electrical insulation is preferably realized by an electrical insulation layer having a nanocomposite structure filled in a recess provided on the other surface of the semiconductor substrate. This is because a dense electrical insulating layer can be formed. Here, the nanocomposite structure refers to a structure in which fine particles of 1 μm or less (nm size) different from the main component of the electric insulating layer 9 are contained in the electric insulating layer 9.
以上述べたように、本発明によれば、基板平面積の増大を抑制しつつ、電源供給線の断面積を増大させ、発熱を抑制した半導体装置を提供することができる。 As described above, according to the present invention, it is possible to provide a semiconductor device in which heat generation is suppressed by increasing the cross-sectional area of the power supply line while suppressing an increase in the plane area of the substrate.
図１〜図３に図示された半導体装置は、半導体基板１と、半導体回路部３と、電源供給導体５と、縦導体７とを含む。半導体基板１は、Si基板、炭化ケイ素（ＳｉＣ）基板又は窒化ガリウム（ＧａＮ）基板等である。これらの半導体基板１のうち、パワー半導体装置には、炭化ケイ素（ＳｉＣ）基板又は窒化ガリウム（ＧａＮ）基板が用いられる。 The semiconductor device illustrated in FIGS. 1 to 3 includes a semiconductor substrate 1, a semiconductor circuit unit 3, a power supply conductor 5, and a vertical conductor 7. The semiconductor substrate 1 is a Si substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or the like. Among these semiconductor substrates 1, a silicon carbide (SiC) substrate or a gallium nitride (GaN) substrate is used for the power semiconductor device.
半導体回路部３は、半導体素子部３１及びその配線部３２を含む。半導体素子部３１及び配線部３２は、半導体基板１の一面１０１の側に設けられている。半導体素子部３１は、半導体基板１の一面１０１の側に高密度で配置された多数の半導体素子を含んでいる。配線部３２は、複数設けられ、半導体素子部３１に含まれる半導体素子に対して、所定の関係、所定のパターンとなるように電気的に接続されている。 The semiconductor circuit unit 3 includes a semiconductor element unit 31 and its wiring unit 32. The semiconductor element part 31 and the wiring part 32 are provided on the one surface 101 side of the semiconductor substrate 1. The semiconductor element portion 31 includes a large number of semiconductor elements arranged at high density on the side of the one surface 101 of the semiconductor substrate 1. A plurality of wiring portions 32 are provided, and are electrically connected to the semiconductor elements included in the semiconductor element portion 31 so as to have a predetermined relationship and a predetermined pattern.
電源供給導体５は、半導体基板１の他面１０２に設けられている。実施の形態において、電源供給導体５は、複数ｎであり、それぞれは、半導体基板１の他面１０２に設けられた凹部１０３に充填された電気絶縁層９の内部に、間隔を隔てて形成されている。電源供給導体５のそれぞれは、電気絶縁層９により、半導体基板１からも電気絶縁されている。電源供給導体５のそれぞれは、断面矩形状であって、深さＨ１、幅Ｗ１、及び、長さL1の各ディメンションを有する。電源供給導体５の一部は、アース導体として用いることができる。電気絶縁層９は、ＳｉＯ２等によって構成することができる。 The power supply conductor 5 is provided on the other surface 102 of the semiconductor substrate 1. In the embodiment, there are a plurality n of power supply conductors 5, each of which is formed inside the electrical insulating layer 9 filled in the recess 103 provided on the other surface 102 of the semiconductor substrate 1 with a gap. ing. Each of the power supply conductors 5 is also electrically insulated from the semiconductor substrate 1 by the electrical insulation layer 9. Each of the power supply conductors 5 has a rectangular cross section and has dimensions of a depth H1, a width W1, and a length L1. A part of the power supply conductor 5 can be used as a ground conductor. The electrical insulating layer 9 can be made of SiO 2 or the like.
電気絶縁層９は、ナノコンポジット構造を有することが好ましい。緻密な電気絶縁層９を構成することができるからである。ここに、ナノコンポジット構造とは、電気絶縁層９の内部に、電気絶縁層９の主成分とは異なる１μｍ以下（ｎｍサイズ）の微粒子を含んでいる構造をいう。例えば、ｎｍサイズのSi微粒子と、有機Si化合物とを反応させてSiO2を主成分とする電気絶縁層９を形成する公知技術を適用したとき、SiO2を主成分とする電気絶縁層９の中に、未反応のSi微粒子又は有機Si化合物が残存するような場合である。ｎｍサイズの微粒子は、例えば、Ａｌ２Ｏ３微粒子又はその他のセラミック微粒子であってもよい。 The electrically insulating layer 9 preferably has a nanocomposite structure. This is because a dense electrical insulating layer 9 can be formed. Here, the nanocomposite structure refers to a structure in which fine particles of 1 μm or less (nm size) different from the main component of the electric insulating layer 9 are contained in the electric insulating layer 9. For example, when a known technique for forming an electrical insulating layer 9 mainly composed of SiO2 by reacting nm-sized Si fine particles with an organic Si compound is applied to the electrical insulating layer 9 mainly composed of SiO2. This is the case where unreacted Si fine particles or organic Si compounds remain. The nm-sized fine particles may be, for example, Al2O3 fine particles or other ceramic fine particles.
縦導体７は、必要な本数ｍだけ備えられ、半導体基板１を一面１０１の側から他面１０２の側に貫通し、半導体素子部３１及び配線部３２と電源供給導体５とを電気接続する。縦導体７のそれぞれは、電気絶縁層１１により、半導体基板１から電気絶縁して設けられている。縦導体７のそれぞれは、例えば口径１０μｍ〜６０μｍ程度の円形状又は角形状の態様をとることができる。縦導体７は、メッキによって形成してもよいし、金属充填法によって形成してもよい。 The required number m of the vertical conductors 7 is provided, penetrates the semiconductor substrate 1 from the one surface 101 side to the other surface 102 side, and electrically connects the semiconductor element portion 31 and the wiring portion 32 to the power supply conductor 5. Each of the vertical conductors 7 is provided by being electrically insulated from the semiconductor substrate 1 by an electrical insulating layer 11. Each of the vertical conductors 7 can take a circular or square shape with a diameter of about 10 μm to 60 μm, for example. The vertical conductor 7 may be formed by plating or may be formed by a metal filling method.
縦導体７の全てが、半導体基板１の一面１０１の側から他面１０２の側に貫通することは必ずしも必須ではない。縦導体７の一部は、非貫通であってもよい。そのような非貫通の縦導体７の存在、及び、配置パターン等によって、当該半導体装置が正当な製造者によって製造されたものであるか否かを判断する識別標識として用いることができる。 It is not always essential that all the vertical conductors 7 penetrate from the one surface 101 side of the semiconductor substrate 1 to the other surface 102 side. A part of the vertical conductor 7 may be non-penetrating. It can be used as an identification mark for determining whether or not the semiconductor device is manufactured by a legitimate manufacturer based on the presence of such a non-penetrating vertical conductor 7 and an arrangement pattern.
更に、縦導体７の全てが、半導体基板１に設けられた貫通孔に充填されることは、必ずしも必須ではない。例えば、その一部又は全部を、半導体基板１の側壁面に設けてもよい。 Further, it is not always essential that all the vertical conductors 7 are filled in the through holes provided in the semiconductor substrate 1. For example, a part or all of them may be provided on the side wall surface of the semiconductor substrate 1.
縦導体７と、電源供給導体５とを電気接続するに当たっては、図示のように、半導体基板１の他面１０２に所定のパターンで形成された配線１３によってもよいし、或いは、予め、配線を形成した他の基板を、半導体基板１の他面１０２に接合することによって実現してもよい。当然のことであるが、半導体基板１の他面１０２と配線１３との間は電気絶縁する。 In electrically connecting the vertical conductor 7 and the power supply conductor 5, as shown in the figure, the wiring 13 may be formed in a predetermined pattern on the other surface 102 of the semiconductor substrate 1, or the wiring may be previously connected. Another formed substrate may be realized by bonding to the other surface 102 of the semiconductor substrate 1. As a matter of course, the other surface 102 of the semiconductor substrate 1 and the wiring 13 are electrically insulated.
電源供給導体５及び縦導体７の配置位置、数ｎ、ｍ及び、断面形状等は、任意であり、図示に限定されるものではない。また、実施の形態では、インダクタ６が設けられている。インダクタ６は、一般的なインダクタンス素子として用いられるほか、半導体装置間の信号伝送手段となるアンテナとして用いられることもある。 The arrangement position, the number n, m, the cross-sectional shape, and the like of the power supply conductor 5 and the vertical conductor 7 are arbitrary and are not limited to those illustrated. In the embodiment, an inductor 6 is provided. Inductor 6 may be used as a general inductance element, or may be used as an antenna serving as a signal transmission means between semiconductor devices.
上述したように、本発明に係る半導体装置では、半導体回路部３を構成する半導体素子部３１及び配線部３２が、半導体基板１の一面１０１の側に設けられている。一方、電源供給導体５は、半導体基板１の他面１０２に設けられている。この構成によれば、半導体基板１の一面１０１の側では、半導体回路部３の配置密度を上げる一方、半導体基板１の他面１０２の側では、半導体回路部３による影響を受けることなく、電源供給導体５の断面積を増大させ得る。すなわち、半導体基板１の両面を有効に活用し、基板平面積の増大を抑制しつつ、電源供給導体５の断面積を増大させ、発熱を抑制し得る。電源供給導体５は、その断面積が、配線部３２の断面積よりも大きい。 As described above, in the semiconductor device according to the present invention, the semiconductor element portion 31 and the wiring portion 32 constituting the semiconductor circuit portion 3 are provided on the one surface 101 side of the semiconductor substrate 1. On the other hand, the power supply conductor 5 is provided on the other surface 102 of the semiconductor substrate 1. According to this configuration, the arrangement density of the semiconductor circuit portions 3 is increased on the one surface 101 side of the semiconductor substrate 1, while the power source is not affected by the semiconductor circuit portion 3 on the other surface 102 side of the semiconductor substrate 1. The cross-sectional area of the supply conductor 5 can be increased. That is, it is possible to effectively use both surfaces of the semiconductor substrate 1 and increase the cross-sectional area of the power supply conductor 5 while suppressing an increase in the plane area of the substrate, thereby suppressing heat generation. The power supply conductor 5 has a cross-sectional area larger than that of the wiring portion 32.
しかも、電源供給導体５は、半導体回路部３のある半導体基板１の一面１０１の側とは反対側の他面に設けられているから、半導体回路部３による制限を受けることなく、電源供給導体５に対してヒートシンクを熱結合させ、放熱性を向上させることができる。例えば、図４に示すように、インターポーザ１５の上で、メモリチップ及びロジックチップ等の複数の半導体装置１A、１Bを、一面１０１を互いに向き合い、電源供給導体５の露出する他面１０２が外側を向く様にして積層するとともに、上側の半導体装置１Bの電源供給導体５に、熱伝導体１７、及び、ヒートシンク１９を熱結合させることにより、放熱性を向上させることができる。 Moreover, since the power supply conductor 5 is provided on the other surface opposite to the one surface 101 side of the semiconductor substrate 1 where the semiconductor circuit portion 3 is located, the power supply conductor 5 is not limited by the semiconductor circuit portion 3. The heat sink can be thermally coupled to 5 to improve heat dissipation. For example, as shown in FIG. 4, on the interposer 15, a plurality of semiconductor devices 1 </ b> A and 1 </ b> B such as a memory chip and a logic chip are arranged such that one surface 101 faces each other and the other surface 102 where the power supply conductor 5 is exposed is outside. Heat dissipation can be improved by laminating the layers so as to face each other and thermally coupling the heat conductor 17 and the heat sink 19 to the power supply conductor 5 of the upper semiconductor device 1B.
また、本発明に係る半導体装置は、縦導体７を含んでおり、縦導体７は、半導体基板１を一面１０１の側から他面１０２の側に貫通し、半導体素子部３１及び配線部３２と電源供給導体５とを電気接続する。この構造によれば、電源供給導体５及び縦導体７を経由して、半導体回路部３に電力を供給することができる。 In addition, the semiconductor device according to the present invention includes a vertical conductor 7, and the vertical conductor 7 penetrates the semiconductor substrate 1 from the one surface 101 side to the other surface 102 side, and the semiconductor element portion 31 and the wiring portion 32. The power supply conductor 5 is electrically connected. According to this structure, power can be supplied to the semiconductor circuit unit 3 via the power supply conductor 5 and the vertical conductor 7.
実施の形態において、電源供給導体５は、半導体基板１の他面に設けられた凹部１０３内に設けられているから、半導体基板１の他面１０２の側では、電源供給導体５の断面積を、凹部１０３の深さ、横幅及び縦幅に応じて拡大すると共に、半導体基板１の一面１０１の側の全面を、半導体回路部形成のために供することができる。 In the embodiment, since the power supply conductor 5 is provided in the recess 103 provided on the other surface of the semiconductor substrate 1, the cross-sectional area of the power supply conductor 5 is set on the other surface 102 side of the semiconductor substrate 1. The entire surface on the side of the first surface 101 of the semiconductor substrate 1 can be used for forming the semiconductor circuit portion while expanding according to the depth, width, and length of the recess 103.
次に、上述した半導体装置の製造方法について、図５〜図１０を参照して説明する。まず、図５に図示するように、一面１０１の側に半導体回路部３を形成してある半導体ウエハ１１０の他面１０２（裏面）にキャビティ１０３を形成する。このキャビティ１０３は、図１〜図３の凹部となる。図中、X-X線はチップとして取り出す際の切断位置を示している。 Next, a method for manufacturing the semiconductor device described above will be described with reference to FIGS. First, as shown in FIG. 5, a cavity 103 is formed on the other surface 102 (back surface) of the semiconductor wafer 110 on which the semiconductor circuit portion 3 is formed on the one surface 101 side. This cavity 103 becomes a recess in FIGS. In the figure, the XX line indicates the cutting position when taking out as a chip.
次に、図６に示すように、キャビティ１０３の内部に充填された電気絶縁層９に、電源供給導体充填用の配線溝５００を形成した後、図７に示すように、配線溝５００の内部に電源供給導体５を充填する。 Next, as shown in FIG. 6, a wiring groove 500 for filling the power supply conductor is formed in the electrical insulating layer 9 filled in the cavity 103, and then, as shown in FIG. Is filled with the power supply conductor 5.
次に、図８に示すように、半導体ウエハ１００の縦導体形成領域内に、その一面１０１の側から他面１０２の側に貫通する貫通溝１１０を形成する。貫通溝１１０の内側には、半導体ウエハ１００の一部が棒状部（ポスト）１０４として残る。 Next, as shown in FIG. 8, a through groove 110 penetrating from the one surface 101 side to the other surface 102 side is formed in the vertical conductor forming region of the semiconductor wafer 100. A part of the semiconductor wafer 100 remains as a rod-shaped portion (post) 104 inside the through groove 110.
次に、図９に示すように、貫通溝１１０の内部に電気絶縁材を充填して、電気絶縁層１１を形成した後、図１０に示すように、電気絶縁層１１によって囲まれたポスト１０４を除去し、更に、図１１に示すように、その除去跡１０５に金属を充填して、縦導体７を形成する。 Next, as shown in FIG. 9, the inside of the through groove 110 is filled with an electrical insulating material to form the electrical insulating layer 11, and then, as shown in FIG. 10, the post 104 surrounded by the electrical insulating layer 11. Further, as shown in FIG. 11, the removal trace 105 is filled with a metal to form the vertical conductor 7.
この後、半導体ウエハ１００をX-X線で切断するダイシング工程等、必要な工程を経て、図１〜図３に示した半導体装置が得られる。
以上、好ましい実施例を参照して本発明を詳細に説明したが、本発明はこれらに限定されるものではなく、当業者であれば、その基本的技術思想および教示に基づき、種々の変形例を想到できることは自明である。
Thereafter, the semiconductor device shown in FIGS. 1 to 3 is obtained through necessary steps such as a dicing step of cutting the semiconductor wafer 100 along the XX line.
The present invention has been described in detail with reference to the preferred embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made by those skilled in the art based on the basic technical idea and teachings. It is self-evident that
１ 半導体基板
３ 半導体回路部
３１ 半導体素子部
３２ 配線部
５ 電源供給導体
７ 縦導体
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 3 Semiconductor circuit part 31 Semiconductor element part 32 Wiring part 5 Power supply conductor 7 Vertical conductor
Claims (3)
前記半導体回路部は、半導体素子部及びその配線部を含み、前記半導体素子部及び前記配線部は、前記半導体基板の一面側に設けられており、
前記電源供給導体は、前記半導体基板の他面に設けられており、
前記縦導体は、前記半導体基板の前記一面側から他面側に導かれ、前記半導体素子部及び前記配線部と前記電源供給導体とを接続する、
半導体装置。 A semiconductor device including a semiconductor substrate, a semiconductor circuit unit, a power supply conductor, and a vertical conductor,
The semiconductor circuit portion includes a semiconductor element portion and a wiring portion thereof, and the semiconductor element portion and the wiring portion are provided on one surface side of the semiconductor substrate,
The power supply conductor is provided on the other surface of the semiconductor substrate,
The vertical conductor is guided from the one surface side of the semiconductor substrate to the other surface side, and connects the semiconductor element portion and the wiring portion and the power supply conductor,
Semiconductor device.
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| JP2015238371A JP2017107898A (en) | 2015-12-07 | 2015-12-07 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015238371A JP2017107898A (en) | 2015-12-07 | 2015-12-07 | Semiconductor device |
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| Publication Number | Publication Date |
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| JP2017107898A true JP2017107898A (en) | 2017-06-15 |
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