JP2017103260A - Transistor and method of manufacturing transistor - Google Patents
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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Abstract
Description
本発明の実施形態は、トランジスタ、および、トランジスタの製造方法に関する。 Embodiments described herein relate generally to a transistor and a method for manufacturing the transistor.
トランジスタは、例えば、表示装置、イメージセンサ、半導体メモリ等、半導体回路を含む種々の電子機器を含む半導体装置に用いられている。 Transistors are used in semiconductor devices including various electronic devices including semiconductor circuits such as display devices, image sensors, and semiconductor memories.
近年、撮像素子として、ＣＭＯＳプロセスを用いたＣＭＯＳイメージセンサが開発されている。撮像素子は高画素化、高速化、高ダイナミックレンジ化を軸とした開発が行われおり、回路の微細化や裏面照射などの開発が進められてきた。しかしながら、回路の微細化が進むと、フォトダイオードの受光面積が減少し、Ｓ／Ｎ比が悪くなってしまう。 In recent years, a CMOS image sensor using a CMOS process has been developed as an image sensor. Image sensors have been developed with a focus on higher pixels, higher speed, and higher dynamic range, and developments such as circuit miniaturization and backside illumination have been promoted. However, as the circuit becomes finer, the light receiving area of the photodiode decreases and the S / N ratio becomes worse.
そこで、画素内にあるアンプやリセットのトランジスタをフォトダイオード上の配線層に形成する積層型ＣＭＯＳイメージセンサを用いることによって、微細化とＳ／Ｎ比の確保を両立できる。ＣＭＯＳプロセスで形成したフォトダイオードの上層に薄膜トランジスタ（Thin Film Transistor：ＴＦＴ）を積層する場合、ＣＭＯＳプロセスよりも比較的低温で形成できる半導体材料が必要となる。 Therefore, by using a stacked CMOS image sensor in which an amplifier and a reset transistor in a pixel are formed in a wiring layer on a photodiode, both miniaturization and securing of an S / N ratio can be achieved. In the case where a thin film transistor (TFT) is stacked on the upper layer of a photodiode formed by a CMOS process, a semiconductor material that can be formed at a relatively lower temperature than the CMOS process is required.
そこで、次世代ＴＦＴの半導体層材料として、酸化物半導体が近年注目されている。中でも、Ｉｎ−Ｇａ−Ｚｎ−Ｏ（以下、ＩＧＺＯ）などのアモルファス酸化物半導体を用いたＴＦＴが注目されている。上記酸化物半導体は、スパッタリング法によって、室温で大面積に均一に成膜でき、３００℃〜４００℃の比較的低温なプロセス温度で高信頼性、高均一なＴＦＴを形成することができる。さらには、電界効果移動度がアモルファスシリコンに対して１０倍程度と、高移動度な特性が得られる。 Thus, oxide semiconductors have recently attracted attention as a semiconductor layer material for next-generation TFTs. In particular, a TFT using an amorphous oxide semiconductor such as In—Ga—Zn—O (hereinafter, IGZO) is attracting attention. The oxide semiconductor can be uniformly formed over a large area at room temperature by a sputtering method, and a highly reliable and highly uniform TFT can be formed at a relatively low process temperature of 300 ° C. to 400 ° C. Furthermore, the field effect mobility is about 10 times that of amorphous silicon, and high mobility characteristics can be obtained.
回路の微細化を実現するためには、ＴＦＴのチャネル長を短くすることが望ましい。しかしながら、酸化物半導体を用いたＴＦＴのチャネル長を短くすると、閾値電圧が負側へシフトする傾向を本願発明者らは見出した。この閾値電圧のシフトは、酸化物半導体の膜厚が厚くなる程顕著であることも見出した。閾値電圧が負側へシフトするとＴＦＴがノーマリオフとならないため、このＴＦＴを搭載した半導体装置の信頼性が低下する可能性があった。 In order to realize circuit miniaturization, it is desirable to shorten the channel length of the TFT. However, the present inventors have found that when the channel length of a TFT using an oxide semiconductor is shortened, the threshold voltage tends to shift to the negative side. It has also been found that this threshold voltage shift becomes more significant as the thickness of the oxide semiconductor increases. When the threshold voltage is shifted to the negative side, the TFT is not normally off, so that there is a possibility that the reliability of the semiconductor device equipped with this TFT is lowered.
本発明の実施形態は、酸化物半導体を用いたときの電気的特性を改善したトランジスタ、および、トランジスタの製造法を提供することを目的とする。 An object of an embodiment of the present invention is to provide a transistor with improved electrical characteristics when an oxide semiconductor is used, and a method for manufacturing the transistor.
実施形態によれば、トランジスタは、ゲート電極と、ゲート電極の上に設けられた第１絶縁層と、前記第１絶縁層を介して前記ゲート電極上に配置され、第１コンタクト部と、第２コンタクト部と、前記第１コンタクト部と前記第２コンタクト部との間に配置されたチャネル部とを含み、前記チャネル部の膜厚が前記第１コンタクト部および前記第２コンタクト部の膜厚よりも小さい半導体層と、前記半導体層を覆うとともに、前記第１コンタクト部および前記第２コンタクト部上に設けられた開口を備えたチャネル保護膜と、前記チャネル保護膜の前記開口において前記第１コンタクト部と電気的に接続したソース電極と、前記チャネル保護膜の前記開口において前記第２コンタクト部と電気的に接続したドレイン電極と、を備え、前記半導体層は、Ｉｎ、Ｇａ、Ｚｎの少なくとも１つの材料を含む酸化物半導体である。 According to the embodiment, the transistor includes a gate electrode, a first insulating layer provided on the gate electrode, the first insulating layer disposed on the gate electrode, a first contact portion, 2 contact portions, and a channel portion disposed between the first contact portion and the second contact portion, and the film thickness of the channel portion is the thickness of the first contact portion and the second contact portion. Smaller than the semiconductor layer, a channel protective film covering the semiconductor layer and having an opening provided on the first contact portion and the second contact portion, and the first opening in the opening of the channel protective film. A source electrode electrically connected to the contact portion, and a drain electrode electrically connected to the second contact portion in the opening of the channel protective film, Body layer is an oxide semiconductor containing In, Ga, and at least one material of Zn.
以下、実施形態のトランジスタ、および、トランジスタの製造方法について、図面を参照して説明する。
図１は、実施形態のトランジスタの構成例を説明するための断面図である。
本実施形態のトランジスタは、例えばＣＭＯＳプロセスで形成されたフォトダイオードを用いた撮像素子に搭載されてもよくよく、表示画素等のスイッチング素子として採用した表示装置に搭載されてもよい。本実施形態のトランジスタが搭載される半導体装置は上記に限定されるものではなく、酸化物半導体を用いたトランジスタを含む種々の電子機器である。
Hereinafter, a transistor of the embodiment and a method for manufacturing the transistor will be described with reference to the drawings.
FIG. 1 is a cross-sectional view illustrating a configuration example of a transistor according to an embodiment.
The transistor of this embodiment may be mounted on an imaging device using a photodiode formed by, for example, a CMOS process, or may be mounted on a display device employed as a switching element such as a display pixel. The semiconductor device on which the transistor of this embodiment is mounted is not limited to the above, and includes various electronic devices including a transistor using an oxide semiconductor.
本実施形態のトランジスタは、ゲート電極ＧＥと、ゲート絶縁膜Ｌ１と、酸化物半導体層ＳＣと、チャネル保護膜Ｌ２と、ソース電極ＳＥと、ドレイン電極ＤＥと、を備えている。 The transistor of this embodiment includes a gate electrode GE, a gate insulating film L1, an oxide semiconductor layer SC, a channel protective film L2, a source electrode SE, and a drain electrode DE.
ゲート電極ＧＥは、下地としての絶縁体上に配置されている。ゲート電極ＧＥは、例えば銅配線やバリアメタルと同じ材料により形成されている。ゲート電極ＧＥは、図示しないゲート配線と電気的に接続され（あるいは一体に形成され）、ゲート配線を介して所定の駆動電圧が印加される。 The gate electrode GE is disposed on an insulator as a base. The gate electrode GE is formed of, for example, the same material as copper wiring or barrier metal. The gate electrode GE is electrically connected (or integrally formed) with a gate wiring (not shown), and a predetermined driving voltage is applied through the gate wiring.
ゲート絶縁膜Ｌ１は、ゲート電極ＧＥ上に配置されゲート電極ＧＥを覆っている。ゲート絶縁膜Ｌ１は、例えばＳｉＮｘ膜であってもよく、ＳｉＮｘ膜上に形成したＳｉＯｘ膜、もしくはＡｌＯｘ膜、ＴａＯｘ膜、ＨｆＯｘ膜、ＴｉＯｘ膜などのＨｉｇｈ−ｋ膜を積層構造のゲート絶縁膜として用いても良い。ゲート絶縁膜Ｌ１は、その膜厚が例えば略１０乃至２０ｎｍに形成されている。ゲート電極ＧＥは、第１種面とこの第１主面に対向する第２主面とを有する。 The gate insulating film L1 is disposed on the gate electrode GE and covers the gate electrode GE. The gate insulating film L1 may be, for example, a SiNx film, and a SiOx film formed on the SiNx film, or a high-k film such as an AlOx film, a TaOx film, a HfOx film, or a TiOx film is used as a gate insulating film having a laminated structure It may be used. The gate insulating film L1 is formed to have a thickness of about 10 to 20 nm, for example. The gate electrode GE has a first type surface and a second main surface opposite to the first main surface.
酸化物半導体層ＳＣは、酸化物半導体層ＳＣは、Ｉｎ−Ｇａ−Ｚｎ−Ｏ（以下、ＩｎＧａＺｎＯ）などのアモルファス酸化物半導体である。酸化物半導体層ＳＣは、ＩｎＧａＺｎＯに限定されるものではなく、Ｉｎ、Ｇａ、Ｚｎの少なくとも１つを含む酸化物半導体であればよい。 The oxide semiconductor layer SC is an amorphous oxide semiconductor such as In—Ga—Zn—O (hereinafter, InGaZnO). The oxide semiconductor layer SC is not limited to InGaZnO, and may be an oxide semiconductor containing at least one of In, Ga, and Zn.
本実施形態では、酸化物半導体層ＳＣは、反応性スパッタリング法で形成する。スパッタ時の成膜雰囲気はアルゴンと酸素の混合雰囲気である。酸化物半導体層ＳＣのキャリア密度は、スパッタ時のアルゴンと酸素の比率で制御することができる。 In the present embodiment, the oxide semiconductor layer SC is formed by a reactive sputtering method. The film formation atmosphere at the time of sputtering is a mixed atmosphere of argon and oxygen. The carrier density of the oxide semiconductor layer SC can be controlled by the ratio of argon and oxygen during sputtering.
なお、酸化物半導体層ＳＣの形成方法として、例えば、ＰＬＤ法、反応性スパッタリング法、ＣＶＤ法、スピンコート法など各種薄膜形成方法を用いることが可能である。 As a method for forming the oxide semiconductor layer SC, various thin film forming methods such as a PLD method, a reactive sputtering method, a CVD method, and a spin coating method can be used.
酸化物半導体層ＳＣは、酸化構造を有し、多結晶構造を有している。各種薄膜構造は高倍率ＴＥＭで観察し、確認することができる。 The oxide semiconductor layer SC has an oxide structure and a polycrystalline structure. Various thin film structures can be observed and confirmed with a high magnification TEM.
酸化物半導体層ＳＣは、チャネル部ＣＮＬとコンタクト部ＣＴとを有している。チャネル部ＣＮＬは一対のコンタクト部ＣＴ間に配置されている。チャネル部ＣＮＬの厚さ（第１主面に略垂直な方向Ｙにおける膜厚）は略５ｎｍである。チャネル部ＣＮＬの第１主面に略平行な方向Ｘにおける幅（チャネル長）Ｌは、１０ｎｍ以上１００μｍ以下、好ましくは１０ｎｍ以上５μｍ以下、さらに好ましくは１０ｎｍ以上１μｍ以下である。なお、チャネル部ＣＮＬの厚さは２ｎｍ以上１０ｎｍ以下であることが望ましい。チャネル長ＣＮＬは一対のコンタクト部ＣＴの距離を示す。 The oxide semiconductor layer SC has a channel part CNL and a contact part CT. The channel part CNL is disposed between the pair of contact parts CT. The thickness of the channel portion CNL (film thickness in the direction Y substantially perpendicular to the first main surface) is approximately 5 nm. The width (channel length) L in the direction X substantially parallel to the first main surface of the channel portion CNL is 10 nm to 100 μm, preferably 10 nm to 5 μm, more preferably 10 nm to 1 μm. Note that the thickness of the channel portion CNL is desirably 2 nm or more and 10 nm or less. The channel length CNL indicates the distance between the pair of contact portions CT.
コンタクト部ＣＴは、第１コンタクト部ＣＴ１と第２コンタクト部ＣＴ２とを備え、基板面と略平行な方向Ｘにおいてチャネル部ＣＮＬの両側に配置されている。コンタクト部ＣＴの厚さは略２５ｎｍである。なお、コンタクト部ＣＴの膜厚Ｈは、少なくともチャネル部ＣＮＬの膜厚よりも大きいことが望ましく、１０ｎｍ以上１００ｎｍ以下とすることが望ましい。ここで、コンタクト部ＣＴの膜厚Ｈはコンタクト部ＣＴの方向Ｙにおける幅の最大値であって、コンタクト部ＣＴの穴が設けられた部分の膜厚とは異なる。また、コンタクト部ＣＴの方向Ｘにおける幅は略０．２μｍ以上１０μｍ以下である。 The contact portion CT includes a first contact portion CT1 and a second contact portion CT2, and is disposed on both sides of the channel portion CNL in a direction X substantially parallel to the substrate surface. The thickness of the contact part CT is approximately 25 nm. Note that the film thickness H of the contact part CT is desirably at least larger than the film thickness of the channel part CNL, and is desirably 10 nm or more and 100 nm or less. Here, the film thickness H of the contact part CT is the maximum value of the width in the direction Y of the contact part CT, and is different from the film thickness of the part where the hole of the contact part CT is provided. Further, the width in the direction X of the contact portion CT is approximately 0.2 μm or more and 10 μm or less.
コンタクト部ＣＴは、方向Ｘにおいてチャネル部ＣＮＬの一方側と他方側とにそれぞれ設けられた穴を有している。コンタクト部ＣＴに設けられた穴の径は方向Ｘにおいて略０．１μｍ以上５μｍ以下である。コンタクト部ＣＴに設けられた穴は、後述するチャネル保護膜Ｌ２の開口とつながり、それぞれにソース電極ＳＥとドレイン電極ＤＥとの一部が配置される。換言すると、酸化物半導体層ＳＣは、コンタクト部ＣＴの一方（第１コンタクト部ＣＴ１）に設けられた穴においてソース電極ＳＥと電気的に接続するとともに、コンタクト部ＣＴの他方（第２コンタクト部ＣＴ２）に設けられた穴においてドレイン電極ＤＥと電気的に接続している。 The contact part CT has holes provided on one side and the other side of the channel part CNL in the direction X, respectively. The diameter of the hole provided in the contact portion CT is approximately 0.1 μm or more and 5 μm or less in the direction X. A hole provided in the contact portion CT is connected to an opening of a channel protective film L2 described later, and a part of the source electrode SE and the drain electrode DE is disposed in each hole. In other words, the oxide semiconductor layer SC is electrically connected to the source electrode SE in a hole provided in one of the contact portions CT (first contact portion CT1), and the other of the contact portions CT (second contact portion CT2). Is electrically connected to the drain electrode DE.
上記の酸化物半導体層ＳＣを形成する工程は、第１層ＳＣ１を形成する工程と、第２層ＳＣ２を形成する工程と、を有している。 The step of forming the oxide semiconductor layer SC includes a step of forming the first layer SC1 and a step of forming the second layer SC2.
第１層ＳＣ１は、ＩｎＧａＺｎＯ等の酸化物半導体材料を成膜およびパターニングすることにより形成される。第１層ＳＣ１は、第１コンタクト部ＣＴ１および第２コンタクト部ＣＴ２のみに形成され、チャネル部ＣＮＬにおいて除去されるように所定のマスクを用いてパターンニングされる。 The first layer SC1 is formed by depositing and patterning an oxide semiconductor material such as InGaZnO. The first layer SC1 is formed only in the first contact portion CT1 and the second contact portion CT2, and is patterned using a predetermined mask so as to be removed in the channel portion CNL.
第１層ＳＣ１を形成した後に、不活性雰囲気で３５０℃の加熱処理（不活性雰囲気アニール）を行った。ここで、第１層ＳＣ１の成膜およびパターンニング後の加熱処理は好ましくは２００℃以上、更に好ましくは３５０℃以上で行う。 After forming the first layer SC1, heat treatment (inert atmosphere annealing) at 350 ° C. was performed in an inert atmosphere. Here, the heat treatment after the film formation and patterning of the first layer SC1 is preferably performed at 200 ° C. or higher, more preferably 350 ° C. or higher.
なお、第１層ＳＣ１を形成した後に、水素を含有した雰囲気中での加熱処理を行ってもよい。例えば、パターンニングにより第１層ＳＣ１を形成した後に、水素雰囲気中において２００℃で加熱処理を行うことにより、第１層ＳＣ１の抵抗値を第２層ＳＣ２よりも低くすることができる。 Note that heat treatment in an atmosphere containing hydrogen may be performed after the first layer SC1 is formed. For example, after forming the first layer SC1 by patterning, the resistance value of the first layer SC1 can be made lower than that of the second layer SC2 by performing heat treatment at 200 ° C. in a hydrogen atmosphere.
また、第１層ＳＣ１を形成した後に、水素プラズマ処理あるいはＡｒプラズマ処理を行ってもよい。例えば、パターンニングにより第１層ＳＣ１を形成した後に、水素プラズマ処理あるいはＡｒプラズマ処理を行うことにより、第１層ＳＣ１の抵抗値を第２層ＳＣ２よりも低くすることができる。 Further, after forming the first layer SC1, hydrogen plasma treatment or Ar plasma treatment may be performed. For example, after forming the first layer SC1 by patterning, the resistance value of the first layer SC1 can be made lower than that of the second layer SC2 by performing hydrogen plasma treatment or Ar plasma treatment.
すなわち、酸化物半導体層ＳＣは、前記第１コンタクト部および前記第２コンタクト部における抵抗が前記チャネル部よりも低くなる。 That is, the oxide semiconductor layer SC has a resistance lower than that of the channel portion in the first contact portion and the second contact portion.
続けて、ＩｎＧａＺｎＯ等の酸化物半導体材料を成膜およびパターニングして第２層ＳＣ２を形成する。第２層ＳＣ２は、チャネル部ＣＮＬおよびコンタクト部（第１コンタクト部ＣＴ１および第２コンタクト部ＣＴ２）ＣＴの両方に形成されるように所定のマスクを用いてパターンニングされる。 Subsequently, an oxide semiconductor material such as InGaZnO is formed and patterned to form the second layer SC2. The second layer SC2 is patterned using a predetermined mask so as to be formed in both the channel portion CNL and the contact portion (first contact portion CT1 and second contact portion CT2) CT.
チャネル保護膜Ｌ２は、酸化物半導体層ＳＣ上にコンタクト部ＣＴおよびチャネル部ＣＮＬを覆うように配置されている。チャネル保護膜Ｌ２は、一対のコンタクト部ＣＴの穴それぞれとつながる一対の開口を有している。 The channel protective film L2 is disposed on the oxide semiconductor layer SC so as to cover the contact part CT and the channel part CNL. The channel protective film L2 has a pair of openings connected to the holes of the pair of contact portions CT.
チャネル保護膜Ｌ２は保護膜として機能する層間絶縁膜（ＳｉＯｘ膜等）であって、例えばＰＥＣＶＤ（plasma-enhanced chemical vapor deposition）法で形成される。チャネル保護膜Ｌ２の成膜雰囲気は、例えばシランと一酸化二窒素の混合雰囲気である。 The channel protective film L2 is an interlayer insulating film (SiOx film or the like) that functions as a protective film, and is formed by, for example, PECVD (plasma-enhanced chemical vapor deposition). The film forming atmosphere of the channel protective film L2 is, for example, a mixed atmosphere of silane and dinitrogen monoxide.
続いて、クリーンオーブンもしくは石英炉で加熱処理を行う。ここで行う加熱処理は、２００℃〜５００℃、好ましくは３５０〜５００℃で行い、雰囲気は大気および窒素雰囲気で行う。 Subsequently, heat treatment is performed in a clean oven or a quartz furnace. The heat treatment performed here is performed at 200 to 500 ° C., preferably 350 to 500 ° C., and the atmosphere is an air and nitrogen atmosphere.
続いて、酸化物半導体層ＳＣの一部を露出するようにチャネル保護膜Ｌ２に一対の開口を形成する。チャネル保護膜Ｌ２に開口を形成するには、反応性イオンエッチングで形成する。このとき、酸化物半導体層ＳＣの一部にも穴が形成される。 Subsequently, a pair of openings is formed in the channel protective film L2 so as to expose a part of the oxide semiconductor layer SC. In order to form the opening in the channel protective film L2, it is formed by reactive ion etching. At this time, a hole is also formed in part of the oxide semiconductor layer SC.
ソース電極ＳＥおよびドレイン電極ＤＥは、チャネル保護膜Ｌ２上に配置されている。ソース電極ＳＥおよびドレイン電極は、例えば、Ｍｏ、Ｔｉ、Ａｌ、ＩＴＯ、ＩＺＯ、ＴｉＮ、ＴａＮ、あるいは、これらの積層体などにより形成されている。ソース電極ＳＥはチャネル保護膜Ｌ２の一方の開口上に配置され、ドレイン電極ＤＥはチャネル保護膜Ｌ２の他方の開口上に配置され、それぞれ酸化物半導体層ＳＣのコンタクト部ＣＴと電気的に接続している。 The source electrode SE and the drain electrode DE are disposed on the channel protective film L2. The source electrode SE and the drain electrode are formed of, for example, Mo, Ti, Al, ITO, IZO, TiN, TaN, or a laminate thereof. The source electrode SE is disposed on one opening of the channel protective film L2, and the drain electrode DE is disposed on the other opening of the channel protective film L2, and is electrically connected to the contact portion CT of the oxide semiconductor layer SC. ing.
ソース電極ＳＥおよびドレイン電極ＤＥは、金属材料を成膜し、所定の形状にパターンニングして形成される。具体的には、まず、ソース電極ＳＥおよびドレイン電極ＤＥとなる金属材料を例えばマグネトロンスパッタリング法により成膜する。金属材料を成膜後、誘導型反応性イオンエッチングで所定の形状にパターニングしてソース電極ＳＥおよびドレイン電極ＤＥを形成する。 The source electrode SE and the drain electrode DE are formed by depositing a metal material and patterning it into a predetermined shape. Specifically, first, a metal material to be the source electrode SE and the drain electrode DE is formed by, for example, a magnetron sputtering method. After forming the metal material, the source electrode SE and the drain electrode DE are formed by patterning into a predetermined shape by inductive reactive ion etching.
次にクリーンオーブンもしくは石英炉で加熱処理を行う。加熱処理は２００℃〜４５０℃、好ましくは３５０〜４００℃で行う。雰囲気は大気および窒素雰囲気で行う。 Next, heat treatment is performed in a clean oven or a quartz furnace. The heat treatment is performed at 200 ° C. to 450 ° C., preferably 350 to 400 ° C. The atmosphere is air and nitrogen atmosphere.
ソース電極ＳＥおよびドレイン電極ＤＥはパッシベーション膜Ｌ３によって覆われている。パッシベーション膜Ｌ３は、例えば窒化シリコン（Ｓｉ３Ｎ４）等により形成されている。 The source electrode SE and the drain electrode DE are covered with a passivation film L3. The passivation film L3 is formed of, for example, silicon nitride (Si 3 N 4 ) or the like.
図２は、酸化物半導体を用いたトランジスタのチャネル長に依存する電気的特性の一例を説明するための図である。
図２に示すグラフの横軸は、酸化物半導体を用いたトランジスタのチャネル長Ｌ［μｍ］であり、縦軸はトランジスタを形成した後に例えば２００℃以下で加熱処理を行った場合の閾値電圧と、高温（例えば４００℃程度）で加熱処理を行った場合の閾値電圧との変化ΔＶｔｈ［Ｖ］である。
FIG. 2 is a diagram for describing an example of electrical characteristics depending on a channel length of a transistor including an oxide semiconductor.
The horizontal axis of the graph shown in FIG. 2 is the channel length L [μm] of the transistor using an oxide semiconductor, and the vertical axis is the threshold voltage when heat treatment is performed at 200 ° C. or lower after the transistor is formed. The change ΔVth [V] from the threshold voltage when the heat treatment is performed at a high temperature (for example, about 400 ° C.).
図２に示すトランジスタの電気的特性によれば、トランジスタのチャネル長Ｌが大きい程、高温の熱処理に依る閾値電圧の変化ΔＶｔｈが小さく、チャネル長Ｌが小さい程、閾値電圧の変化ΔＶｔｈが大きくなる傾向があることが分かる。 According to the electrical characteristics of the transistor shown in FIG. 2, the larger the channel length L of the transistor, the smaller the threshold voltage change ΔVth due to high-temperature heat treatment, and the smaller the channel length L, the larger the threshold voltage change ΔVth. It turns out that there is a tendency.
また、高温で加熱処理を行った場合の閾値電圧が、トランジスタ形成後の加熱処理を行った場合の閾値電圧よりも小さくなっている。 Further, the threshold voltage when the heat treatment is performed at a high temperature is smaller than the threshold voltage when the heat treatment after the transistor is formed.
上記のことから、半導体回路の微細化が進むことによりチャネル長Ｌが小さくなり、かつ、トランジスタ形成後の加熱処理温度が高くなると、トランジスタの閾値電圧Ｖｔｈが負側へシフトする傾向がみられる。 From the above, if the channel length L is reduced as the semiconductor circuit is miniaturized and the heat treatment temperature after formation of the transistor is increased, the threshold voltage Vth of the transistor tends to shift to the negative side.
これは、トランジスタ形成後の加熱処理においてソース電極ＳＥおよびドレイン電極ＤＥから酸化物半導体層へ不純物が拡散して酸化物半導体の特性が劣化するためと考えられる。したがって、チャネル長Ｌが小さくなると実質的にチャネルとして機能する部分の長さが短くなり、トランジスタの電気的特性が劣化することとなる。 This is presumably because impurities are diffused from the source electrode SE and the drain electrode DE into the oxide semiconductor layer in the heat treatment after the transistor is formed, so that the characteristics of the oxide semiconductor are deteriorated. Therefore, when the channel length L is reduced, the length of the portion that functions as a channel is substantially reduced, and the electrical characteristics of the transistor are deteriorated.
図３は、酸化物半導体を用いたトランジスタの酸化物半導体層の膜厚に依存する電気的特性の一例を説明するための図である。 FIG. 3 is a diagram for describing an example of electrical characteristics depending on the thickness of an oxide semiconductor layer of a transistor including an oxide semiconductor.
図３に示すグラフの横軸は、チャネル部ＣＮＬにおける酸化物半導体層の厚さ［ｎｍ］であり、縦軸はトランジスタを形成した後の加熱処理を行った場合の閾値電圧と、高温で加熱処理を行った場合の閾値電圧との変化ΔＶｔｈ［Ｖ］である。 The horizontal axis of the graph shown in FIG. 3 is the thickness [nm] of the oxide semiconductor layer in the channel portion CNL. It is a change ΔVth [V] from the threshold voltage when processing is performed.
図３に示すトランジスタの電気的特性によれば、トランジスタのチャネル部ＣＮＬにおける酸化物半導体層の膜厚が小さい程、閾値電圧の変化ΔＶｔｈが小さく、トランジスタのチャネル部ＣＮＬにおける酸化物半導体層の膜厚が大きい程、閾値電圧の変化ΔＶｔｈが大きくなる傾向があることが分かる。 According to the electrical characteristics of the transistor illustrated in FIG. 3, the smaller the oxide semiconductor layer thickness in the channel portion CNL of the transistor, the smaller the threshold voltage change ΔVth. It can be seen that the threshold voltage change ΔVth tends to increase as the thickness increases.
上記のことから、酸化物半導体層の膜厚が大きくなり、かつ、かつ、トランジスタ形成後の加熱処理温度が高くなると、トランジスタの閾値電圧Ｖｔｈが負側へシフトする傾向がみられる。 From the above, when the thickness of the oxide semiconductor layer is increased and the heat treatment temperature after the formation of the transistor is increased, the threshold voltage Vth of the transistor tends to shift to the negative side.
図４は、酸化物半導体を用いたトランジスタの酸化物半導体層の膜厚Ｈに依存する電気的特性の一例を説明するための図である。 FIG. 4 is a diagram for describing an example of electrical characteristics depending on the thickness H of the oxide semiconductor layer of a transistor including an oxide semiconductor.
図４に示すグラフの横軸はゲート電極ＧＥに印加されるゲート電圧Ｖｇ［Ｖ］であり、縦軸はソース電極ＳＥとドレイン電極ＤＥとの間に流れる電流Ｉｄ［Ａ］である。図４には、酸化物半導体層の厚さＨが２０ｎｍ、５０ｎｍ、１００ｎｍの場合の電気的特性を示している。 The horizontal axis of the graph shown in FIG. 4 is the gate voltage Vg [V] applied to the gate electrode GE, and the vertical axis is the current Id [A] flowing between the source electrode SE and the drain electrode DE. FIG. 4 shows electrical characteristics in the case where the thickness H of the oxide semiconductor layer is 20 nm, 50 nm, and 100 nm.
図４に示すグラフによれば、酸化物半導体層の厚さＨが薄い程トランジスタがオンするときのゲート電圧Ｖｇがゼロに近い値となり、酸化物半導体層の厚さＨが厚くなる程トランジスタがオンするときのゲート電圧Ｖｇが負側へシフトする傾向がみられる。 According to the graph shown in FIG. 4, the gate voltage Vg when the transistor is turned on is closer to zero as the thickness H of the oxide semiconductor layer is smaller, and the transistor H There is a tendency that the gate voltage Vg when turning on shifts to the negative side.
すなわち、酸化物半導体層の厚さＨが大きくなるとトランジスタがノーマリオフとならず、トランジスタをオフするためには所定の電圧を印加しなければならなくなる。 That is, when the thickness H of the oxide semiconductor layer is increased, the transistor is not normally off, and a predetermined voltage must be applied to turn off the transistor.
図５は、トランジスタがオンのときとオフのときとの酸化物半導体層のキャリア濃度分布の一例を示す図である。ここでは、酸化物半導体層の厚さが略５０ｎｍの場合のキャリア濃度分布のシミュレーション結果を示している。 FIG. 5 is a diagram illustrating an example of the carrier concentration distribution of the oxide semiconductor layer when the transistor is on and when the transistor is off. Here, a simulation result of the carrier concentration distribution when the thickness of the oxide semiconductor layer is approximately 50 nm is shown.
図５に示すキャリア濃度分布では、酸化物半導体層における色が濃い部分でキャリア濃度が高く、色が薄い部分でキャリア濃度が低くなるようにグラデーションで表示している。ここで示す例（ｂ）では、ゲート電圧Ｖｇが２０Ｖであり、トランジスタがオンされている状態であって、酸化物半導体層のキャリア濃度は十分に高い状態となっている。ここで示す例（ａ）では、ゲート電圧Ｖｇが−４Ｖであり、酸化物半導体層は空乏化されキャリア濃度が低くなっている。このとき、酸化物半導体層の厚さが大きいと、ゲート電極ＧＥによる負バイアスが十分に大きくなければ酸化物半導体層の膜全体を空乏化できないため、酸化物半導体層の厚さが大きくなるほどトランジスタをオフするためのゲート電圧Ｖｇが負側へシフトすることとなる。 In the carrier concentration distribution shown in FIG. 5, the oxide semiconductor layer is displayed in gradation so that the carrier concentration is high in a dark portion and the carrier concentration is low in a light portion. In the example (b) shown here, the gate voltage Vg is 20 V, the transistor is on, and the carrier concentration of the oxide semiconductor layer is sufficiently high. In the example (a) shown here, the gate voltage Vg is −4 V, the oxide semiconductor layer is depleted, and the carrier concentration is low. At this time, if the thickness of the oxide semiconductor layer is large, the entire oxide semiconductor layer cannot be depleted unless the negative bias due to the gate electrode GE is sufficiently large. The gate voltage Vg for turning off is shifted to the negative side.
上記のことから、酸化物半導体層の膜厚を小さくすることにより、トランジスタの閾値電圧Ｖｔｈが負側へシフトすることを抑制することができる。しかしながら、コンタクト部ＣＴにおいて酸化物半導体層の膜厚が小さくなると、チャネル保護膜Ｌ２に開口を設ける際に精度が高度となり、開口が酸化物半導体層を貫通してしまうと、コンタクト抵抗が増加するだけでなく、ゲート電極とソース電極あるいはゲート電極とドレイン電極がショートし、歩留りも低下することとなる。本構造は、特にボトムゲート型のトランジスタにおいてゲート絶縁膜を薄くする場合に有効となる。エッチング加工によるダメージなく、極薄のチャネル部を形成できるため、プロセスマージンが広く、特性を制御し易い。 From the above, the threshold voltage Vth of the transistor can be prevented from shifting to the negative side by reducing the thickness of the oxide semiconductor layer. However, when the thickness of the oxide semiconductor layer is reduced in the contact portion CT, the accuracy becomes high when the opening is provided in the channel protective film L2, and when the opening penetrates the oxide semiconductor layer, the contact resistance increases. In addition, the gate electrode and the source electrode or the gate electrode and the drain electrode are short-circuited, resulting in a decrease in yield. This structure is particularly effective when the gate insulating film is thinned in a bottom gate type transistor. Since an extremely thin channel portion can be formed without damage caused by etching, the process margin is wide and the characteristics can be easily controlled.
そこで、本実施形態では、チャネル部ＣＮＬにおいて膜厚を小さくし、コンタクト部ＣＴはチャネル部ＣＮＬよりも膜厚が大きくなるように酸化物半導体層ＳＣを形成することにより、歩留りを低下させることなくトランジスタの電気的特性の劣化を抑制している。 Therefore, in the present embodiment, the thickness is reduced in the channel portion CNL, and the oxide semiconductor layer SC is formed so that the contact portion CT is thicker than the channel portion CNL, so that the yield is not reduced. Degradation of the electrical characteristics of the transistor is suppressed.
すなわち、本実施形態のトランジスタ、および、トランジスタの製造方法によれば、チャネル部ＣＮＬの酸化物半導体層は薄膜化により加熱処理（アニール）耐性が改善され、かつ、コンタクト部ＣＴの酸化物半導体層は低いコンタクト抵抗を実現することができる。さらに、トランジスタのチャネル長Ｌの増加なく、ソース電極ＳＥおよびドレイン電極ＤＥからチャネル部ＣＮＬを遠ざけることができ、拡散種による影響を低減することができるため、トランジスタの微細化を実現することができる。 That is, according to the transistor of the present embodiment and the method for manufacturing the transistor, the oxide semiconductor layer of the channel portion CNL has improved heat treatment (annealing) resistance by thinning, and the oxide semiconductor layer of the contact portion CT. Can realize low contact resistance. Further, the channel portion CNL can be moved away from the source electrode SE and the drain electrode DE without increasing the channel length L of the transistor, and the influence of the diffusion species can be reduced, so that the transistor can be miniaturized. .
上記のことから、本実施形態によれば、酸化物半導体を用いたときの電気的特性を改善したトランジスタ、および、トランジスタの製造法を提供することができる。 From the above, according to this embodiment, it is possible to provide a transistor with improved electrical characteristics when an oxide semiconductor is used, and a method for manufacturing the transistor.
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.
Ｌ１…ゲート絶縁膜、Ｌ２…チャネル保護膜、Ｌ３…パッシベーション膜、ＧＥ…ゲート電極、ＳＥ…ソース電極、ＤＥ…ドレイン電極、ＳＣ…酸化物半導体層、ＣＮＬ…チャネル部、ＣＴ…コンタクト部、ＣＴ１…第１コンタクト部、ＣＴ２…第２コンタクト部、Ｌ…チャネル長 L1 ... Gate insulating film, L2 ... Channel protective film, L3 ... Passivation film, GE ... Gate electrode, SE ... Source electrode, DE ... Drain electrode, SC ... Oxide semiconductor layer, CNL ... Channel part, CT ... Contact part, CT1 ... first contact part, CT2 ... second contact part, L ... channel length
Claims (11)
ゲート電極の上に設けられた第１絶縁層と、
前記第１絶縁層を介して前記ゲート電極上に配置され、第１コンタクト部と、第２コンタクト部と、前記第１コンタクト部と前記第２コンタクト部との間に配置されたチャネル部とを含み、前記チャネル部の膜厚が前記第１コンタクト部および前記第２コンタクト部の膜厚よりも小さい半導体層と、
前記半導体層を覆うとともに、前記第１コンタクト部および前記第２コンタクト部上に設けられた開口を備えたチャネル保護膜と、
前記チャネル保護膜の前記開口において前記第１コンタクト部と電気的に接続したソース電極と、
前記チャネル保護膜の前記開口において前記第２コンタクト部と電気的に接続したドレイン電極と、を備え、
前記半導体層は、Ｉｎ、Ｇａ、Ｚｎの少なくとも１つの材料を含む酸化物半導体である、トランジスタ。 A gate electrode;
A first insulating layer provided on the gate electrode;
A first contact portion, a second contact portion, and a channel portion disposed between the first contact portion and the second contact portion, disposed on the gate electrode via the first insulating layer; A semiconductor layer having a thickness of the channel portion smaller than that of the first contact portion and the second contact portion;
A channel protective film that covers the semiconductor layer and includes an opening provided on the first contact portion and the second contact portion;
A source electrode electrically connected to the first contact portion in the opening of the channel protective film;
A drain electrode electrically connected to the second contact portion in the opening of the channel protective film,
The transistor is a transistor in which the semiconductor layer is an oxide semiconductor including at least one material of In, Ga, and Zn.
前記ゲート電極上を用いてゲート絶縁膜を形成し、
前記ゲート絶縁膜上にＩｎ、Ｇａ、Ｚｎの少なくとも１つを含む酸化物半導体材料を成膜およびパターンニングして、第１コンタクト部および第２コンタクト部に配置された第１層を形成し、
前記第１層上に、Ｉｎ、Ｇａ、Ｚｎの少なくとも１つを含む酸化物半導体材料を成膜およびパターンニングして、第１コンタクト部、第２コンタクト部、および、チャネル部に配置された第２層を形成し、
前記第２層上に絶縁性材料を成膜するとともに、前記第１コンタクト部および前記第２コンタクト部上に開口を形成してチャネル保護膜を形成し、
前記チャネル保護膜上に導電性材料を成膜およびパターンニングして、前記開口において前記第１コンタクト部と電気的に接続したソース電極と、前記開口において前記ドレイン電極と電気的に接続したドレイン電極を形成する、トランジスタの製造方法。 Form a gate electrode using a conductive material,
Forming a gate insulating film on the gate electrode;
Forming and patterning an oxide semiconductor material containing at least one of In, Ga, and Zn on the gate insulating film to form a first layer disposed in the first contact portion and the second contact portion;
An oxide semiconductor material containing at least one of In, Ga, and Zn is formed and patterned on the first layer, and is disposed in the first contact portion, the second contact portion, and the channel portion. Forming two layers,
Forming an insulating material on the second layer and forming an opening on the first contact portion and the second contact portion to form a channel protective film;
Forming and patterning a conductive material on the channel protective film, a source electrode electrically connected to the first contact portion in the opening, and a drain electrode electrically connected to the drain electrode in the opening A method of manufacturing a transistor.
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