JP2017084962A - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents
配線基板、半導体装置及び配線基板の製造方法 Download PDFInfo
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- JP2017084962A JP2017084962A JP2015211723A JP2015211723A JP2017084962A JP 2017084962 A JP2017084962 A JP 2017084962A JP 2015211723 A JP2015211723 A JP 2015211723A JP 2015211723 A JP2015211723 A JP 2015211723A JP 2017084962 A JP2017084962 A JP 2017084962A
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- wiring pattern
- insulating layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 239000010410 layer Substances 0.000 claims description 275
- 229910052751 metal Inorganic materials 0.000 claims description 125
- 239000002184 metal Substances 0.000 claims description 125
- 239000002335 surface treatment layer Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 23
- 238000007788 roughening Methods 0.000 claims description 19
- 230000003746 surface roughness Effects 0.000 claims description 12
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract description 5
- 238000000576 coating method Methods 0.000 abstract description 5
- 239000011888 foil Substances 0.000 description 51
- 239000000463 material Substances 0.000 description 41
- 239000011347 resin Substances 0.000 description 38
- 229920005989 resin Polymers 0.000 description 38
- 230000008569 process Effects 0.000 description 26
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 22
- 239000010931 gold Substances 0.000 description 19
- 239000010949 copper Substances 0.000 description 16
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 14
- 229910000679 solder Inorganic materials 0.000 description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 238000007789 sealing Methods 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000007864 aqueous solution Substances 0.000 description 9
- 238000007747 plating Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 6
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 3
- -1 azole compound Chemical class 0.000 description 3
- 229960003280 cupric chloride Drugs 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- KAESVJOAVNADME-UHFFFAOYSA-N 1H-pyrrole Natural products C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 description 1
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920006290 polyethylene naphthalate film Polymers 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000012779 reinforcing material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Abstract
【解決手段】配線基板20は、半導体素子60が実装される実装領域よりも外側の領域に形成された接続パッド31と、実装領域内に形成されたパッド32と、接続パッド31とパッド32とを接続する回路パターン33とを有する配線パターン30を有する。配線基板20は、配線パターン30の下面及び側面を被覆し、配線パターン30の上面の一部を露出する絶縁層40を有する。絶縁層40は、配線パターン30の上面の外周縁全周を連続して被覆する被覆部41を有している。また、絶縁層40の上面40Aは、配線パターン30の上面よりも上方に形成されている。
【選択図】図2
Description
以下、図1〜図8に従って第1実施形態を説明する。
図2に示すように、半導体装置10は、配線基板20と、その配線基板20にフリップチップ実装された1つ又は複数(ここでは、1つ)の半導体素子60と、アンダーフィル材65と、封止樹脂66と、外部接続端子70とを有している。
以上説明したように、配線基板20では、1層の絶縁層40が、配線パターン30の4つの側面と下面と上面との6面に接触されている。すなわち、絶縁層40は、配線パターン30を取り囲むように形成されている。そして、絶縁層40、特に配線パターン30の上面と接触する被覆部41により、配線パターン30が係止されている。換言すると、各配線パターン30は、絶縁層40内に食い込んで形成され、上面の外縁部が絶縁層40の被覆部41に係止されている。このため、配線パターン30が絶縁層40から剥離することが好適に抑制される。
図5(a)に示すように、支持体80の下面にキャリア付金属箔81が貼着された支持基板を準備する。支持体80は、例えば、ガラス、アラミド、LCP(Liquid Crystal Polymer)繊維の織布や不織布などの補強材に、エポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂を含浸させたプリプレグである。キャリア付金属箔81は、支持体80の下面に貼着されたキャリア層82と、キャリア層82の下面に剥離層(図示略)を介して積層された極薄の金属箔83とを有している。キャリア層82は、金属箔83の取り扱いを容易にするための支持材として設けられている。キャリア層82は、例えば、厚さが15〜70μm程度の銅板である。金属箔83は、例えば、厚さが0.5〜5μm程度の銅箔である。
次に、半導体装置10の製造方法について説明する。
まず、図8(d)に示す工程では、柱状の接続端子61を有する半導体素子60を用意する。接続端子61は、公知の製造方法により製造することが可能であるため、図示を省略して詳細な説明を割愛するが、例えば以下のような方法で製造される。
続いて、配線基板20の絶縁層40上に、半導体素子60を封止する封止樹脂66(図2参照)を形成する。例えば、封止樹脂66の材料として熱硬化性を有したモールド樹脂を用いる場合には、アンダーフィル材65を形成した構造体を金型内に収容し、その金型内に圧力(例えば、5〜10MPa)を印加し、流動化したモールド樹脂を導入する。その後、モールド樹脂を180℃程度の温度で加熱して硬化させることで、封止樹脂66を形成する。なお、モールド樹脂を充填する方法としては、例えば、トランスファーモールド法、コンプレッションモールド法やインジェクションモールド法などの方法を用いることができる。
以上説明した本実施形態によれば、以下の効果を奏することができる。
(1)配線パターン30の下面及び側面を被覆する絶縁層40に、配線パターン30の上面の外縁部全周を連続して被覆する被覆部41を設けた。これにより、絶縁層40が配線パターン30の4つの側面と下面と上面との6面に接触され、その絶縁層40によって配線パターン30が係止される。このため、配線パターン30が絶縁層40から剥離することを好適に抑制することができる。
以下、図9〜図12に従って第3実施形態を説明する。この実施形態の半導体装置10Aは、配線基板20Aの配線パターン30の構成が上記第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。先の図1〜図8に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
以下、図13に従って第3実施形態について説明する。この実施形態では、配線基板20の製造方法が第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。先の図1〜図12に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
次に、図13(b)に示す工程では、図13(a)に示した構造体の下面側に露出している金属層のうちCu層、ここでは配線パターン30及び金属箔83に対して選択的に粗化処理を施す。この粗化処理により、各配線パターン30の下面及び側面に微細な凹凸が形成され、それら各配線パターン30の下面全面及び側面全面が粗化面30Rに形成される。さらに、凹部84Xに露出された各配線パターン30の上面にも微細な凹凸が形成され、それら各配線パターン30の上面の一部も粗化面30Rに形成される。また、粗化処理により、凹部84Xの底部に露出する金属箔83の下面83Aに微細な凹凸が形成され、その金属箔83の下面83Aが粗化面83Rに形成される。例えば、粗化前の(または、金属膜84に被覆された)配線パターン30及び金属箔83の表面の粗度が表面粗さRa値で1〜300nm程度であるのに対し、粗化処理により配線パターン30及び金属箔83の表面の粗度を表面粗さRa値で100〜700nm程度とすることができる。換言すると、本工程では、外部に露出された配線パターン30及び金属箔83の表面の粗度が、表面粗さRa値で100〜150nm程度となるように粗化が行われる。ここで、表面粗さRa値とは、表面粗さを表わす数値の一種であり、算術平均粗さと呼ばれるものであって、具体的には測定領域内で変化する高さの絶対値を平均ラインである表面から測定して算術平均したものである。
以上説明した実施形態によれば、第1実施形態の(1)〜(5)の効果に加えて以下の効果を奏することができる。
なお、上記各実施形態は、これを適宜変更した以下の態様にて実施することもできる。
・図14に示す製造工程により配線基板20を形成するようにしてもよい。なお、図14(a)は、先の図13(b)に示した工程の代わりに実施される。
以上説明した製造方法により製造された配線基板20では、絶縁層40の上面40Aと突出部42の側面とを粗化面40Rとしたため、絶縁層40とアンダーフィル材65との密着性をより向上させることができる。
・上記各実施形態におけるアンダーフィル材65を省略してもよい。この場合には、例えば、封止樹脂66によって、配線基板20,20A,20Bと半導体素子60との隙間を封止するようにしてもよい。
・上記各実施形態では、支持基板の片側(一方の面)に配線パターン30及び絶縁層40を積層し、最後に支持基板を除去してコアレスの配線基板20を製造するようにした。これに限らず、例えば、支持基板の両側(一方の面及び他方の面)に金属膜84を形成し、それら両側の金属膜84上に配線パターン30及び絶縁層40を積層し、最後に支持基板及び金属膜84を除去して複数のコアレスの配線基板20を製造するようにしてもよい。
・上記各実施形態では、絶縁層40から露出する配線パターン30の上面の一部に表面処理層52を形成するようにした。これに限らず、例えば、絶縁層40から露出する配線パターン30(接続パッド31、パッド32及び回路パターン33)の上面全面を被覆するように表面処理層52に形成するようにしてもよい。
・上記各実施形態における表面処理層52を省略してもよい。
・上記各実施形態における配線基板20,20A,20Bにおける配線パターンの取り回しなどは様々に変形・変更することが可能である。
20,20A,20B 配線基板
30 配線パターン
30R 粗化面
31 接続パッド
32 パッド
33 回路パターン
40 絶縁層
40A 上面
40R 粗化面
41 被覆部
51 表面処理層
52 表面処理層
60 半導体素子
80 支持体(支持基板)
81 キャリア付金属箔(支持基板)
82 キャリア層
83 金属箔
84 金属膜
84X 凹部
Claims (10)
- 電子部品が実装される実装領域内に形成されたパッドと、前記パッドから平面方向に延出された回路パターンとを有する配線パターンと、
前記配線パターンの下面及び側面を被覆し、前記配線パターンの上面の一部を露出する絶縁層と、を有し、
前記絶縁層は、前記配線パターンの上面の外縁部全周を連続して被覆する被覆部を有し、
前記絶縁層の上面は、前記配線パターンの上面よりも上方に形成されていることを特徴とする配線基板。 - 前記被覆部の側面は、凸型R形状に形成されていることを特徴とする請求項1に記載の配線基板。
- 前記絶縁層と接する前記配線パターンの表面全面は、前記絶縁層から露出された前記配線パターンの上面よりも表面粗度の大きい粗化面であることを特徴とする請求項1又は2に記載の配線基板。
- 前記絶縁層の上面は、前記絶縁層から露出された前記配線パターンの上面よりも表面粗度の大きい粗化面であることを特徴とする請求項1〜3のいずれか一項に記載の配線基板。
- 前記配線パターンは、前記回路パターンを介して前記パッドと接続された接続パッドを有し、
前記絶縁層は、前記接続パッドの下面の一部を露出する貫通孔を有することを特徴とする請求項1〜4のいずれか一項に記載の配線基板。 - 前記貫通孔に露出された前記接続パッドの下面に形成された表面処理層と、
前記絶縁層から露出された前記パッドの上面に形成された表面処理層と、
を有することを特徴とする請求項5に記載の配線基板。 - 請求項1〜6のいずれか一項に記載の配線基板と、
前記パッドと電気的に接続され、前記配線基板に実装された半導体素子と、を有することを特徴とする半導体装置。 - 支持基板を準備する工程と、
前記支持基板の下面に金属膜を形成する工程と、
前記金属膜の下面に配線パターンを形成する工程と、
前記配線パターンをマスクにして、前記金属膜を前記配線パターン及び前記支持基板に対して選択的に除去し、前記配線パターンの上面の外縁部を露出する凹部を前記金属膜に形成する工程と、
前記配線パターンの下面全面及び側面全面を被覆するとともに、前記凹部を充填する絶縁層を形成する工程と、
前記支持基板を除去する工程と、
前記金属膜を除去する工程と、を有し、
前記絶縁層には、前記配線パターンの上面の外縁部全周を連続して被覆する被覆部が形成されることを特徴とする配線基板の製造方法。 - 前記凹部を形成する工程の後であって、前記絶縁層を形成する工程の前に、前記配線パターンと前記凹部に露出する前記支持基板とに対して選択的に粗化処理を施す工程を有することを特徴とする請求項8に記載の配線基板の製造方法。
- 前記凹部を形成する工程では、等方性エッチングにより、前記金属膜を除去して前記凹部を形成することを特徴とする請求項8又は9に記載の配線基板の製造方法。
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