JP2017005137A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2017005137A
JP2017005137A JP2015118324A JP2015118324A JP2017005137A JP 2017005137 A JP2017005137 A JP 2017005137A JP 2015118324 A JP2015118324 A JP 2015118324A JP 2015118324 A JP2015118324 A JP 2015118324A JP 2017005137 A JP2017005137 A JP 2017005137A
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opening
base plate
solder
solder resist
insulating substrate
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慎吾 井上
Shingo Inoue
慎吾 井上
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Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same capable of suppressing generation of solder balls while securing the positioning property of an insulation substrate.SOLUTION: A solder resist 2 is formed on a base plate 1. The solder resist 2 has an opening 3. In the opening 3 of the solder resist 2, an insulation substrate 5 is bonded on the base plate 1 via solder 4. The opening 3 of the solder resist 2 has a rectangle region 3a and enlarged regions 3b where central parts of sides of the rectangle region 3a are enlarged.SELECTED DRAWING: Figure 2

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

産業機器や民生機器のモータ制御にパワーモジュールが用いられている。パワーモジュールの製造工程においてベース板上に絶縁基板をはんだ付けする。この際、絶縁基板の位置決めのためにソルダーレジストを塗布している（例えば、特許文献１参照）。従来、ソルダーレジストの開口の形状は絶縁基板の外形と同じであった。   Power modules are used for motor control of industrial equipment and consumer equipment. In the power module manufacturing process, an insulating substrate is soldered on the base plate. At this time, a solder resist is applied to position the insulating substrate (see, for example, Patent Document 1). Conventionally, the shape of the opening of the solder resist is the same as the outer shape of the insulating substrate.

特開平４−１５２６６３号公報Japanese Patent Laid-Open No. 4-152663

はんだ溶融時やボイドが抜ける際にソルダーレジストによってはんだの表面張力が増大し、はんだが噴出して、はんだボールが発生する。このため、部品、装置、治具等にはんだが付着し手直しや不良が発生するという問題があった。   When the solder is melted or the void is removed, the solder resist increases the surface tension of the solder, and the solder is ejected to generate solder balls. For this reason, there is a problem that solder adheres to parts, devices, jigs, etc., and rework or defects occur.

本発明は、上述のような課題を解決するためになされたもので、その目的は絶縁基板の位置決め性を確保しつつ、はんだボールの発生を抑制することができる半導体装置及びその製造方法を得るものである。   The present invention has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device capable of suppressing the generation of solder balls while ensuring the positioning of an insulating substrate, and a method for manufacturing the same. Is.

本発明に係る半導体装置は、ベース板と、前記ベース板上に形成され、開口を有するソルダーレジストと、前記ソルダーレジストの前記開口内において前記ベース板上にはんだを介して接合された絶縁基板とを備え、前記開口は、四角領域と、前記四角領域の辺の中央部を拡大した拡大領域とを有することを特徴とする。   A semiconductor device according to the present invention includes a base plate, a solder resist formed on the base plate and having an opening, and an insulating substrate joined to the base plate via solder in the opening of the solder resist. The opening has a square region and an enlarged region obtained by enlarging a central portion of a side of the square region.

本発明により、絶縁基板の位置決め性を確保しつつ、はんだボールの発生を抑制することができる。   According to the present invention, it is possible to suppress the generation of solder balls while ensuring the positioning of the insulating substrate.

本発明の実施の形態１に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置のソルダーレジストを示す平面図である。It is a top view which shows the soldering resist of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体装置のソルダーレジストを示す平面図である。It is a top view which shows the soldering resist of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体装置の製造方法を示す平面図である。It is a top view which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る半導体装置の製造方法を示す平面図である。It is a top view which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention.

本発明の実施の形態に係る半導体装置及びその製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す断面図である。ベース板１上にソルダーレジスト２が形成されている。ソルダーレジスト２は開口３を有する。ソルダーレジスト２の開口３内においてベース板１上にはんだ４を介して絶縁基板５が接合されている。絶縁基板５は、上面側に設けられた上面電極６と、下面側に設けられた下面電極７とを有する。絶縁基板５の下面電極７がはんだ４によりベース板１の上面に接合されている。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. A solder resist 2 is formed on the base plate 1. The solder resist 2 has an opening 3. An insulating substrate 5 is joined to the base plate 1 via the solder 4 in the opening 3 of the solder resist 2. The insulating substrate 5 has an upper surface electrode 6 provided on the upper surface side and a lower surface electrode 7 provided on the lower surface side. The lower surface electrode 7 of the insulating substrate 5 is joined to the upper surface of the base plate 1 by the solder 4.

図２は、本発明の実施の形態１に係る半導体装置のソルダーレジストを示す平面図である。ソルダーレジスト２の開口３は、正方形又は長方形の四角領域３ａと、四角領域３ａの辺の中央部を拡大した拡大領域３ｂとを有する。四角領域３ａは絶縁基板５の下面電極７の外形サイズとほぼ同じである。絶縁基板５は四角領域３ａ内でベース板１に接合されるが、拡大領域３ｂ内ではベース板１に接合されない。拡大領域３ｂは、四角領域３ａの四辺の中央部から外側に延びて開口３の外形を拡大している。   FIG. 2 is a plan view showing the solder resist of the semiconductor device according to the first embodiment of the present invention. The opening 3 of the solder resist 2 includes a square or rectangular square area 3a and an enlarged area 3b obtained by enlarging the central portion of the side of the square area 3a. The square region 3 a is substantially the same as the outer size of the lower surface electrode 7 of the insulating substrate 5. The insulating substrate 5 is bonded to the base plate 1 in the square region 3a, but is not bonded to the base plate 1 in the enlarged region 3b. The enlarged region 3b extends outward from the center of the four sides of the square region 3a to enlarge the outer shape of the opening 3.

ベース板１と絶縁基板５をはんだ４で接合するが、はんだ４の溶融時にソルダーレジスト２とはんだ４の界面で表面張力が発生する。しかし、はんだ４が拡大領域３ｂに流れることにより、はんだ４の表面張力を緩和してはんだボールの発生を抑制することができる。また、開口３の四隅の外形を残すことで、ソルダーレジスト２の本来の目的である絶縁基板５の位置決め性を確保することができる。   The base plate 1 and the insulating substrate 5 are joined with the solder 4, and surface tension is generated at the interface between the solder resist 2 and the solder 4 when the solder 4 is melted. However, when the solder 4 flows into the enlarged region 3b, the surface tension of the solder 4 can be relaxed and the generation of solder balls can be suppressed. Further, by leaving the outer shapes of the four corners of the opening 3, it is possible to ensure the positioning of the insulating substrate 5 which is the original purpose of the solder resist 2.

実施の形態２．
図３は、本発明の実施の形態２に係る半導体装置のソルダーレジストを示す平面図である。ソルダーレジスト２の開口３は、正方形又は長方形の四角領域３ａと、四角領域３ａの四隅を拡大した拡大領域３ｂとを有する。拡大領域３ｂは、四隅から外側に延びて開口３の外形を拡大している。その他の構成は実施の形態１と同様である。 Embodiment 2. FIG.
FIG. 3 is a plan view showing a solder resist of the semiconductor device according to the second embodiment of the present invention. The opening 3 of the solder resist 2 includes a square or rectangular square area 3a and an enlarged area 3b obtained by enlarging the four corners of the square area 3a. The enlarged region 3b extends outward from the four corners to enlarge the outer shape of the opening 3. Other configurations are the same as those of the first embodiment.

はんだ４の溶融時にはんだ４が拡大領域３ｂに流れることにより、はんだ４の表面張力を緩和してはんだボールの発生を抑制することができる。また、四角領域３ａの四辺の中央部の外形を残すことで、ソルダーレジスト２の本来の目的である絶縁基板５の位置決め性を確保することができる。また、本実施の形態は絶縁基板５の角部近傍へのはんだボールの付着を抑えたいときに特に有効である。   By flowing the solder 4 to the enlarged region 3b when the solder 4 is melted, the surface tension of the solder 4 can be relaxed and the generation of solder balls can be suppressed. Further, by leaving the outer shape of the central part of the four sides of the square region 3a, the positioning of the insulating substrate 5 which is the original purpose of the solder resist 2 can be ensured. Further, this embodiment is particularly effective when it is desired to suppress the adhesion of solder balls near the corners of the insulating substrate 5.

実施の形態３．
図４は、本発明の実施の形態３に係る半導体装置の製造方法を示す平面図である。図５は、本発明の実施の形態３に係る半導体装置の製造方法を示す断面図である。 Embodiment 3 FIG.
FIG. 4 is a plan view showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention. FIG. 5 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention.

まず、図４に示すように、ベース板１上に、開口８を有する位置決め治具９を配置する。位置決め治具９の材質はアルミニウムや、カーボンなど、はんだが付着しない材質である。次に、図５に示すように、位置決め治具９の開口８内においてベース板１上にはんだ４を介して絶縁基板５を接合する。位置決め治具９の開口８は、四角領域８ａと、四角領域８ａの辺の中央部を拡大した拡大領域８ｂとを有する。四角領域８ａは絶縁基板５の外形サイズとほぼ同じである。絶縁基板５は四角領域８ａ内に実装され、拡大領域８ｂ内には実装されない。拡大領域８ｂは、四角領域８ａの四辺の中央部から外側に延びて開口８の外形を拡大している。   First, as shown in FIG. 4, a positioning jig 9 having an opening 8 is arranged on the base plate 1. The material of the positioning jig 9 is a material to which solder does not adhere, such as aluminum or carbon. Next, as shown in FIG. 5, the insulating substrate 5 is joined to the base plate 1 via the solder 4 in the opening 8 of the positioning jig 9. The opening 8 of the positioning jig 9 has a square area 8a and an enlarged area 8b obtained by enlarging the central portion of the side of the square area 8a. The square region 8a is substantially the same as the outer size of the insulating substrate 5. The insulating substrate 5 is mounted in the square area 8a and is not mounted in the enlarged area 8b. The enlarged region 8b extends outward from the center of the four sides of the square region 8a to enlarge the outer shape of the opening 8.

実施の形態１と同様に、拡大領域８ｂを設けることによりはんだボールの発生を抑制することができる。また、位置決め治具９により絶縁基板５の位置決め性を確保することができる。さらに、ソルダーレジスト自体が不要なため、ソルダーレジスト塗布工数と材料費を抑えることができる。   As in the first embodiment, the generation of solder balls can be suppressed by providing the enlarged region 8b. In addition, the positioning jig 9 can ensure the positioning of the insulating substrate 5. Furthermore, since the solder resist itself is unnecessary, the number of solder resist coating steps and material costs can be reduced.

実施の形態４．
図６は、本発明の実施の形態４に係る半導体装置の製造方法を示す平面図である。位置決め治具９の開口８は、四角領域８ａと、四角領域８ａの四隅を拡大した拡大領域８ｂとを有する。拡大領域８ｂは、四角領域８ａの四隅から外側に延びて開口８の外形を拡大している。その他の構成は実施の形態３と同様である。 Embodiment 4 FIG.
FIG. 6 is a plan view showing the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention. The opening 8 of the positioning jig 9 has a square area 8a and an enlarged area 8b obtained by enlarging the four corners of the square area 8a. The enlarged region 8b extends outward from the four corners of the square region 8a to enlarge the outer shape of the opening 8. Other configurations are the same as those of the third embodiment.

実施の形態２と同様に、拡大領域８ｂを設けることによりはんだボールの発生を抑制することができ、絶縁基板５の角部近傍へのはんだボールの付着を抑えたいときに特に有効である。また、位置決め治具９により絶縁基板５の位置決め性を確保することができる。さらに、ソルダーレジスト自体が不要なため、ソルダーレジスト塗布工数と材料費を抑えることができる。   As in the second embodiment, the formation of the enlarged region 8b can suppress the generation of solder balls, and is particularly effective when it is desired to suppress the adhesion of solder balls near the corners of the insulating substrate 5. In addition, the positioning jig 9 can ensure the positioning of the insulating substrate 5. Furthermore, since the solder resist itself is unnecessary, the number of solder resist coating steps and material costs can be reduced.

なお、実施の形態１〜４において、開口３，８とそれに実装する絶縁基板５が２組の場合について説明した。これに限らず、開口３，８と絶縁基板５が１組でもよいし、３組以上でもよい。   In the first to fourth embodiments, the case where two sets of the openings 3 and 8 and the insulating substrate 5 mounted thereon has been described. Not only this but 1 set of openings 3 and 8 and insulating substrate 5 may be sufficient, and 3 or more sets may be sufficient.

１ ベース板、２ ソルダーレジスト、３ 開口、３ａ 四角領域、３ｂ 拡大領域、４ はんだ、８ 開口、８ａ 四角領域、８ｂ 拡大領域、９ 位置決め治具 1 Base plate, 2 Solder resist, 3 Aperture, 3a Square area, 3b Enlarged area, 4 Solder, 8 Opening, 8a Square area, 8b Enlarged area, 9 Positioning jig

Claims (4)

ベース板と、
前記ベース板上に形成され、開口を有するソルダーレジストと、
前記ソルダーレジストの前記開口内において前記ベース板上にはんだを介して接合された絶縁基板とを備え、
前記開口は、四角領域と、前記四角領域の辺の中央部を拡大した拡大領域とを有することを特徴とする半導体装置。 A base plate,
A solder resist formed on the base plate and having an opening;
An insulating substrate joined via solder on the base plate in the opening of the solder resist;
The opening includes a square region and an enlarged region obtained by enlarging a central portion of a side of the square region. ベース板と、
前記ベース板上に形成され、開口を有するソルダーレジストと、
前記ソルダーレジストの前記開口内において前記ベース板上にはんだを介して接合された絶縁基板とを備え、
前記開口は、四角領域と、前記四角領域の四隅を拡大した拡大領域とを有することを特徴とする半導体装置。 A base plate,
A solder resist formed on the base plate and having an opening;
An insulating substrate joined via solder on the base plate in the opening of the solder resist;
The opening has a square region and an enlarged region obtained by enlarging the four corners of the square region. ベース板上に、開口を有する位置決め治具を配置する工程と、
前記位置決め治具の前記開口内において前記ベース板上にはんだを介して絶縁基板を接合する工程とを備え、
前記開口は、四角領域と、前記四角領域の辺の中央部を拡大した拡大領域とを有することを特徴とする半導体装置の製造方法。 Placing a positioning jig having an opening on the base plate;
A step of joining an insulating substrate to the base plate via solder in the opening of the positioning jig,
The said opening has a square area | region and the enlarged area which expanded the center part of the side of the said square area | region, The manufacturing method of the semiconductor device characterized by the above-mentioned. ベース板上に、開口を有する位置決め治具を配置する工程と、
前記位置決め治具の前記開口内において前記ベース板上にはんだを介して絶縁基板を接合する工程とを備え、
前記開口は、四角領域と、前記四角領域の四隅を拡大した拡大領域とを有することを特徴とする半導体装置の製造方法。 Placing a positioning jig having an opening on the base plate;
A step of joining an insulating substrate to the base plate via solder in the opening of the positioning jig,
The manufacturing method of a semiconductor device, wherein the opening includes a square region and an enlarged region obtained by enlarging the four corners of the square region.
JP2015118324A 2015-06-11 2015-06-11 Semiconductor device and method of manufacturing the same Pending JP2017005137A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018202490A1 (en) 2017-04-17 2018-10-18 Fuji Electric Co., Ltd. Semiconductor device

Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2010062248A (en) * 2008-09-02 2010-03-18 Shindengen Electric Mfg Co Ltd Positioning tool unit and soldering method
JP2011100864A (en) * 2009-11-06 2011-05-19 Toshiba Corp Semiconductor device and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010062248A (en) * 2008-09-02 2010-03-18 Shindengen Electric Mfg Co Ltd Positioning tool unit and soldering method
JP2011100864A (en) * 2009-11-06 2011-05-19 Toshiba Corp Semiconductor device and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018202490A1 (en) 2017-04-17 2018-10-18 Fuji Electric Co., Ltd. Semiconductor device
JP2018182143A (en) * 2017-04-17 2018-11-15 富士電機株式会社 Semiconductor device
US10692800B2 (en) 2017-04-17 2020-06-23 Fuji Electric Co., Ltd. Semiconductor device having substrate and base plate joined by joining member

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