JP2016213349A - 貫通電極及びその製造方法、並びに半導体装置及びその製造方法 - Google Patents
貫通電極及びその製造方法、並びに半導体装置及びその製造方法 Download PDFInfo
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- JP2016213349A JP2016213349A JP2015096523A JP2015096523A JP2016213349A JP 2016213349 A JP2016213349 A JP 2016213349A JP 2015096523 A JP2015096523 A JP 2015096523A JP 2015096523 A JP2015096523 A JP 2015096523A JP 2016213349 A JP2016213349 A JP 2016213349A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 113
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000012792 core layer Substances 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 14
- 239000010949 copper Substances 0.000 claims description 23
- 230000035515 penetration Effects 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000008646 thermal stress Effects 0.000 abstract description 19
- 238000009826 distribution Methods 0.000 abstract description 5
- 238000005457 optimization Methods 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 26
- 230000000052 comparative effect Effects 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 238000004458 analytical method Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 241000724291 Tobacco streak virus Species 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 230000000930 thermomechanical effect Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000009623 Bosch process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- 229910004813 CaTe Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020830 Sn-Bi Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910018728 Sn—Bi Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 239000007769 metal material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- 230000000149 penetrating effect Effects 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
実施例では、半導体基板10は単結晶シリコンとし、コア層12は銅とし、半導体層13はシリコン層とし、絶縁層14は酸化シリコンとした。実施例の貫通電極11の各種寸法は、表1に示す通りである。具体的には、貫通電極11の径Dを5,10,15,20μmと変化させた。貫通電極11のピッチPは径Dの2倍に設定し、高さHを40μmとし、絶縁層14の厚さを0.5μmとし、半導体層13の厚さを1μmとした。
比較例として、従来構造として一般的な銅層と、銅層の側面を被覆する絶縁層からなる貫通電極を設定した。比較例の貫通電極の設計は、半導体層がない点を除き、表1に示す条件を採用した。
Claims (9)
- 半導体基板に絶縁層を介して形成された貫通電極であって、
導電性のコア層と、
前記コア層と前記絶縁層との間に形成され、前記半導体基板と同じ材料を含む筒形状の半導体層と、
を有する、貫通電極。 - 前記コア層は、銅を含む、
請求項1記載の貫通電極。 - 前記絶縁層は、酸化シリコンを含む、
請求項1又は2に記載の貫通電極。 - 前記半導体基板及び前記半導体層は、シリコンを含む、
請求項1〜3のいずれかに記載の貫通電極。 - 請求項1〜4のいずれかに記載の貫通電極を備える半導体装置。
- 半導体基板に筒形状の溝部を形成する工程と、
前記溝部に絶縁層を埋め込む工程と、
前記絶縁層の内側にスルーホールを形成し、かつ、前記絶縁層とスルーホールとの間に前記半導体基板の一部からなる筒形状の半導体層を形成する工程と、
前記スルーホールに導電性材料を埋め込み、コア層を形成する工程と、
を有する貫通電極の製造方法。 - 前記溝部に絶縁層を埋め込む工程において、前記溝部に酸化シリコンを含む絶縁層を埋め込む、
請求項6に記載の貫通電極の製造方法。 - 前記コア層を形成する工程において、銅を含む前記導電性材料を埋め込む、
請求項6又は7に記載の貫通電極の製造方法。 - 請求項6〜8のいずれかに記載の貫通電極の製造方法を含む、半導体装置の製造方法。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110943052A (zh) * | 2018-09-25 | 2020-03-31 | 精材科技股份有限公司 | 晶片封装体及其制造方法 |
CN112599491A (zh) * | 2020-12-15 | 2021-04-02 | 西安电子科技大学 | 基于低热应力硅通孔的硅基板 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009124087A (ja) * | 2007-11-19 | 2009-06-04 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP2010010324A (ja) * | 2008-06-26 | 2010-01-14 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2012222141A (ja) * | 2011-04-08 | 2012-11-12 | Elpida Memory Inc | 半導体チップ |
JP2013125831A (ja) * | 2011-12-14 | 2013-06-24 | Elpida Memory Inc | 半導体装置の製造方法及び半導体装置 |
JP2014022637A (ja) * | 2012-07-20 | 2014-02-03 | Ps4 Luxco S A R L | 半導体装置及びその製造方法 |
JP2014120504A (ja) * | 2012-12-13 | 2014-06-30 | Renesas Electronics Corp | 半導体装置 |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009124087A (ja) * | 2007-11-19 | 2009-06-04 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP2010010324A (ja) * | 2008-06-26 | 2010-01-14 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2012222141A (ja) * | 2011-04-08 | 2012-11-12 | Elpida Memory Inc | 半導体チップ |
JP2013125831A (ja) * | 2011-12-14 | 2013-06-24 | Elpida Memory Inc | 半導体装置の製造方法及び半導体装置 |
JP2014022637A (ja) * | 2012-07-20 | 2014-02-03 | Ps4 Luxco S A R L | 半導体装置及びその製造方法 |
JP2014120504A (ja) * | 2012-12-13 | 2014-06-30 | Renesas Electronics Corp | 半導体装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110943052A (zh) * | 2018-09-25 | 2020-03-31 | 精材科技股份有限公司 | 晶片封装体及其制造方法 |
JP2020077855A (ja) * | 2018-09-25 | 2020-05-21 | 精材科技股▲ふん▼有限公司 | チップパッケージおよびその製造方法 |
CN110943052B (zh) * | 2018-09-25 | 2022-07-29 | 精材科技股份有限公司 | 晶片封装体及其制造方法 |
US11450697B2 (en) | 2018-09-25 | 2022-09-20 | Xintec Inc. | Chip package with substrate having first opening surrounded by second opening and method for forming the same |
CN112599491A (zh) * | 2020-12-15 | 2021-04-02 | 西安电子科技大学 | 基于低热应力硅通孔的硅基板 |
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