JP2016162814A - Semiconductor package and solder packaging method - Google Patents

Semiconductor package and solder packaging method Download PDF

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Publication number
JP2016162814A
JP2016162814A JP2015038232A JP2015038232A JP2016162814A JP 2016162814 A JP2016162814 A JP 2016162814A JP 2015038232 A JP2015038232 A JP 2015038232A JP 2015038232 A JP2015038232 A JP 2015038232A JP 2016162814 A JP2016162814 A JP 2016162814A
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Prior art keywords
solder
pin
substrate
hole
mother board
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JP6492768B2 (en
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菅田　隆
Takashi Sugata
隆 菅田
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Fujitsu Ltd
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Fujitsu Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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Abstract

PROBLEM TO BE SOLVED: To reduce stress occurring in solder balls for joining substrates.SOLUTION: A semiconductor package includes: a first substrate on which a semiconductor chip is mounted; solder balls formed on the first substrate; and pins inserted into through holes penetrating through the second substrate which is disposed facing the first substrate. The pins are joined to the solder balls.SELECTED DRAWING: Figure 1

Description

本発明は、半導体パッケージ及びはんだ実装方法に関する。   The present invention relates to a semiconductor package and a solder mounting method.

ＬＳＩ（Large Scale Integration）等の半導体チップを備える半導体パッケージの構
造の一例として、ＢＧＡ（Ball Grid Array）パッケージがある。ＢＧＡパッケージは、
パッケージ基板の底面に半球状の外部入出力端子（はんだボール）がアレイ状に配設されている。図１８は、ＢＧＡパッケージの一例を示す断面図である。図１８に示すように、ＢＧＡパッケージ１０１は、パッケージ基板１０２と、パッケージ基板１０２上に搭載されたＬＳＩチップ１０３と、ＬＳＩチップ１０３と電気的に接続されたはんだボール１０４とを備える。また、パッケージ基板１０２上には、ＬＳＩチップ１０３の熱を放熱するヒートスプレッダ１０５が搭載されている。 As an example of the structure of a semiconductor package including a semiconductor chip such as an LSI (Large Scale Integration), there is a BGA (Ball Grid Array) package. BGA package is
Hemispherical external input / output terminals (solder balls) are arranged in an array on the bottom surface of the package substrate. FIG. 18 is a cross-sectional view showing an example of a BGA package. As shown in FIG. 18, the BGA package 101 includes a package substrate 102, an LSI chip 103 mounted on the package substrate 102, and solder balls 104 that are electrically connected to the LSI chip 103. A heat spreader 105 that dissipates heat from the LSI chip 103 is mounted on the package substrate 102.

特開平５−２９１４３２号公報JP-A-5-291432 特開平７−２０２３７８号公報JP-A-7-202378 特開２００１−４４３２６号公報JP 2001-44326 A 特開２００８−１３５６５０号公報JP 2008-135650 A

近年、半導体パッケージのパッケージサイズの大型化により、パッケージ基板の反りが大きくなってきている。このため、マザーボードへの半導体パッケージの実装が困難となり、半導体パッケージの実装歩留まりが低下する。また、マザーボードへの半導体パッケージの実装におけるリフロー処理の際、半導体パッケージ及びマザーボードが反る。リフロー処理の加熱が終わると、パッケージ基板とマザーボードとを接合するはんだボールが固まって、半導体パッケージ及びマザーボードの反りが元に戻る。このとき、半導体パッケージの基板の熱膨張係数とマザーボードのプリント基板の熱膨張係数とが異なることから、半導体パッケージとマザーボードの反りが元に戻る（縮む）量が、それぞれ異なる。そのため、はんだボールに発生する応力が増加する。例えば、パッケージ基板の熱膨張係数は８〜１２ｐｐｍ／℃であり、マザーボードの熱膨張係数は１５〜１８ｐｐｍ／℃である。その結果、パッケージ基板とマザーボードとを接合するはんだボールにクラックが発生し、半導体パッケージの実装歩留まりが低下する。   In recent years, the warpage of the package substrate has been increased due to the increase in the package size of the semiconductor package. For this reason, it becomes difficult to mount the semiconductor package on the mother board, and the mounting yield of the semiconductor package decreases. In addition, the semiconductor package and the motherboard warp during the reflow process in mounting the semiconductor package on the motherboard. When the reflow process is finished, the solder balls that join the package substrate and the mother board are solidified, and the warpage of the semiconductor package and the mother board is restored. At this time, since the thermal expansion coefficient of the substrate of the semiconductor package and the thermal expansion coefficient of the printed circuit board of the mother board are different, the amounts of the warpage of the semiconductor package and the mother board returning (shrinking) are different. Therefore, the stress generated in the solder ball increases. For example, the thermal expansion coefficient of the package substrate is 8 to 12 ppm / ° C., and the thermal expansion coefficient of the motherboard is 15 to 18 ppm / ° C. As a result, cracks occur in the solder balls that join the package substrate and the mother board, and the mounting yield of the semiconductor package decreases.

本願は、基板同士を接合するはんだボールに発生する応力を低減することを目的とする。   This application aims at reducing the stress which generate | occur | produces in the solder ball which joins substrates.

本願の一観点による半導体パッケージは、半導体チップが搭載された第１基板と、前記第１基板に形成されたはんだボールと、前記第１基板と対向するように配置された第２基板を貫通するスルーホールに挿入されたピンと、を備え、前記ピンは、前記はんだボールに接合されている。   A semiconductor package according to an aspect of the present application penetrates a first substrate on which a semiconductor chip is mounted, solder balls formed on the first substrate, and a second substrate disposed so as to face the first substrate. A pin inserted into the through hole, and the pin is joined to the solder ball.

本願によれば、ピンが基板の反りを吸収し、基板同士を接合するはんだボールに発生する応力を低減することができる。   According to the present application, the pins absorb the warp of the substrates, and the stress generated in the solder balls that join the substrates can be reduced.

図１は、実施例１に係る電子装置の断面図である。FIG. 1 is a cross-sectional view of the electronic device according to the first embodiment. 図２は、マザーボードの部分断面図である。FIG. 2 is a partial cross-sectional view of the motherboard. 図３は、実施例１に係る電子装置の製造工程図である。FIG. 3 is a manufacturing process diagram of the electronic device according to the first embodiment. 図４は、実施例１に係る電子装置の製造工程図である。FIG. 4 is a manufacturing process diagram of the electronic device according to the first embodiment. 図５は、実施例１に係る電子装置の製造工程図である。FIG. 5 is a manufacturing process diagram of the electronic device according to the first embodiment. 図６は、実施例１に係る電子装置の製造工程図である。FIG. 6 is a manufacturing process diagram of the electronic device according to the first embodiment. 図７は、マザーボードの部分断面図である。FIG. 7 is a partial cross-sectional view of the motherboard. 図８は、実施例１に係る電子装置の断面図である。FIG. 8 is a cross-sectional view of the electronic device according to the first embodiment. 図９は、実施例２に係る電子装置の断面図である。FIG. 9 is a cross-sectional view of the electronic device according to the second embodiment. 図１０は、実施例２に係る電子装置の製造工程図である。FIG. 10 is a manufacturing process diagram of the electronic device according to the second embodiment. 図１１は、実施例２に係る電子装置の製造工程図である。FIG. 11 is a manufacturing process diagram of the electronic device according to the second embodiment. 図１２は、実施例２に係る電子装置の製造工程図である。FIG. 12 is a manufacturing process diagram of the electronic device according to the second embodiment. 図１３は、実施例２に係る電子装置の製造工程図である。FIG. 13 is a manufacturing process diagram of the electronic device according to the second embodiment. 図１４は、実施例３に係る電子装置の断面図である。FIG. 14 is a cross-sectional view of the electronic device according to the third embodiment. 図１５は、実施例３に係る電子装置の製造工程図である。FIG. 15 is a manufacturing process diagram of the electronic device according to the third embodiment. 図１６は、実施例３に係る電子装置の製造工程図である。FIG. 16 is a manufacturing process diagram of the electronic device according to the third embodiment. 図１７は、実施例４に係る電子装置の部分断面図である。FIG. 17 is a partial cross-sectional view of the electronic device according to the fourth embodiment. 図１８は、ＢＧＡパッケージの一例を示す断面図である。FIG. 18 is a cross-sectional view showing an example of a BGA package.

以下、図面を参照して実施形態について説明する。以下に示す各実施例の構成は例示であり、実施形態に係る構成は、以下に示す各実施例の構成に限定されない。また、実施形態に係る構成は、各実施例を組み合わせた構成であってもよい。   Hereinafter, embodiments will be described with reference to the drawings. The configuration of each example shown below is an exemplification, and the configuration according to the embodiment is not limited to the configuration of each example shown below. Moreover, the structure which concerns on embodiment may be the structure which combined each Example.

〈実施例１〉
実施例１に係る電子装置１について説明する。図１は、実施例１に係る電子装置１の断面図である。電子装置１は、マザーボード２と、半導体パッケージ３とを備える。半導体パッケージ３は、マザーボード２に実装されている。マザーボード２は、例えば、プリント基板である。半導体パッケージ３は、例えば、ＢＧＡパッケージである。 <Example 1>
An electronic device 1 according to a first embodiment will be described. FIG. 1 is a cross-sectional view of the electronic device 1 according to the first embodiment. The electronic device 1 includes a mother board 2 and a semiconductor package 3. The semiconductor package 3 is mounted on the mother board 2. The motherboard 2 is, for example, a printed board. The semiconductor package 3 is, for example, a BGA package.

マザーボード２は、マザーボード２を貫通する複数のメッキスルーホール（ＰＴＨ）１１、１２を有する。図２は、マザーボード２の部分断面図である。メッキスルーホール１１は、マザーボード２を貫通する孔２１と、孔２１の側壁に形成された金属膜（導電膜）２２とを含む。メッキスルーホール１１は、スルーホールの一例である。メッキスルーホール１２は、マザーボード２を貫通する孔２３と、孔２３の側壁に形成された金属膜（導電膜）２４とを含む。金属膜２４は、ランドパターン２５に接続される。例えば、ドリルを用いて、マザーボード２に孔２１、２３を形成する。金属膜２２、２４及びランドパターン２５の材料は、例えば、Ｃｕ（銅）である。   The mother board 2 has a plurality of plated through holes (PTH) 11 and 12 penetrating the mother board 2. FIG. 2 is a partial cross-sectional view of the mother board 2. The plated through hole 11 includes a hole 21 penetrating the mother board 2 and a metal film (conductive film) 22 formed on the side wall of the hole 21. The plated through hole 11 is an example of a through hole. The plated through hole 12 includes a hole 23 penetrating the mother board 2 and a metal film (conductive film) 24 formed on the side wall of the hole 23. The metal film 24 is connected to the land pattern 25. For example, the holes 21 and 23 are formed in the mother board 2 using a drill. The material of the metal films 22 and 24 and the land pattern 25 is, for example, Cu (copper).

半導体パッケージ３は、パッケージ基板３１と、半導体チップ３２と、ヒートスプレッダ３３とを備える。パッケージ基板３１として、例えば、ビルドアップ基板、セラミック基板、ガラスセラミック基板、コアレス基板等が挙げられる。パッケージ基板３１は、第１基板の一例である。マザーボード２及びパッケージ基板３１は、互いに対向するように配置されている。マザーボード２は、第２基板の一例である。パッケージ基板３１の第１面に半導体チップ３２及びヒートスプレッダ３３が搭載されている。パッケージ基板３１の第２面に複数の電極パッド３４、複数のはんだボール３５及び複数のはんだボール３６が形成されている。パッケージ基板３１の第２面は、マザーボード２と対向する面であって、パッケージ基板３１の第１面の反対面である。したがって、マザーボード２は、パッ
ケージ基板３１の第２面と対向するように配置されている。はんだボール３５、３６は、マザーボード２及びパッケージ基板３１同士を接合する。はんだボール３５、３６の材料は、例えば、Ｓｎ（スズ）又はＳｎを含む合金である。 The semiconductor package 3 includes a package substrate 31, a semiconductor chip 32, and a heat spreader 33. Examples of the package substrate 31 include a build-up substrate, a ceramic substrate, a glass ceramic substrate, and a coreless substrate. The package substrate 31 is an example of a first substrate. The mother board 2 and the package substrate 31 are arranged to face each other. The motherboard 2 is an example of a second substrate. A semiconductor chip 32 and a heat spreader 33 are mounted on the first surface of the package substrate 31. A plurality of electrode pads 34, a plurality of solder balls 35, and a plurality of solder balls 36 are formed on the second surface of the package substrate 31. The second surface of the package substrate 31 is the surface facing the mother board 2 and is the opposite surface of the first surface of the package substrate 31. Therefore, the mother board 2 is disposed so as to face the second surface of the package substrate 31. The solder balls 35 and 36 join the mother board 2 and the package substrate 31 together. The material of the solder balls 35 and 36 is, for example, Sn (tin) or an alloy containing Sn.

半導体チップ３２は、例えば、ＬＳＩ（Large Scale Integration）等のロジックチッ
プである。半導体チップ３２は、パッケージ基板３１にフリップチップ接合されている。半導体チップ３２の回路が形成されている面（以下、回路面という）をパッケージ基板３１に向けた状態（フェースダウン）で、半導体チップ３２の回路面に形成された電極と、パッケージ基板３１に形成された電極とが、はんだボール３７を介して接合されている。はんだボール３７の材料は、例えば、Ｓｎ又はＳｎを含む合金である。 The semiconductor chip 32 is a logic chip such as an LSI (Large Scale Integration), for example. The semiconductor chip 32 is flip-chip bonded to the package substrate 31. Formed on the package substrate 31 and the electrodes formed on the circuit surface of the semiconductor chip 32 with the surface on which the circuit of the semiconductor chip 32 is formed (hereinafter referred to as the circuit surface) facing the package substrate 31 (face down) These electrodes are joined via solder balls 37. The material of the solder ball 37 is, for example, Sn or an alloy containing Sn.

ヒートスプレッダ３３が半導体チップ３２を覆っている。ヒートスプレッダ３３は、半導体チップ３２の回路面の反対面と接触している。ヒートスプレッダ３３は、例えば、Ｃｕ（銅）、Ａｌ（アルミニウム）等の金属部材や、ＳｉＣ（炭化ケイ素）、ＡｌＮ（窒化アルミニウム）等の高熱伝導セラミックス部材を用いて形成されている。ヒートスプレッダ３３は、半導体チップ３２から伝わる熱を放熱する。半導体チップ３２とヒートスプレッダ３３との間にＴＩＭ（Thermal Interface Material）を形成してもよい。ＴＩＭは、例えば、金属ペースト、シリコンゴム、グラファイトシート、熱伝導グリス、接着剤等の熱伝導材料である。   A heat spreader 33 covers the semiconductor chip 32. The heat spreader 33 is in contact with the surface opposite to the circuit surface of the semiconductor chip 32. The heat spreader 33 is formed using, for example, a metal member such as Cu (copper) or Al (aluminum), or a high thermal conductive ceramic member such as SiC (silicon carbide) or AlN (aluminum nitride). The heat spreader 33 radiates heat transmitted from the semiconductor chip 32. A TIM (Thermal Interface Material) may be formed between the semiconductor chip 32 and the heat spreader 33. TIM is a heat conductive material such as metal paste, silicon rubber, graphite sheet, heat conductive grease, adhesive, and the like.

メッキスルーホール１１にピン１３が挿入されている。ピン１３は、円柱形状である。ピン１３の材料は、例えば、Ｃｕ又はＡｕ（金）である。ピン１３は、マザーボード２の第１面から突出した状態となっている。マザーボード２の第１面は、パッケージ基板３１と対向する面である。ピン１３の第１端部（上端部）は、マザーボード２の第１面に繋がるメッキスルーホール１１から突出し、はんだボール３５と接合されている。したがって、ピン１３は、はんだボール３５を介して電極パッド３４にはんだ接合されている。ピン１３の第２端部（下端部）及び中央部は、メッキスルーホール１１に挿入されている。ピン１３の挿入部分は、メッキスルーホール１１内に埋め込まれたはんだ１４を介して、メッキスルーホール１１とはんだ接合されている。   A pin 13 is inserted into the plated through hole 11. The pin 13 has a cylindrical shape. The material of the pin 13 is, for example, Cu or Au (gold). The pin 13 protrudes from the first surface of the motherboard 2. The first surface of the mother board 2 is a surface facing the package substrate 31. A first end (upper end) of the pin 13 protrudes from the plated through hole 11 connected to the first surface of the mother board 2 and is joined to the solder ball 35. Accordingly, the pin 13 is soldered to the electrode pad 34 via the solder ball 35. The second end (lower end) and the center of the pin 13 are inserted into the plated through hole 11. The insertion portion of the pin 13 is soldered to the plated through hole 11 via the solder 14 embedded in the plated through hole 11.

図２に示すように、メッキスルーホール１２上にランドパターン２５が形成されている。ランドパターン２５は、はんだボール３６と接合されている。したがって、ランドパターン２５は、はんだボール３６を介して電極パッド３４にはんだ接合されている。   As shown in FIG. 2, a land pattern 25 is formed on the plated through hole 12. The land pattern 25 is joined to the solder ball 36. Therefore, the land pattern 25 is soldered to the electrode pad 34 via the solder ball 36.

マザーボード２上に半導体パッケージ３を搭載した後、リフロー処理を行うことにより、マザーボード２上に半導体パッケージ３が実装される。リフロー処理が行われることにより、マザーボード２及びパッケージ基板３１に反りが発生する。図１に示すように、マザーボード２とパッケージ基板３１との接合部として、はんだボール３５、３６が用いられている。メッキスルーホール１１に挿入されたピン１３は、パッケージ基板３１に向けてメッキスルーホール１１から突出し、ピン１３とはんだボール３５とが接合している。リフロー処理の過熱が終わった後、メッキスルーホール１１に挿入されたピン１３が、マザーボード２の反りやパッケージ基板３１の反りの戻り（縮む）際に発生する応力を吸収し、はんだボール３５に発生する応力が低減される。その結果、はんだボール３５におけるクラックの発生が抑止される。したがって、マザーボード２及びパッケージ基板３１に反りが発生しても、マザーボード２に半導体パッケージ３を実装することが可能となり、半導体パッケージ３の実装歩留まりが向上する。なお、リフロー処理時のマザーボード２の反りやパッケージ基板３１の反りが大きい箇所のメッキスルーホール１１に、ピン１３を挿入するのが望ましい。反りが大きい箇所は、例えば、図１のように、パッケージ基板３１の中央に半導体チップ３２が置かれている場合、半導体チップ３２から離れたパッケージ基板３１の周辺部が挙げられる。   After the semiconductor package 3 is mounted on the mother board 2, the semiconductor package 3 is mounted on the mother board 2 by performing a reflow process. When the reflow process is performed, the mother board 2 and the package substrate 31 are warped. As shown in FIG. 1, solder balls 35 and 36 are used as a joint between the mother board 2 and the package substrate 31. The pin 13 inserted into the plated through hole 11 protrudes from the plated through hole 11 toward the package substrate 31, and the pin 13 and the solder ball 35 are joined. After the reflow process is overheated, the pin 13 inserted into the plated through hole 11 absorbs the stress generated when the warp of the mother board 2 or the warp of the package substrate 31 returns (shrinks), and is generated in the solder ball 35. Stress to be reduced. As a result, the occurrence of cracks in the solder balls 35 is suppressed. Therefore, even if the mother board 2 and the package substrate 31 are warped, the semiconductor package 3 can be mounted on the mother board 2 and the mounting yield of the semiconductor package 3 is improved. In addition, it is desirable to insert the pin 13 into the plated through hole 11 where the warpage of the motherboard 2 or the warpage of the package substrate 31 is large during the reflow process. For example, when the semiconductor chip 32 is placed at the center of the package substrate 31 as shown in FIG. 1, a portion where the warpage is large includes a peripheral portion of the package substrate 31 away from the semiconductor chip 32.

ピン１３とはんだボール３５とが接合しているため、マザーボード２の熱膨張係数とパッケージ基板３１の熱膨張係数とが異なる場合でも、はんだボール３５に発生する応力を低減することができる。したがって、マザーボード２の熱膨張係数とパッケージ基板３１の熱膨張係数とが異なる場合でも、マザーボード２とパッケージ基板３１との接合部の信頼性が向上し、半導体パッケージ３の実装歩留まりが向上する。例えば、有機マザーボードにセラミックパッケージを実装する場合のように、熱膨張係数の差が大きな組み合わせでも、はんだボール３５に発生する応力が低減される。   Since the pins 13 and the solder balls 35 are joined, even when the thermal expansion coefficient of the mother board 2 and the thermal expansion coefficient of the package substrate 31 are different, the stress generated in the solder balls 35 can be reduced. Therefore, even when the thermal expansion coefficient of the motherboard 2 and the thermal expansion coefficient of the package substrate 31 are different, the reliability of the joint portion between the motherboard 2 and the package substrate 31 is improved, and the mounting yield of the semiconductor package 3 is improved. For example, even when the difference in the thermal expansion coefficient is large, as in the case where a ceramic package is mounted on an organic mother board, the stress generated in the solder ball 35 is reduced.

〈製造方法及びはんだ実装方法〉
実施例１に係る電子装置１の製造方法及びはんだ実装方法について説明する。図３から図６は、実施例１に係る電子装置１の製造工程図である。まず、マザーボード２を用意する。マザーボード２には、マザーボード２を貫通する複数のメッキスルーホール１１、１２が形成されている。次に、図３に示すように、複数のメッキスルーホール１１の内部のそれぞれにはんだペースト４１を充填する。例えば、ディスペンサ又はスキージを用いて、はんだペースト４１の充填を行う。はんだペースト４１は、はんだ粉末及びフラックスを含んでいる。はんだ粉末は、例えば、Ｓｎ又はＳｎを含む合金である。次いで、図４に示すように、複数のメッキスルーホール１１にピン１３をそれぞれ挿入し、各ピン１３の第１端部をマザーボード２の第１面に繋がるメッキスルーホール１１から突出させる。 <Manufacturing method and solder mounting method>
A method for manufacturing the electronic device 1 and a solder mounting method according to the first embodiment will be described. 3 to 6 are manufacturing process diagrams of the electronic device 1 according to the first embodiment. First, the mother board 2 is prepared. The motherboard 2 is formed with a plurality of plated through holes 11 and 12 that penetrate the motherboard 2. Next, as shown in FIG. 3, a solder paste 41 is filled in each of the plurality of plated through holes 11. For example, the solder paste 41 is filled using a dispenser or a squeegee. The solder paste 41 contains solder powder and flux. The solder powder is, for example, Sn or an alloy containing Sn. Next, as shown in FIG. 4, pins 13 are respectively inserted into the plurality of plated through holes 11, and the first ends of the pins 13 are projected from the plated through holes 11 connected to the first surface of the mother board 2.

次に、図５に示すように、マザーボード２上に半導体パッケージ３を搭載する。マザーボード２の第１面に半導体パッケージ３を搭載する。これにより、マザーボード２及びパッケージ基板３１が、互いに対向するように配置される。パッケージ基板３１の第１面に複数の電極パッド３４、複数のはんだボール３５及び複数のはんだボール３６が形成されている。複数のはんだボール３５、３６にはフラックスが塗布されている。   Next, as shown in FIG. 5, the semiconductor package 3 is mounted on the mother board 2. The semiconductor package 3 is mounted on the first surface of the motherboard 2. Thereby, the mother board 2 and the package substrate 31 are disposed so as to face each other. A plurality of electrode pads 34, a plurality of solder balls 35, and a plurality of solder balls 36 are formed on the first surface of the package substrate 31. A flux is applied to the plurality of solder balls 35 and 36.

次いで、図６に示すように、リフロー処理を行うことにより、ピン１３とはんだボール３５とを接合し、ランドパターン２５とはんだボール３６とを接合する。例えば、マザーボード２及び半導体パッケージ３をリフロー炉に導入し、加熱を行う。リフロー処理が行われることで、はんだペースト４１のはんだ粉末が溶融し、はんだペースト４１のフラックスが気化して、メッキスルーホール１１内にはんだ１４が形成される。これにより、ピン１３の挿入部分が、メッキスルーホール１１内に形成されたはんだ１４を介して、メッキスルーホール１１とはんだ接合される。   Next, as shown in FIG. 6, by performing a reflow process, the pin 13 and the solder ball 35 are joined, and the land pattern 25 and the solder ball 36 are joined. For example, the mother board 2 and the semiconductor package 3 are introduced into a reflow furnace and heated. By performing the reflow process, the solder powder of the solder paste 41 is melted, the flux of the solder paste 41 is vaporized, and the solder 14 is formed in the plated through hole 11. Thereby, the insertion portion of the pin 13 is soldered to the plated through hole 11 via the solder 14 formed in the plated through hole 11.

リフロー処理により、ピン１３とはんだ１４とが接合され、ピン１３とはんだボール３５とが接合される。ピン１３とはんだ１４との接合が完了するまで、はんだ１４は溶融した状態となる。ピン１３とはんだボール３５との接合が完了するまではんだボール３５は溶融した状態となる。そのため、リフロー処理が行われている間、ピン１３はメッキスルーホール１１内で上下方向（マザーボード２の厚み方向）に移動可能である。なお、はんだボール３５の表面張力により、ピン１３が抜け落ちることはない。   By reflow processing, the pin 13 and the solder 14 are joined, and the pin 13 and the solder ball 35 are joined. The solder 14 is in a molten state until the joining of the pin 13 and the solder 14 is completed. The solder ball 35 is in a molten state until the joining of the pin 13 and the solder ball 35 is completed. Therefore, while the reflow process is being performed, the pin 13 can move in the vertical direction (the thickness direction of the mother board 2) within the plated through hole 11. Note that the pins 13 do not fall off due to the surface tension of the solder balls 35.

図７は、マザーボード２に反りが発生した場合のマザーボード２の部分断面図である。リフロー処理の際、マザーボード２が反る。リフロー処理の加熱が終わって冷えると、はんだボール３５とはんだ１４が固まりピン１３が固定されて、マザーボード２の反りが元に戻る。メッキスルーホール１１に挿入されたピン１３が、リフロー処理の加熱が終わってマザーボード２の反りが元に戻る（縮む）際に発生する応力を吸収し、はんだボール３５に発生する応力を低減する。したがって、マザーボード２とパッケージ基板３１との接合部の信頼性が向上し、半導体パッケージ３の実装歩留まりが向上する。   FIG. 7 is a partial cross-sectional view of the mother board 2 when the mother board 2 is warped. During the reflow process, the motherboard 2 warps. When the heating in the reflow process is finished and the solder ball 35 is cooled, the solder balls 35 and the solder 14 are solidified, the pins 13 are fixed, and the warpage of the mother board 2 is restored. The pins 13 inserted into the plated through holes 11 absorb the stress generated when the heating of the reflow process is finished and the warp of the mother board 2 returns (shrinks) to reduce the stress generated in the solder balls 35. Therefore, the reliability of the joint portion between the mother board 2 and the package substrate 31 is improved, and the mounting yield of the semiconductor package 3 is improved.

図８は、実施例１に係る電子装置１の断面図である。図８に示すように、メッキスルー
ホール１１内に空間４２を形成してもよい。メッキスルーホール１１内に充填するはんだペースト４１の量を調整し、メッキスルーホール１１内にはんだペースト４１の未充填の領域を形成した後、リフロー処理を行うことにより、メッキスルーホール１１内に空間４２が形成される。図８に示す構造例では、はんだ１４とはんだボール３５との間に空間４２が形成されており、はんだ１４とはんだボール３５とが接合されていない。はんだ１４とはんだボール３５とが離れることにより、はんだボール３５に発生する応力を低減することができる。 FIG. 8 is a cross-sectional view of the electronic device 1 according to the first embodiment. As shown in FIG. 8, a space 42 may be formed in the plated through hole 11. After adjusting the amount of the solder paste 41 to be filled in the plated through hole 11 and forming an unfilled region of the solder paste 41 in the plated through hole 11, a reflow process is performed so that the space in the plated through hole 11 is obtained. 42 is formed. In the structural example shown in FIG. 8, a space 42 is formed between the solder 14 and the solder ball 35, and the solder 14 and the solder ball 35 are not joined. When the solder 14 and the solder ball 35 are separated, the stress generated in the solder ball 35 can be reduced.

〈実施例２〉
実施例２に係る電子装置１について説明する。実施例１と同一の構成要素については、実施例１と同一の符号を付し、その説明を省略する。図９は、実施例２に係る電子装置１の断面図である。マザーボード２の第１面側に、メッキスルーホール１１と繋がり、メッキスルーホール１１の径よりも大きい径の凹部（ザグリ穴）５１が形成されている。凹部５１は、平面視で、円形であってもよいし、矩形であってもよい。凹部５１の側壁には、はんだ１４及び金属膜２２が形成されていない。 <Example 2>
An electronic apparatus 1 according to a second embodiment will be described. The same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and the description thereof is omitted. FIG. 9 is a cross-sectional view of the electronic device 1 according to the second embodiment. On the first surface side of the motherboard 2, a concave portion (counterbore hole) 51 that is connected to the plated through hole 11 and has a diameter larger than the diameter of the plated through hole 11 is formed. The recess 51 may be circular or rectangular in plan view. The solder 14 and the metal film 22 are not formed on the side wall of the recess 51.

ピン１３は、マザーボード２の第１面から突出した状態となっている。ピン１３の第１端部及び中央部は、凹部５１の底面から上方に突出し、ピン１３の第１端部は、凹部５１の開口から上方に突出している。ピン１３の第２端部は、メッキスルーホール１１に挿入されている。はんだ１４とはんだボール３５とは接合されていない。すなわち、凹部５１内におけるピン１３の側面の一部が露出している。   The pin 13 protrudes from the first surface of the motherboard 2. The first end portion and the center portion of the pin 13 protrude upward from the bottom surface of the recess 51, and the first end portion of the pin 13 protrudes upward from the opening of the recess 51. The second end of the pin 13 is inserted into the plated through hole 11. The solder 14 and the solder ball 35 are not joined. That is, a part of the side surface of the pin 13 in the recess 51 is exposed.

図９に示す構造例では、凹部５１内におけるピン１３の側面の一部が露出している。図９に示す構造例に限定されず、凹部５１内におけるピン１３の側面を樹脂が覆うようにしてもよい。ピン１３の側面を覆う樹脂は、例えば、エポキシ樹脂である。凹部５１内におけるピン１３の側面を樹脂が覆うことにより、ピン１３の耐性が向上する。   In the structural example shown in FIG. 9, a part of the side surface of the pin 13 in the recess 51 is exposed. It is not limited to the structural example shown in FIG. 9, and the resin may cover the side surface of the pin 13 in the recess 51. The resin that covers the side surfaces of the pins 13 is, for example, an epoxy resin. The resin covers the side surface of the pin 13 in the recess 51, whereby the resistance of the pin 13 is improved.

〈製造方法及びはんだ実装方法〉
実施例２に係る電子装置１の製造方法及びはんだ実装方法について説明する。図１０から図１３は、実施例２に係る電子装置１の製造工程図である。まず、マザーボード２を用意する。マザーボード２には、マザーボード２を貫通する複数のメッキスルーホール１１、１２が形成されている。次に、図１０に示すように、ドリルを用いて、マザーボード２の第１面に複数の凹部５１を形成する。この場合、マザーボード２の第１面に、メッキスルーホール１１と重なる領域及びメッキスルーホール１１の周囲の領域に凹部５１を形成する。したがって、マザーボード２の第１面側のメッキスルーホール１１が部分的に除去され、マザーボード２の第２面側にメッキスルーホール１１が残存した状態となる。マザーボード２の第２面は、マザーボード２の第１面の反対面である。 <Manufacturing method and solder mounting method>
A method for manufacturing the electronic device 1 and a solder mounting method according to the second embodiment will be described. 10 to 13 are manufacturing process diagrams of the electronic device 1 according to the second embodiment. First, the mother board 2 is prepared. The motherboard 2 is formed with a plurality of plated through holes 11 and 12 that penetrate the motherboard 2. Next, as shown in FIG. 10, a plurality of recesses 51 are formed on the first surface of the mother board 2 using a drill. In this case, a recess 51 is formed on the first surface of the motherboard 2 in a region overlapping with the plated through hole 11 and a region around the plated through hole 11. Therefore, the plated through hole 11 on the first surface side of the motherboard 2 is partially removed, and the plated through hole 11 remains on the second surface side of the motherboard 2. The second surface of the motherboard 2 is the opposite surface of the first surface of the motherboard 2.

次いで、図１１に示すように、複数のメッキスルーホール１１の内部のそれぞれにはんだペースト５２を充填する。この場合、凹部５１の内部にはんだペースト５２を充填しない。はんだペースト５２は、はんだ粉末及びフラックスを含んでいる。次に、図１２に示すように、複数のメッキスルーホール１１にピン１３をそれぞれ挿入し、ピン１３の第１端部及び中央部をメッキスルーホール１１から突出させる。したがって、ピン１３の第１端部及び中央部は、はんだペースト５２と接触しない状態となる。   Next, as shown in FIG. 11, a solder paste 52 is filled in each of the plurality of plated through holes 11. In this case, the solder paste 52 is not filled in the recess 51. The solder paste 52 contains solder powder and flux. Next, as shown in FIG. 12, the pins 13 are inserted into the plurality of plated through holes 11, respectively, and the first end portion and the central portion of the pins 13 are protruded from the plated through holes 11. Therefore, the first end portion and the central portion of the pin 13 are not in contact with the solder paste 52.

次に、マザーボード２上に半導体パッケージ３を搭載する。マザーボード２上に半導体パッケージ３を搭載する処理は、実施例１と同様である。次いで、図１３に示すように、リフロー処理を行うことにより、ピン１３とはんだボール３５とを接合し、ランドパターン２５とはんだボール３６とを接合する。例えば、マザーボード２及び半導体パッケージ３をリフロー炉に導入し、加熱を行う。リフロー処理が行われることで、はんだペースト
５２のはんだ粉末が溶融し、はんだペースト５２のフラックスが気化して、メッキスルーホール１１内にはんだ１４が形成される。これにより、ピン１３の挿入部分が、メッキスルーホール１１内に形成されたはんだ１４を介して、メッキスルーホール１１とはんだ接合される。 Next, the semiconductor package 3 is mounted on the mother board 2. The process of mounting the semiconductor package 3 on the mother board 2 is the same as that of the first embodiment. Next, as shown in FIG. 13, by performing a reflow process, the pin 13 and the solder ball 35 are joined, and the land pattern 25 and the solder ball 36 are joined. For example, the mother board 2 and the semiconductor package 3 are introduced into a reflow furnace and heated. By performing the reflow process, the solder powder of the solder paste 52 is melted, the flux of the solder paste 52 is vaporized, and the solder 14 is formed in the plated through hole 11. Thereby, the insertion portion of the pin 13 is soldered to the plated through hole 11 via the solder 14 formed in the plated through hole 11.

リフロー処理により、ピン１３とはんだ１４とが接合され、ピン１３とはんだボール３５とが接合される。リフロー処理が行われている間、はんだ１４及びはんだボール３５は溶融状態となっている。そのため、リフロー処理が行われている間、ピン１３はメッキスルーホール１１内で上下に移動可能である。すなわち、リフロー処理が行われている間、ピン１３はマザーボード２の厚み方向で移動可能である。   By reflow processing, the pin 13 and the solder 14 are joined, and the pin 13 and the solder ball 35 are joined. During the reflow process, the solder 14 and the solder balls 35 are in a molten state. Therefore, the pin 13 can move up and down in the plated through hole 11 while the reflow process is performed. That is, the pin 13 is movable in the thickness direction of the mother board 2 while the reflow process is being performed.

リフロー処理が行われている間、はんだボール３５が溶融し、はんだボール３５がピン１３に沿って変形する。はんだボール３５の直下に凹部５１が形成されているため、はんだボール３５が凹部５１内に入り込む。はんだ１４とはんだボール３５とは、ピン１３の中央部分の長さに相当する距離離れている。したがって、リフロー処理により、はんだボール３５がピン１３に沿って変形しても、はんだ１４とはんだボール３５とは接合されない。メッキスルーホール１１とはんだボール３５とは、ピン１３の中央部分の長さに相当する距離離れている。したがって、リフロー処理により、はんだボール３５がピン１３に沿って変形しても、メッキスルーホール１１とはんだボール３５とは接合されない。このため、はんだボール３５に発生する応力が低減される。その結果、マザーボード２とパッケージ基板３１との接合部の信頼性が向上し、半導体パッケージ３の実装歩留まりが向上する。   During the reflow process, the solder ball 35 melts and the solder ball 35 is deformed along the pin 13. Since the recess 51 is formed immediately below the solder ball 35, the solder ball 35 enters the recess 51. The solder 14 and the solder ball 35 are separated by a distance corresponding to the length of the central portion of the pin 13. Therefore, even if the solder ball 35 is deformed along the pin 13 by the reflow process, the solder 14 and the solder ball 35 are not joined. The plated through hole 11 and the solder ball 35 are separated by a distance corresponding to the length of the central portion of the pin 13. Therefore, even if the solder ball 35 is deformed along the pin 13 by the reflow process, the plated through hole 11 and the solder ball 35 are not joined. For this reason, the stress generated in the solder ball 35 is reduced. As a result, the reliability of the joint between the mother board 2 and the package substrate 31 is improved, and the mounting yield of the semiconductor package 3 is improved.

〈実施例３〉
実施例３に係る電子装置１について説明する。実施例１及び実施例２と同一の構成要素については、実施例１及び実施例２と同一の符号を付し、その説明を省略する。図１４は、実施例３に係る電子装置１の断面図である。マザーボード２は、マザーボード２を貫通する複数の孔６１を有する。例えば、ドリルを用いて、マザーボード２に孔６１を形成する。マザーボード２の第２面であって、孔６１の開口の周囲に電極パッド６２が形成されている。孔６１は、スルーホールの一例である。 <Example 3>
An electronic apparatus 1 according to a third embodiment will be described. The same components as those in the first and second embodiments are denoted by the same reference numerals as those in the first and second embodiments, and the description thereof is omitted. FIG. 14 is a cross-sectional view of the electronic device 1 according to the third embodiment. The mother board 2 has a plurality of holes 61 penetrating the mother board 2. For example, the hole 61 is formed in the mother board 2 using a drill. An electrode pad 62 is formed on the second surface of the mother board 2 around the opening of the hole 61. The hole 61 is an example of a through hole.

孔６１にピン１３が挿入されている。ピン１３は、マザーボード２の第１面から突出した状態となっている。ピン１３の第１端部は、マザーボード２の第１面に繋がる孔６１から突出し、はんだボール３５と接合されている。したがって、ピン１３は、はんだボール３５を介して電極パッド３４にはんだ接合されている。ピン１３の中央部は、孔６１に挿入されている。ピン１３の第２端部は、マザーボード２の第２面に繋がる孔６１から突出し、かつ、台座（支持板）６３に接続されている。台座６３の材料は、ピン１３の材料と同じである。ピン１３と台座６３とが一体的に形成されていてもよい。ピン１３が台座６３に溶接されていてもよい。台座６３の径は、孔６１の径よりも大きい。   A pin 13 is inserted into the hole 61. The pin 13 protrudes from the first surface of the motherboard 2. A first end portion of the pin 13 protrudes from a hole 61 connected to the first surface of the mother board 2 and is joined to the solder ball 35. Accordingly, the pin 13 is soldered to the electrode pad 34 via the solder ball 35. A central portion of the pin 13 is inserted into the hole 61. A second end portion of the pin 13 protrudes from a hole 61 connected to the second surface of the mother board 2 and is connected to a base (support plate) 63. The material of the pedestal 63 is the same as the material of the pin 13. The pin 13 and the pedestal 63 may be integrally formed. The pin 13 may be welded to the pedestal 63. The diameter of the pedestal 63 is larger than the diameter of the hole 61.

電極パッド６２は、電極パッド６２と台座６３との間に形成されたはんだ６４に接合されている。台座６３は、電極パッド６２と台座６３との間に形成されたはんだ６４に接合されている。したがって、電極パッド６２及び台座６３は、はんだ６４を介してはんだ接合されている。すなわち、台座６３は、マザーボード２の第２面にはんだ接合されている。リフロー処理において、はんだボール３５と孔６１内のはんだペーストとが接触し、はんだボール３５の過剰な濡れ広がりが発生する場合、はんだボール３５の強度が低下する。孔６１内にはんだペーストが充填されていないため、リフロー処理において、はんだボール３５の過剰な濡れ広がりが抑制される。この結果、はんだボール３５の強度の低下が抑止され、はんだボール３５におけるクラックの発生が抑止される。したがって、マザーボード２とパッケージ基板３１との接合部の信頼性が向上し、半導体パッケージ３の実装
歩留まりが向上する。また、図１、図８及び図９に示す構造例におけるピン１３の第２端部に台座６３を接続してもよい。 The electrode pad 62 is joined to the solder 64 formed between the electrode pad 62 and the pedestal 63. The pedestal 63 is joined to a solder 64 formed between the electrode pad 62 and the pedestal 63. Therefore, the electrode pad 62 and the pedestal 63 are soldered together via the solder 64. That is, the pedestal 63 is soldered to the second surface of the mother board 2. In the reflow process, when the solder balls 35 come into contact with the solder paste in the holes 61 and the solder balls 35 are excessively wet and spread, the strength of the solder balls 35 is reduced. Since the solder paste is not filled in the hole 61, excessive wetting and spreading of the solder ball 35 is suppressed in the reflow process. As a result, a decrease in the strength of the solder ball 35 is suppressed, and the occurrence of cracks in the solder ball 35 is suppressed. Therefore, the reliability of the joint portion between the mother board 2 and the package substrate 31 is improved, and the mounting yield of the semiconductor package 3 is improved. Moreover, you may connect the base 63 to the 2nd end part of the pin 13 in the structural example shown in FIG.1, FIG8 and FIG.9.

〈製造方法及びはんだ実装方法〉
実施例３に係る電子装置１の製造方法及びはんだ実装方法について説明する。図１５及び図１６は、実施例３に係る電子装置１の製造工程図である。まず、図１５に示すように、マザーボード２を用意する。マザーボード２には、マザーボード２を貫通する複数の孔６１が形成されている。マザーボード２の第２面であって、孔６１の開口の周囲に電極パッド６２が形成されている。次に、電極パッド６２上にはんだペースト６５を形成する。次いで、マザーボード２の第２面側から孔６１にピン１３を挿入する。 <Manufacturing method and solder mounting method>
A method for manufacturing the electronic device 1 and a solder mounting method according to the third embodiment will be described. 15 and 16 are manufacturing process diagrams of the electronic device 1 according to the third embodiment. First, as shown in FIG. 15, the mother board 2 is prepared. A plurality of holes 61 penetrating the mother board 2 are formed in the mother board 2. An electrode pad 62 is formed on the second surface of the mother board 2 around the opening of the hole 61. Next, a solder paste 65 is formed on the electrode pad 62. Next, the pin 13 is inserted into the hole 61 from the second surface side of the mother board 2.

次いで、図１６に示すように、マザーボード２上に半導体パッケージ３を搭載する。マザーボード２の第１面に半導体パッケージ３が搭載される。これにより、マザーボード２及びパッケージ基板３１が、互いに対向するように配置される。パッケージ基板３１の第１面に複数の電極パッド３４、複数のはんだボール３５及び複数のはんだボール３６が形成されている。複数のはんだボール３５、３６にはフラックスが塗布されている。   Next, as shown in FIG. 16, the semiconductor package 3 is mounted on the mother board 2. A semiconductor package 3 is mounted on the first surface of the motherboard 2. Thereby, the mother board 2 and the package substrate 31 are disposed so as to face each other. A plurality of electrode pads 34, a plurality of solder balls 35, and a plurality of solder balls 36 are formed on the first surface of the package substrate 31. A flux is applied to the plurality of solder balls 35 and 36.

次いで、リフロー処理を行うことにより、ピン１３とはんだボール３５とを接合し、ランドパターン２５とはんだボール３６とを接合する。例えば、マザーボード２及び半導体パッケージ３をリフロー炉に導入し、加熱を行う。リフロー処理が行われることで、はんだペースト６５のはんだ粉末が溶融し、はんだペースト６５のフラックスが気化して、電極パッド６２と台座６３との間にはんだ６４が形成される。これにより、台座６３が、はんだ６４を介して、電極パッド６２とはんだ接合される。すなわち、台座６３が、マザーボード２の第２面にはんだ接合される。   Next, by performing a reflow process, the pin 13 and the solder ball 35 are joined, and the land pattern 25 and the solder ball 36 are joined. For example, the mother board 2 and the semiconductor package 3 are introduced into a reflow furnace and heated. By performing the reflow process, the solder powder of the solder paste 65 is melted, the flux of the solder paste 65 is vaporized, and the solder 64 is formed between the electrode pad 62 and the pedestal 63. Thereby, the pedestal 63 is soldered to the electrode pad 62 via the solder 64. That is, the pedestal 63 is soldered to the second surface of the mother board 2.

〈実施例４〉
実施例４に係る電子装置１について説明する。実施例１〜実施例３と同一の構成要素については、実施例１〜実施例３と同一の符号を付し、その説明を省略する。図１７は、実施例４に係る電子装置１の部分断面図である。マザーボード２は、マザーボード２の第１面に凹部５１を有する。ピン１３の第１端部及び中央部は、凹部５１の底面から突出し、ピン１３の第１端部は、凹部５１の開口から突出している。ピン１３の第２端部は、メッキスルーホール１１に挿入されている。ピン１３の中央部は、金属メッキ７１が施されている。金属メッキ７１は、はんだとの濡れ性が悪い。金属メッキ７１は、例えば、Ｎｉ（ニッケル）メッキ、Ｔｉ（チタン）メッキ、Ｗ（タングステン）メッキ、Ｔａ（タンタル）メッキ及びＣｒ（クロム）メッキ等である。ピン１３をメッキスルーホール１１に挿入する前に、例えば、スパッタリングによりピン１３の中央部に金属メッキ７１を形成する。また、図８及び図１４に示す構造例におけるピン１３の中央部に金属メッキ７１を施してもよい。 <Example 4>
An electronic apparatus 1 according to a fourth embodiment will be described. The same components as those of the first to third embodiments are denoted by the same reference numerals as those of the first to third embodiments, and the description thereof is omitted. FIG. 17 is a partial cross-sectional view of the electronic device 1 according to the fourth embodiment. The motherboard 2 has a recess 51 on the first surface of the motherboard 2. The first end portion and the center portion of the pin 13 protrude from the bottom surface of the recess 51, and the first end portion of the pin 13 protrudes from the opening of the recess 51. The second end of the pin 13 is inserted into the plated through hole 11. A metal plating 71 is applied to the central portion of the pin 13. The metal plating 71 has poor wettability with solder. The metal plating 71 is, for example, Ni (nickel) plating, Ti (titanium) plating, W (tungsten) plating, Ta (tantalum) plating, Cr (chromium) plating, or the like. Before inserting the pin 13 into the plated through hole 11, the metal plating 71 is formed at the center of the pin 13 by sputtering, for example. Moreover, you may give the metal plating 71 to the center part of the pin 13 in the structural example shown in FIG.8 and FIG.14.

リフロー処理が行われている間、はんだボール３５が溶融し、はんだボール３５がピン１３に沿って変形する。ピン１３の中央部に金属メッキ７１が形成されている。金属メッキ７１ははんだとの濡れ性が悪いため、リフロー処理において、はんだボール３５の過剰な濡れ広がりが抑制される。その結果、はんだボール３５の強度の低下が抑止され、はんだボール３５におけるクラックの発生が抑止される。したがって、マザーボード２とパッケージ基板３１との接合部の信頼性が向上し、半導体パッケージ３の実装歩留まりが向上する。   During the reflow process, the solder ball 35 melts and the solder ball 35 is deformed along the pin 13. A metal plating 71 is formed at the center of the pin 13. Since the metal plating 71 has poor wettability with the solder, excessive spreading of the solder balls 35 is suppressed in the reflow process. As a result, a decrease in the strength of the solder balls 35 is suppressed, and the occurrence of cracks in the solder balls 35 is suppressed. Therefore, the reliability of the joint portion between the mother board 2 and the package substrate 31 is improved, and the mounting yield of the semiconductor package 3 is improved.

実施例１から実施例４において、マザーボード２とパッケージ基板３１との接合部の全てについて、ピン１３及びはんだボール３５を用いてもよい。実施例１から実施例４において、マザーボード２の反り、半導体パッケージ３の反り、パッケージ基板３１の反り及
びはんだボール３５に発生する応力をシミュレーションにより事前に予測してもよい。予測結果に基づいて、ピン１３及びはんだボール３５の接合箇所を決定してもよい。例えば、マザーボード２の反りが大きい箇所について、ピン１３及びはんだボール３５の接合を行うようにしてもよい。 In the first to fourth embodiments, the pins 13 and the solder balls 35 may be used for all the joints between the mother board 2 and the package substrate 31. In the first to fourth embodiments, warpage of the mother board 2, warpage of the semiconductor package 3, warpage of the package substrate 31, and stress generated in the solder balls 35 may be predicted in advance by simulation. Based on the prediction result, the joint location between the pin 13 and the solder ball 35 may be determined. For example, the pins 13 and the solder balls 35 may be joined at locations where the warpage of the mother board 2 is large.

１ 電子装置
２ マザーボード
３ 半導体パッケージ
１１、１２ メッキスルーホール
１３ ピン
１４、６４ はんだ
２１、２３、６１ 孔
２２、２４ 金属膜
２５ ランドパターン
３１ パッケージ基板
３２ 半導体チップ
３３ ヒートスプレッダ
３４、６２ 電極パッド
３５、３６、３７ はんだボール
４１、５２、６５ はんだペースト
４２ 空間
５１ 凹部
６３ 台座 DESCRIPTION OF SYMBOLS 1 Electronic device 2 Mother board 3 Semiconductor package 11, 12 Plated through hole 13 Pin 14, 64 Solder 21, 23, 61 Hole 22, 24 Metal film 25 Land pattern 31 Package substrate 32 Semiconductor chip 33 Heat spreader 34, 62 Electrode pads 35, 36 37 Solder balls 41, 52, 65 Solder paste 42 Space 51 Recess 63 Pedestal

Claims (8)

半導体チップが搭載された第１基板と、
前記第１基板に形成されたはんだボールと、
前記第１基板と対向するように配置された第２基板を貫通するスルーホールに挿入されたピンと、
を備え、
前記ピンは、前記はんだボールに接合されていることを特徴とする半導体パッケージ。 A first substrate on which a semiconductor chip is mounted;
Solder balls formed on the first substrate;
A pin inserted into a through-hole penetrating a second substrate disposed to face the first substrate;
With
The semiconductor package, wherein the pin is joined to the solder ball. 前記第２基板における前記第１基板と対向する面側に、前記スルーホールと繋がり、前記スルーホールの径よりも大きい径の凹部が形成されていることを特徴とする請求項１に記載の半導体パッケージ。   2. The semiconductor according to claim 1, wherein a concave portion having a diameter larger than the diameter of the through hole is formed on the surface of the second substrate facing the first substrate. package. 前記第２基板は、前記第１基板と対向する第１面及び前記第１面の反対面の第２面を有し、
前記ピンの一方の端部は、前記第２面に繋がる前記スルーホールから突出し、かつ、台座に接続され、
前記台座は、前記第２面にはんだ接合されていることを特徴とする請求項１又は２に記載の半導体パッケージ。 The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface,
One end of the pin protrudes from the through hole connected to the second surface, and is connected to a pedestal,
The semiconductor package according to claim 1, wherein the pedestal is soldered to the second surface. 前記ピンの中央部に、はんだとの濡れ性が悪いメッキが施されていることを特徴とする請求項１から３の何れか一項に記載の半導体パッケージ。   4. The semiconductor package according to claim 1, wherein the pin is plated with poor wettability with solder at a central portion thereof. 5. 基板を貫通するスルーホールにピンを挿入する工程と、
前記基板に半導体パッケージを搭載する工程と、
加熱して、前記半導体パッケージに形成されたはんだボールと前記ピンとを接合する工程と、
を備えることを特徴とするはんだ実装方法。 Inserting a pin into a through hole penetrating the substrate;
Mounting a semiconductor package on the substrate;
Heating and bonding the solder balls formed on the semiconductor package and the pins;
A solder mounting method comprising: 前記ピンを挿入する工程の前に、前記基板における前記半導体パッケージと対向する面側に、前記スルーホールと繋がり、前記スルーホールの径よりも大きい径の凹部を形成する工程を備えることを特徴とする請求項５に記載のはんだ実装方法。   Before the step of inserting the pins, a step of forming a recess having a diameter larger than the diameter of the through hole connected to the through hole on the surface side of the substrate facing the semiconductor package is provided. The solder mounting method according to claim 5. 前記基板は、前記半導体パッケージと対向する第１面及び前記第１面の反対面である第２面を有し、
前記ピンの一方の端部は、前記第２面に繋がる前記スルーホールから突出し、かつ、台座に接続され、
前記台座を前記第２面にはんだ接合する工程を備えることを特徴とする請求項５又は６に記載のはんだ実装方法。 The substrate has a first surface facing the semiconductor package and a second surface that is the opposite surface of the first surface;
One end of the pin protrudes from the through hole connected to the second surface, and is connected to a pedestal,
The solder mounting method according to claim 5, further comprising a step of soldering the pedestal to the second surface. 前記ピンの中央部に、はんだとの濡れ性が悪いメッキが施されていることを特徴とする請求項５から７の何れか一項に記載のはんだ実装方法。   The solder mounting method according to claim 5, wherein plating having poor wettability with solder is applied to a central portion of the pin.
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