JP2016162786A5 - - Google Patents
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- JP2016162786A5 JP2016162786A5 JP2015037512A JP2015037512A JP2016162786A5 JP 2016162786 A5 JP2016162786 A5 JP 2016162786A5 JP 2015037512 A JP2015037512 A JP 2015037512A JP 2015037512 A JP2015037512 A JP 2015037512A JP 2016162786 A5 JP2016162786 A5 JP 2016162786A5
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- Prior art keywords
- electrode
- forming
- insulating film
- semiconductor device
- opening
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- 239000004065 semiconductor Substances 0.000 claims description 35
- 230000002093 peripheral Effects 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 230000000875 corresponding Effects 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N HF Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N Silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N al2o3 Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 2
- 229910052782 aluminium Inorganic materials 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- XCCANNJCMHMXBZ-UHFFFAOYSA-N hydroxyiminosilicon Chemical compound ON=[Si] XCCANNJCMHMXBZ-UHFFFAOYSA-N 0.000 claims 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims 2
- 235000012239 silicon dioxide Nutrition 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- LDDQLRUQCUTJBB-UHFFFAOYSA-N Ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 claims 1
- 210000002381 Plasma Anatomy 0.000 claims 1
- 229910004207 SiNx Inorganic materials 0.000 claims 1
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 1
- 229910052738 indium Inorganic materials 0.000 claims 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims 1
- 229910052741 iridium Inorganic materials 0.000 claims 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 1
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 239000011733 molybdenum Substances 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 claims 1
- 229910052763 palladium Inorganic materials 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 229910052697 platinum Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000004381 surface treatment Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Description
（１０）本発明の一形態によれば、半導体装置の製造方法が提供される。この製造方法は、上面と側面とを有する台地状を成すメサ構造と、前記メサ構造の周囲に広がる周囲面とを、半導体層に形成する工程と；前記周囲面から前記側面を通じて前記上面の上方にわたって絶縁膜を形成する工程であって、前記上面の上方に形成され前記上面の端部より内側に開口部を画定する上面部と、前記側面に形成された側面部と、前記周囲面に形成された周囲部と、を有する絶縁膜を形成する工程と；ウェットエッチングによって前記絶縁膜における前記開口部を形成する工程と；前記開口部の内側から、前記上面部、前記側面部および前記周囲部の上にわたって電極を形成する工程とを備え、前記開口部を形成する工程は、前記開口部に対応する部分にマスク開口部を有するマスクを、前記絶縁膜の部位のうち、前記上面部と、前記側面部と、前記周囲部との各部の上に形成する工程と；前記マスクを形成した後、前記絶縁膜における前記マスク開口部から露出した部分をエッチャントに晒すことによって前記開口部を形成する際、前記絶縁膜と前記マスクとの間に前記エッチャントを入り込ませることによって、前記周囲部より薄い膜厚から前記上面部に向かうにつれて更に膜厚が薄くなる部分を、前記側面部に形成する工程とを含む。この形態によれば、絶縁膜に開口部を形成する工程において側面部を薄肉化できる。したがって、製造工程の煩雑化を回避しながら、絶縁破壊の防止と逆方向リーク電流の抑制とを両立可能な半導体装置を製造できる。 (10) According to an aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method includes a step of forming, on a semiconductor layer, a mesa structure having a plateau shape having an upper surface and a side surface, and a peripheral surface extending around the mesa structure; above the upper surface through the side surface from the peripheral surface Forming an insulating film over the upper surface, the upper surface portion defining an opening inside the end portion of the upper surface, the side surface portion formed on the side surface, and the peripheral surface process and to form a front KiHiraki opening in the insulating film by wet etching; process and of forming an insulating film having been and the surrounding portion, a is from the inside of the opening, said upper surface portion, said side portions and said and forming an electrode over the peripheral portion, the step of forming the opening, a mask having a mask opening in a portion corresponding to the opening, of the portion of the insulating film, before SL on surface If, before SL side surface portion, pre-process and formed on the respective parts of the distichum surrounding portion; after forming the mask, said by exposing said exposed from the mask opening in the insulating film portion in an etchant When forming the opening, by inserting the etchant between the insulating film and the mask, a portion where the film thickness is further reduced from the film thickness thinner than the peripheral part toward the upper surface part is formed on the side surface. Forming on the portion. According to this embodiment, the side surface can be thinned in the step of forming the opening in the insulating film. Therefore, it is possible to manufacture a semiconductor device that can achieve both prevention of dielectric breakdown and suppression of reverse leakage current while avoiding complicated manufacturing processes.
Claims (20)
上面と側面とを有する台地状を成すメサ構造と、前記メサ構造の周囲に広がる周囲面と、を有する半導体層と、
前記周囲面から前記側面を通じて前記上面の上方にわたって形成された絶縁膜であって、前記上面の上方に形成され前記上面の端部より内側に開口部を画定する上面部と、前記側面に形成された側面部と、前記周囲面に形成された周囲部と、を有する絶縁膜と、
前記開口部の内側から、前記上面部、前記側面部および前記周囲部の上にわたって形成された電極と
を備え、
前記側面部は、前記周囲部より薄い膜厚から前記上面部に向かうにつれて更に膜厚が薄くなる部分を、有する、半導体装置。 A semiconductor device,
A semiconductor layer having a plateau-like mesa structure having an upper surface and side surfaces, and a peripheral surface extending around the mesa structure;
An insulating film formed from the peripheral surface to the upper surface through the side surface, the upper surface portion being formed above the upper surface and defining an opening inside the end portion of the upper surface; and formed on the side surface. An insulating film having a side surface portion and a peripheral portion formed on the peripheral surface;
An electrode formed from the inside of the opening to the top surface, the side surface, and the peripheral portion;
The side surface portion has a portion where the film thickness further decreases from the film thickness thinner than the peripheral area toward the upper surface area.
前記絶縁膜は、前記周囲面から前記側面を通じて前記上面にわたって形成され、
前記電極は、前記上面のうち前記開口部から露出した部分から、前記上面部、前記側面部および前記周囲部の上にわたって一体的に形成された、半導体装置。 The semiconductor device according to claim 1 or 2, wherein
The insulating film is formed from the peripheral surface to the upper surface through the side surface,
The electrode is a semiconductor device formed integrally from a portion of the upper surface exposed from the opening to the upper surface portion, the side surface portion, and the peripheral portion.
前記電極は、第１の電極と、第２の電極とを含み、
前記第１の電極は、前記上面に形成され、
前記絶縁膜は、前記周囲面から前記側面を通じて前記第１の電極の上にわたって形成され、
前記第２の電極は、前記第１の電極のうち前記開口部から露出した部分から、前記上面部、前記側面部および前記周囲部の上にわたって一体的に形成された、半導体装置。 The semiconductor device according to claim 1 or 2, wherein
The electrode includes a first electrode and a second electrode,
The first electrode is formed on the upper surface,
The insulating film is formed on the first electrode from the peripheral surface through the side surface,
The second electrode is a semiconductor device formed integrally from a portion of the first electrode exposed from the opening to the upper surface, the side surface, and the peripheral portion.
前記半導体層は、相互に隣接するｐ型半導体層およびｎ型半導体層を含み、
前記電極は、前記上面にオーミック接合されたオーミック電極を含み、
前記側面は、前記ｐ型半導体層から前記ｎ型半導体層にわたって形成された、半導体装置。 A semiconductor device according to any one of claims 1 to 4, wherein
The semiconductor layer includes a p-type semiconductor layer and an n-type semiconductor layer adjacent to each other,
The electrode includes an ohmic electrode ohmic-bonded to the upper surface,
The side surface is a semiconductor device formed from the p-type semiconductor layer to the n-type semiconductor layer.
上面と側面とを有する台地状を成すメサ構造と、前記メサ構造の周囲に広がる周囲面とを、半導体層に形成する工程と、
前記周囲面から前記側面を通じて前記上面の上方にわたって絶縁膜を形成する工程であって、前記上面の上方に形成され前記上面の端部より内側に開口部を画定する上面部と、前記側面に形成された側面部と、前記周囲面に形成された周囲部と、を有する絶縁膜を形成する工程と、
ウェットエッチングによって前記絶縁膜における前記開口部を形成する工程と、
前記開口部の内側から、前記上面部、前記側面部および前記周囲部の上にわたって電極を形成する工程と
を備え、
前記開口部を形成する工程は、
前記開口部に対応する部分にマスク開口部を有するマスクを、前記絶縁膜の部位のうち、前記上面部と、前記側面部と、前記周囲部との各部の上に形成する工程と、
前記マスクを形成した後、前記絶縁膜における前記マスク開口部から露出した部分をエッチャントに晒すことによって前記開口部を形成する際、前記絶縁膜と前記マスクとの間に前記エッチャントを入り込ませることによって、前記周囲部より薄い膜厚から前記上面部に向かうにつれて更に膜厚が薄くなる部分を、前記側面部に形成する工程と
を含む、半導体装置の製造方法。 A method for manufacturing a semiconductor device, comprising:
Forming a plateau-shaped mesa structure having an upper surface and a side surface and a peripheral surface extending around the mesa structure in a semiconductor layer;
Forming an insulating film over the upper surface from the peripheral surface through the side surface, the upper surface portion being formed above the upper surface and defining an opening inside the end portion of the upper surface; and formed on the side surface Forming an insulating film having a side surface portion formed on the peripheral surface and a peripheral portion formed on the peripheral surface ;
Forming a front KiHiraki opening in the insulating film by wet etching,
Forming an electrode over the upper surface portion, the side surface portion, and the peripheral portion from the inside of the opening, and
The step of forming the opening includes
Forming a mask having a mask opening in a portion corresponding to the opening, of the portion of the insulating film, on the respective portions of the front SL on surface, and the front SL side surface portion, the front distichum surrounding portion When,
After forming the mask, when the opening is formed by exposing a portion of the insulating film exposed from the mask opening to an etchant, the etchant is inserted between the insulating film and the mask. And a step of forming, on the side surface portion, a portion whose film thickness is further reduced from the thinner film thickness toward the upper surface portion than the peripheral portion.
前記絶縁膜を形成する工程は、前記周囲面から前記側面を通じて前記上面にわたって前記絶縁膜を形成する工程であり、
前記電極を形成する工程は、前記上面のうち前記開口部から露出した部分から、前記上面部、前記側面部および前記周囲部の上にわたって一体的に前記電極を形成する工程である、半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 10 or 11,
The step of forming the insulating film is a step of forming the insulating film from the peripheral surface to the upper surface through the side surface,
The step of forming the electrode is a step of integrally forming the electrode from a portion of the upper surface exposed from the opening to the upper surface portion, the side surface portion, and the peripheral portion. Production method.
更に、前記絶縁膜を形成する工程に先立って、前記電極とは異なる他の電極を前記上面に形成する工程を備え、
前記絶縁膜を形成する工程は、前記他の電極を形成した後、前記周囲面から前記側面を通じて前記他の電極の上にわたって前記絶縁膜を形成する工程であり、
前記電極を形成する工程は、前記他の電極のうち前記開口部から露出した部分から、前記上面部、前記側面部および前記周囲部の上にわたって一体的に前記電極を形成する工程である、半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 10 or 11,
Furthermore, prior to the step of forming the insulating film, the method includes the step of forming another electrode different from the electrode on the upper surface,
The step of forming the insulating film is a step of forming the insulating film over the other electrode from the peripheral surface through the side surface after forming the other electrode,
The step of forming the electrode is a step of forming the electrode integrally from the portion of the other electrode exposed from the opening to the upper surface, the side surface, and the peripheral portion. Device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015037512A JP6344264B2 (en) | 2015-02-27 | 2015-02-27 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015037512A JP6344264B2 (en) | 2015-02-27 | 2015-02-27 | Semiconductor device and manufacturing method thereof |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016162786A JP2016162786A (en) | 2016-09-05 |
| JP2016162786A5 true JP2016162786A5 (en) | 2017-06-22 |
| JP6344264B2 JP6344264B2 (en) | 2018-06-20 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015037512A Active JP6344264B2 (en) | 2015-02-27 | 2015-02-27 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6344264B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7455535B2 (en) | 2019-09-11 | 2024-03-26 | 旭ダイヤモンド工業株式会社 | Super abrasive tool and method for manufacturing super abrasive tool |
| CN111403566A (en) * | 2020-03-27 | 2020-07-10 | 天津赛米卡尔科技有限公司 | Light emitting diode device structure with side wall field plate and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08139341A (en) * | 1994-11-11 | 1996-05-31 | Murata Mfg Co Ltd | Schottky barrier diode |
| CN103441140A (en) * | 2008-08-05 | 2013-12-11 | 住友电气工业株式会社 | Schottky barrier diode |
| JP6107430B2 (en) * | 2012-06-08 | 2017-04-05 | 豊田合成株式会社 | Semiconductor device |
| JP6241099B2 (en) * | 2013-07-17 | 2017-12-06 | 豊田合成株式会社 | Semiconductor device |
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