JP2015126212A - Manufacturing method and manufacturing jig of semiconductor device - Google Patents

Manufacturing method and manufacturing jig of semiconductor device Download PDF

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JP2015126212A
JP2015126212A JP2013271948A JP2013271948A JP2015126212A JP 2015126212 A JP2015126212 A JP 2015126212A JP 2013271948 A JP2013271948 A JP 2013271948A JP 2013271948 A JP2013271948 A JP 2013271948A JP 2015126212 A JP2015126212 A JP 2015126212A
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jig
semiconductor device
surrounding
substrate
manufacturing
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JP6148171B2 (en
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良宣 須原
Yoshinobu Suhara
良宣 須原
小澤　哲也
Tetsuya Ozawa
哲也 小澤
史彦 嶋津
Fumihiko Shimazu
史彦 嶋津
聡則 井浦
Satonori Iura
聡則 井浦
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Honda Motor Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method and a manufacturing jig of a semiconductor device, which allow favorable soldering even when expansion and contraction different from each other between components occur in a reflow process.SOLUTION: A manufacturing method of a semiconductor device comprises: a process S7 of arranging a surrounding jig 40 around a substrate 4; a process S9 of arranging a semiconductor chip 5 on the substrate 4 via a second solder material 8; a process S11 of a wiring member 6 on the semiconductor chip 5 via a third solder material 9; a process S12 of arranging a weight jig 50 on the wiring member 6; a process S13 of sandwiching a semiconductor device 1 with an upper jig 60 and a lower jig 20 in a vertical direction to position the surrounding jig 40 by inserting positioning pins 61a that are extended from the upper jig 60 into the surrounding jig 40; and a reflow process S14 of heating the semiconductor device 1 with the positioned surrounding jig 40 in a reflow furnace and subsequently cooling the semiconductor device 1 to melt and subsequently solidify the second solder material 8 and the third solder material 9 to perform soldering.

Description

本発明は、半導体装置の製造方法および製造治具に関する。より詳細には、実装部品が搭載された状態の半導体装置にはんだリフローを実施する半導体装置の製造方法および製造治具に関する。   The present invention relates to a semiconductor device manufacturing method and a manufacturing jig. More specifically, the present invention relates to a semiconductor device manufacturing method and a manufacturing jig for performing solder reflow on a semiconductor device on which mounted components are mounted.

従来、リフロー工程にて半導体チップをはんだ付けする際に用いる治具が知られている（例えば、特許文献１，２参照）。   Conventionally, a jig used when soldering a semiconductor chip in a reflow process is known (see, for example, Patent Documents 1 and 2).

特許文献１の治具は、上治具および下治具から構成され、半導体装置における基板、半導体チップ、はんだ材および実装部品などを挟み込んで位置決めする。この特許文献１の治具によれば、裏面側導電板の外面と表面側導電板の外面との距離を所定の値に設定し、両導電板の厚さがばらついても、ばらつきを抑制できるとされている。   The jig of Patent Document 1 includes an upper jig and a lower jig, and positions a substrate, a semiconductor chip, a solder material, a mounting component, and the like in a semiconductor device by sandwiching them. According to the jig of this patent document 1, even if the distance between the outer surface of the back-side conductive plate and the outer surface of the front-side conductive plate is set to a predetermined value and the thickness of both conductive plates varies, the variation can be suppressed. It is said that.

また、特許文献２の治具は、基板の貫通孔に導電パターンに固着した位置決め端子を貫通させるものであって、位置決め端子の孔径に変化を設けた構成である。この特許文献２の治具によれば、はんだ材の固化に伴い発生する半導体チップなどの位置ずれを吸収できるとされている。   Moreover, the jig | tool of patent document 2 is made to penetrate the positioning terminal fixed to the conductive pattern in the through-hole of the board | substrate, and is a structure which provided the change in the hole diameter of the positioning terminal. According to the jig of this patent document 2, it is supposed that the position shift of the semiconductor chip etc. which generate | occur | produces with solidification of a solder material can be absorbed.

特開２００６−２７８５９１号公報JP 2006-278591 A 特開２０１２−１２９３３６号公報JP 2012-129336 A

しかしながら、近年の半導体装置の大型化に伴い、リフロー工程にて半導体チップを押える治具とケースあるいはウォータジャケットとの熱膨張差によって部材間の伸縮が相違することが要因となり、はんだ付けが悪化する課題が生じる。例えば、半導体チップを押える治具とケースあるいはウォータジャケットとが干渉したり、半導体チップを押える治具とケースあるいはウォータジャケットとの当接部分にて応力が拡大して半導体チップのはんだ付けに不具合が発生したりする。   However, along with the recent increase in size of semiconductor devices, soldering deteriorates due to differences in expansion and contraction between members due to the difference in thermal expansion between the jig that holds the semiconductor chip and the case or water jacket in the reflow process. Challenges arise. For example, the jig that holds the semiconductor chip interferes with the case or the water jacket, or the stress increases at the contact portion between the jig holding the semiconductor chip and the case or the water jacket, causing problems in soldering the semiconductor chip. Occur.

本発明は上記課題を解決するためのものであり、その目的は、リフロー工程にて部材間に相違する伸縮が生じても良好にはんだ付けする半導体装置の製造方法および製造治具を提供することにある。   The present invention is for solving the above-described problems, and an object of the present invention is to provide a manufacturing method and a manufacturing jig of a semiconductor device that can be soldered well even when different expansion and contraction occurs between members in a reflow process. It is in.

（１） 実装部品（例えば、実施形態における基板４、半導体チップ５、配線部材６）が搭載された状態の半導体装置（例えば、実施形態における半導体装置１）にはんだリフローを実施する半導体装置の製造方法であって、基板（例えば、実施形態における基板４）の周囲に囲繞治具（例えば、実施形態における囲繞治具４０）を配置する工程（例えば、実施形態におけるステップＳ７）と、前記基板にはんだ材（例えば、実施形態における第２はんだ材８）を介在させて半導体チップ（例えば、実施形態における半導体チップ５）を配置する工程（例えば、実施形態におけるステップＳ９）と、前記半導体チップ上にはんだ材（例えば、実施形態における第３はんだ材９）を介在させて配線部材（例えば、実施形態における配線部材６）を配置する工程（例えば、実施形態におけるステップＳ１１）と、前記配線部材上に錘治具（例えば、実施形態における錘治具５０）を配置する工程（例えば、実施形態におけるステップＳ１２）と、前記半導体装置を上治具（例えば、実施形態における上治具６０）および下治具（例えば、実施形態における下治具２０）によって上下に挟み込み、前記上治具から延出された位置決めピン（例えば、実施形態における位置決めピン６１ａ）を前記囲繞治具に挿通することで、前記囲繞治具を位置決めする工程（例えば、実施形態におけるステップＳ１３）と、前記囲繞治具が位置決めされた前記半導体装置をリフロー炉内にて加熱しその後に冷却することで、はんだ材（例えば、実施形態における第２はんだ材８、第３はんだ材９）を溶融後固化してはんだ付けするリフロー工程（例えば、実施形態におけるステップＳ１４）と、を含むことを特徴とする半導体装置の製造方法。   (1) Manufacture of a semiconductor device that performs solder reflow on a semiconductor device (for example, the semiconductor device 1 in the embodiment) on which mounted components (for example, the substrate 4, the semiconductor chip 5, and the wiring member 6 in the embodiment) are mounted. A method (for example, step S7 in the embodiment) of placing an surrounding jig (for example, the surrounding jig 40 in the embodiment) around the substrate (for example, the substrate 4 in the embodiment); A step (for example, step S9 in the embodiment) of disposing a semiconductor chip (for example, the semiconductor chip 5 in the embodiment) with a solder material (for example, the second solder material 8 in the embodiment) interposed therebetween, and the semiconductor chip on the semiconductor chip A wiring member (for example, the wiring member 6 in the embodiment) with a solder material (for example, the third solder material 9 in the embodiment) interposed therebetween. A step of placing (for example, step S11 in the embodiment), a step of placing a weight jig (for example, the weight jig 50 in the embodiment) on the wiring member (for example, step S12 in the embodiment), and the semiconductor The apparatus is sandwiched up and down by an upper jig (for example, the upper jig 60 in the embodiment) and a lower jig (for example, the lower jig 20 in the embodiment), and a positioning pin (for example, The positioning pin 61a) in the embodiment is inserted into the surrounding jig to position the surrounding jig (for example, step S13 in the embodiment), and the semiconductor device in which the surrounding jig is positioned is reflowed. After melting the solder material (for example, the second solder material 8 and the third solder material 9 in the embodiment) by heating in the furnace and then cooling. And a reflow process for solidifying and soldering (for example, step S14 in the embodiment).

（１）の発明によれば、はんだ材によってはんだ付けされる基板、半導体チップおよび配線部材が上治具から延出された位置決めピンに挿通された囲繞治具に位置決めされる。このため、基板、半導体チップおよび配線部材が下治具やケースなどの他部材から離間させて固定できる。よって、リフロー工程にて基板と下治具やケースなどの他部材との熱膨張差によってこれら部材間の伸縮が相違しても、囲繞治具に位置決めされた基板、半導体チップおよび配線部材は下治具やケースなどの他部材に干渉されず、水平方向の進退を自在とする。また、囲繞治具あるいは囲繞治具に位置決めされた基板、半導体チップおよび配線部材が下治具やケースなどの他部材と当接せず影響を受けないため、当接時に拡大する応力に起因する基板、半導体チップおよび配線部材のはんだ付けの不具合は発生しない。したがって、リフロー工程にて部材間に相違する伸縮が生じても半導体装置は良好にはんだ付けできる。   According to the invention of (1), the substrate, the semiconductor chip, and the wiring member to be soldered by the solder material are positioned on the surrounding jig inserted through the positioning pins extended from the upper jig. For this reason, a board | substrate, a semiconductor chip, and a wiring member can be fixed apart from other members, such as a lower jig and a case. Therefore, even if the expansion and contraction between these members differs due to the difference in thermal expansion between the substrate and other members such as the lower jig and case in the reflow process, the substrate, semiconductor chip and wiring member positioned on the surrounding jig are The horizontal movement is free without interference with other members such as jigs and cases. In addition, the surrounding jig, the substrate positioned on the surrounding jig, the semiconductor chip, and the wiring member do not come into contact with other members such as the lower jig and the case and are not affected. There is no problem in soldering the substrate, the semiconductor chip and the wiring member. Therefore, the semiconductor device can be soldered satisfactorily even when different expansion and contraction occurs between the members in the reflow process.

（２） 実装部品（例えば、実施形態における基板４、半導体チップ５、配線部材６）が搭載された状態の半導体装置（例えば、実施形態における半導体装置１）にはんだリフローを実施する半導体装置の製造治具（例えば、製造治具１０）であって、前記実装部品が搭載される基板（例えば、実施形態における基板４）の周囲に配置される囲繞治具（例えば、実施形態における囲繞治具４０）と、はんだ材（例えば、実施形態における第２はんだ材８、第３はんだ材９）を介在させた状態で積層された前記実装部品上に配置される錘治具（例えば、実施形態における錘治具５０）と、前記半導体装置を上下に挟み込む上治具（例えば、実施形態における上治具６０）および下治具（例えば、実施形態における下治具２０）と、前記上治具から延出され、前記囲繞治具に挿通されることで、前記囲繞治具を位置決めする位置決めピン（例えば、実施形態における位置決めピン６１ａ）と、を備え、前記半導体装置とともにリフロー炉内に投入されることを特徴とする半導体装置の製造治具。   (2) Manufacture of a semiconductor device that performs solder reflow on a semiconductor device (for example, the semiconductor device 1 in the embodiment) on which mounted components (for example, the substrate 4, the semiconductor chip 5, and the wiring member 6 in the embodiment) are mounted. A jig (for example, a manufacturing jig 10), and an surrounding jig (for example, the surrounding jig 40 in the embodiment) disposed around a substrate (for example, the substrate 4 in the embodiment) on which the mounting component is mounted. ) And a solder jig (e.g., the second solder material 8 and the third solder material 9 in the embodiment) and a weight jig (e.g. A jig 50), an upper jig (for example, the upper jig 60 in the embodiment) and a lower jig (for example, the lower jig 20 in the embodiment) that sandwich the semiconductor device up and down, and the upper jig A positioning pin (for example, the positioning pin 61a in the embodiment) for positioning the surrounding jig by being extended and inserted into the surrounding jig, and put into the reflow furnace together with the semiconductor device A semiconductor device manufacturing jig.

（２）の発明によれば、（１）の発明と同様な作用・効果を奏する。   According to the invention of (2), there are the same operations and effects as the invention of (1).

本発明によれば、リフロー工程にて部材間に相違する伸縮が生じても良好にはんだ付けする半導体装置の製造方法および製造治具を提供できる。   According to the present invention, it is possible to provide a semiconductor device manufacturing method and a manufacturing jig that can be soldered satisfactorily even if different stretching occurs between members in the reflow process.

本発明の実施形態に係る半導体装置を示す図であり、図１（ａ）が分解斜視図であり、図１（ｂ）が全体斜視図である。1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is an exploded perspective view and FIG. 1B is an overall perspective view. 上記実施形態に係る半導体装置の製造治具を示す分解斜視図である。It is a disassembled perspective view which shows the manufacturing jig of the semiconductor device which concerns on the said embodiment. 上記実施形態に係る半導体装置の製造治具の使用状態を示す断面図である。It is sectional drawing which shows the use condition of the manufacturing jig of the semiconductor device which concerns on the said embodiment. 上記実施形態に係る半導体装置の製造方法におけるリフローの実施手順を示すフローチャートである。It is a flowchart which shows the implementation procedure of the reflow in the manufacturing method of the semiconductor device which concerns on the said embodiment.

以下、本発明の実施形態について、図面を参照しながら詳しく説明する。
先ず、本実施形態に係る半導体装置１を説明する。
図１は、本実施形態に係る半導体装置１を示す図であり、図１（ａ）が分解斜視図であり、図１（ｂ）が全体斜視図である。
図１に示すように、半導体装置１は、ウォータジャケット２と、ケース３と、基板４と、半導体チップ５と、配線部材６と、を備える。
半導体装置１は、半導体装置１の底部を構成するウォータジャケット２とウォータジャケット２の周縁部を囲ったケース３との内部に、複数の基板４上にそれぞれ半導体チップ５および配線部材６をこの順に積層して有する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the semiconductor device 1 according to the present embodiment will be described.
1A and 1B are diagrams showing a semiconductor device 1 according to the present embodiment, in which FIG. 1A is an exploded perspective view and FIG. 1B is an overall perspective view.
As shown in FIG. 1, the semiconductor device 1 includes a water jacket 2, a case 3, a substrate 4, a semiconductor chip 5, and a wiring member 6.
In the semiconductor device 1, a semiconductor chip 5 and a wiring member 6 are arranged in this order on a plurality of substrates 4 in a water jacket 2 that constitutes the bottom of the semiconductor device 1 and a case 3 that surrounds the periphery of the water jacket 2. Have stacked.

ウォータジャケット２は、内部に冷却水を流通させることで、半導体チップ５の発熱が伝熱された基板４を冷却する。ウォータジャケット２は、矩形平板状であり、半導体装置１の底部を構成する。ウォータジャケット２は、内部中空であり、短手方向両端部それぞれに内部に流通させる冷却水の開口部が設けられた突出部２ａ，２ｂを有する。
ウォータジャケット２を流通する冷却水は、一方の突出部２ａから流入し、ウォータジャケット２の内部を流通する際に基板４の熱を吸熱して基板４を冷却し、水温が高まった状態で他方の突出部２ｂから流出する。 The water jacket 2 cools the substrate 4 to which the heat generated by the semiconductor chip 5 has been transferred by circulating cooling water therein. The water jacket 2 has a rectangular flat plate shape and forms the bottom of the semiconductor device 1. The water jacket 2 is hollow inside, and has projecting portions 2a and 2b provided with openings of cooling water to be circulated inside at both ends in the lateral direction.
The cooling water flowing through the water jacket 2 flows in from the one protruding portion 2a, absorbs the heat of the substrate 4 when flowing through the water jacket 2, and cools the substrate 4, while the water temperature is increased. Out of the protrusion 2b.

ケース３は、基板４、半導体チップ５および配線部材６を保護するようにウォータジャケット２の周縁部を囲う。
ケース３は、樹脂製であり、矩形平板状であるウォータジャケット２の周縁部の４辺に繋がって立設した外壁部３ａと、外壁部３ａの内部を、格納される複数の基板に合わせて仕切る仕切り部３ｂと、を有する。仕切り部３ｂは、半導体装置１の短手方向中央部において長手方向にわたって短手方向両端部に繋がる主仕切り部３ｂ１と、主仕切り部３ｂ１から半導体装置１の長手方向両端部それぞれに複数の基板４の間に延出される副仕切り部３ｂ２と、から構成される。 The case 3 surrounds the peripheral portion of the water jacket 2 so as to protect the substrate 4, the semiconductor chip 5, and the wiring member 6.
The case 3 is made of resin, and the outer wall portion 3a erected and connected to the four peripheral edges of the water jacket 2 having a rectangular flat plate shape, and the inside of the outer wall portion 3a are matched to a plurality of stored boards. And a partition part 3b for partitioning. The partition portion 3b includes a main partition portion 3b1 that is connected to both ends in the short direction over the longitudinal direction at the center portion in the short direction of the semiconductor device 1, and a plurality of substrates 4 from the main partition portion 3b1 to both ends in the longitudinal direction of the semiconductor device 1. And a sub-partition portion 3b2 extending between the two.

基板４は、半導体チップ５から発する熱を放熱させる構造を有する。
基板４は、１個の半導体装置１内において複数分割され、半導体装置１のサイズに対して小型であり、ウォータジャケット２上に複数個搭載される。基板４は、例えばＣｕなどの金属板とこの金属板を挟み込んだ例えばセラミックなどの絶縁体とからなるサンドイッチ構造であり、ウォータジャケット２と半導体チップ５とを絶縁する。基板４は、ウォータジャケット２との当接面（下面）にてウォータジャケット２に伝熱可能にウォータジャケット２上にはんだ付けされる。 The substrate 4 has a structure for radiating heat generated from the semiconductor chip 5.
The substrate 4 is divided into a plurality of parts in one semiconductor device 1, is small with respect to the size of the semiconductor device 1, and is mounted on the water jacket 2. The substrate 4 has a sandwich structure composed of a metal plate such as Cu and an insulator such as ceramic sandwiching the metal plate, and insulates the water jacket 2 and the semiconductor chip 5 from each other. The substrate 4 is soldered onto the water jacket 2 so that heat can be transferred to the water jacket 2 at the contact surface (lower surface) with the water jacket 2.

半導体チップ５は、車両制御などに用いられる例えばＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）などの半導体スイッチング素子である。半導体チップ５は、１枚の基板４上に１〜３個配置される。
半導体チップ５は、基板４の金属板と伝熱可能に基板４上にはんだ付けされる。 The semiconductor chip 5 is a semiconductor switching element such as an IGBT (Insulated Gate Bipolar Transistor) used for vehicle control. One to three semiconductor chips 5 are arranged on one substrate 4.
The semiconductor chip 5 is soldered onto the substrate 4 so as to transfer heat to the metal plate of the substrate 4.

配線部材６は、半導体チップ５あるいは基板４とケース３の導電部とを接続する。配線部材６は、導電性金属製であり、半導体チップ５上あるいは基板４上に配置される。配線部材６は、半導体チップ５上または基板４上にはんだ付けされる。   The wiring member 6 connects the semiconductor chip 5 or the substrate 4 and the conductive portion of the case 3. The wiring member 6 is made of a conductive metal and is disposed on the semiconductor chip 5 or the substrate 4. The wiring member 6 is soldered on the semiconductor chip 5 or the substrate 4.

次に、本実施形態に係る半導体製造方法を説明する。
半導体製造方法は、先ず、複数の半導体チップ５それぞれの単体検査を行う。次に、複数個の半導体チップ５を搭載する大型の半導体装置１を一括ではんだリフローする。はんだリフローするリフロー工程は、ウォータジャケット２と基板４との間、基板４と半導体チップ５との間および半導体チップ５と配線部材６との間の３層のはんだ付けの接合工程を集約したものである。半導体装置１のリフロー工程の完了後に、半導体装置１に他のゲル接合工程を行い、半導体装置１に制御基板を組み付け、半導体装置１の機能検査を行う。 Next, the semiconductor manufacturing method according to the present embodiment will be described.
In the semiconductor manufacturing method, first, a single inspection of each of the plurality of semiconductor chips 5 is performed. Next, the large-sized semiconductor device 1 on which a plurality of semiconductor chips 5 are mounted is reflowed in a batch. The reflow process for solder reflow is a combination of the soldering joining process of three layers between the water jacket 2 and the substrate 4, between the substrate 4 and the semiconductor chip 5, and between the semiconductor chip 5 and the wiring member 6. It is. After completion of the reflow process of the semiconductor device 1, another gel bonding process is performed on the semiconductor device 1, a control board is assembled to the semiconductor device 1, and a function test of the semiconductor device 1 is performed.

次に、本実施形態に係る半導体装置１のリフロー工程にて使用する製造治具１０を説明する。
図２は、本実施形態に係る半導体装置１の製造治具１０を示す分解斜視図である。図３は、本実施形態に係る半導体装置１の製造治具１０の使用状態を示す断面図である。
製造治具１０は、下治具２０と、矯正治具３０と、囲繞治具４０と、錘治具５０と、上治具６０と、を備える。また、製造治具１０は、第１固定ピン７１と、第２固定ピン７２と、を有する。
製造治具１０は、半導体装置１を下治具２０および矯正治具３０に配置し、基板４を囲繞部材４１にて囲繞し、錘治具５０を囲繞治具４０で位置決めしつつ半導体装置１に載置し、上治具６０と下治具２０とによって半導体装置１を上下に挟み込み、囲繞治具４０を上治具６０によって位置決めする。 Next, the manufacturing jig 10 used in the reflow process of the semiconductor device 1 according to the present embodiment will be described.
FIG. 2 is an exploded perspective view showing the manufacturing jig 10 of the semiconductor device 1 according to the present embodiment. FIG. 3 is a cross-sectional view showing a usage state of the manufacturing jig 10 of the semiconductor device 1 according to the present embodiment.
The manufacturing jig 10 includes a lower jig 20, a correction jig 30, a surrounding jig 40, a weight jig 50, and an upper jig 60. Further, the manufacturing jig 10 includes a first fixing pin 71 and a second fixing pin 72.
In the manufacturing jig 10, the semiconductor device 1 is disposed on the lower jig 20 and the correction jig 30, the substrate 4 is surrounded by the surrounding member 41, and the weight jig 50 is positioned by the surrounding jig 40 while the semiconductor device 1 is positioned. The semiconductor device 1 is sandwiched up and down by the upper jig 60 and the lower jig 20, and the surrounding jig 40 is positioned by the upper jig 60.

下治具２０は、図示しない載置台上に載置される基礎部材である。
下治具２０は、半導体装置１を載置する矩形平板状のベース部材２１から構成される。ベース部材２１は、４隅にクランプ２２を有する。 The lower jig 20 is a basic member that is placed on a placement table (not shown).
The lower jig 20 includes a rectangular flat base member 21 on which the semiconductor device 1 is placed. The base member 21 has clamps 22 at four corners.

矯正治具３０は、下治具２０であるベース部材２１に載置された半導体装置１を抑えて半導体装置１の姿勢を矯正する。矯正治具３０は、矯正部材３１から構成される。   The correction jig 30 corrects the posture of the semiconductor device 1 by suppressing the semiconductor device 1 placed on the base member 21 that is the lower jig 20. The correction jig 30 includes a correction member 31.

矯正部材３１は、中央に矩形孔部３１ａを有する平板部３１ｂと、平板部３１ｂをベース部材２１から持ち上げるように平板部３１ｂの４隅に立設した脚部３１ｃと、を有する。矯正部材３１は、脚部３１ｃをベース部材２１上に載置して脚部３１ｃをベース部材２１のクランプ２２によってクランプされて保持される。矯正部材３１は、半導体装置１を矩形孔部３１ａ内において複数箇所の並列した長手方向位置にて半導体装置１の中央の反りを抑える平板部３１ｂの短手方向両端部に掛け渡された複数本の細棒部３１ｄを有する。複数本の細棒部３１ｄは、矯正部材３１の平板部３１ｂの短手方向両端部側にて下方に延出する両側の鉛直棒部と、両側の鉛直棒部の下端から短手方向中央部側に水平方向に延出する水平棒部と、から構成される。矯正部材３１は、平板部３１ｂの下面から下方に延出されて半導体装置１の外周部の反りを抑える複数本の抑棒部３１ｅを有する。抑棒部３１ｅは、平板部３１ｂに対してスライド可能な軸と、この軸に介装されるスプリングと、から構成される。   The correction member 31 includes a flat plate portion 31b having a rectangular hole portion 31a at the center, and leg portions 31c erected at the four corners of the flat plate portion 31b so as to lift the flat plate portion 31b from the base member 21. The correction member 31 is placed with the leg portion 31 c placed on the base member 21, and the leg portion 31 c is clamped and held by the clamp 22 of the base member 21. The correction member 31 includes a plurality of the semiconductor devices 1 that are stretched over both ends in the short direction of the flat plate portion 31b that suppresses warping of the center of the semiconductor device 1 at a plurality of parallel longitudinal positions in the rectangular hole portion 31a. The thin rod portion 31d. The plurality of thin rod portions 31d are vertically vertically extending from both ends of the flat plate portion 31b of the correction member 31 to the lower side, and from the lower ends of the vertical rod portions on both sides to the center portion in the width direction. And a horizontal bar portion extending horizontally on the side. The correction member 31 has a plurality of depressing bar portions 31 e that extend downward from the lower surface of the flat plate portion 31 b and suppress warping of the outer peripheral portion of the semiconductor device 1. The restraining bar portion 31e includes a shaft that can slide with respect to the flat plate portion 31b, and a spring that is interposed on the shaft.

矯正部材３１は、下治具２０であるベース部材２１に対して平板部３１ｂの長手方向中央部かつ短手方向一端部側の１箇所の第１固定ピン７１で固定される（図２、図３参照）。
製造治具１０に配置される半導体装置１のウォータジャケット２は、ベース部材２１の上面において第１固定ピン７１と同じ側にて同様にベース部材２１の長手方向中央部かつ短手方向一端部側の１箇所の第２固定ピン７２でケース３ごと固定される（図３参照）。
上治具６０および下治具２０が１箇所の第１固定ピン７１によって固定され、ウォータジャケット２および下治具２０が第１固定ピン７１近傍の１箇所の第２固定ピン７２によって固定されることで、上治具６０、ウォータジャケット２および下治具２０それぞれの熱膨張変化が許容される。この熱膨張変化は、第１固定ピン７１および第２固定ピン７２を起点として、上治具６０、ウォータジャケット２および下治具２０それぞれを放射状に変化させる。 The correction member 31 is fixed to the base member 21 which is the lower jig 20 by a first fixing pin 71 at one location on the side in the longitudinal center of the flat plate portion 31b and one end in the short direction (FIG. 2, FIG. 3).
The water jacket 2 of the semiconductor device 1 arranged in the manufacturing jig 10 is similarly arranged on the same side as the first fixing pin 71 on the upper surface of the base member 21 in the longitudinal direction central portion and the lateral direction one end portion side. The case 3 is fixed by one second fixing pin 72 (see FIG. 3).
The upper jig 60 and the lower jig 20 are fixed by one first fixing pin 71, and the water jacket 2 and the lower jig 20 are fixed by one second fixing pin 72 in the vicinity of the first fixing pin 71. Thus, the thermal expansion changes of the upper jig 60, the water jacket 2 and the lower jig 20 are allowed. This thermal expansion change causes the upper jig 60, the water jacket 2 and the lower jig 20 to change radially from the first fixing pin 71 and the second fixing pin 72 as starting points.

囲繞治具４０は、上治具６０から延出された位置決めピン６１ａに挿通される。囲繞治具４０は、複数の囲繞部材４１から構成される。   The surrounding jig 40 is inserted into a positioning pin 61 a extended from the upper jig 60. The surrounding jig 40 includes a plurality of surrounding members 41.

囲繞部材４１は、各基板４より一回り大きい形状である。囲繞部材４１は、縦孔部４１ａと、位置決め部としての丸穴４１ｂと、を有する、縦孔部４１ａは、錘部材５１を配置可能な矩形の空間部であり、基板４上の半導体チップ５の数に合わせた数設けられる。丸穴４１ｂは、２本の位置決めピン６１ａによって位置決めされるように囲繞部材４１の厚肉部に２箇所設けられる。丸穴４１ｂは、位置決めピン６１ａの先端を挿通時に差し込めるように円錐状である。囲繞部材４１ごとの２箇所の丸穴４１ｂは、少なくとも所定距離隔てて設けられる。囲繞部材４１は、２箇所の丸穴４１ｂが少なくとも所定距離隔てられることで、回動を禁止される。囲繞部材４１は、２本の位置決めピン６１ａを丸穴４１ｂに挿通することで２点支持され、上治具６０と一体的に上治具６０の熱膨張の伸縮に応じて回動せずに移動する。   The surrounding member 41 has a shape that is slightly larger than each substrate 4. The surrounding member 41 has a vertical hole portion 41 a and a round hole 41 b as a positioning portion. The vertical hole portion 41 a is a rectangular space portion in which the weight member 51 can be arranged, and the semiconductor chip 5 on the substrate 4. The number is set according to the number of. Two round holes 41b are provided in the thick part of the surrounding member 41 so as to be positioned by the two positioning pins 61a. The round hole 41b has a conical shape so that the tip of the positioning pin 61a can be inserted during insertion. The two round holes 41b for each surrounding member 41 are provided at least a predetermined distance apart. The surrounding member 41 is prohibited from rotating by the two round holes 41b being separated by at least a predetermined distance. The surrounding member 41 is supported at two points by inserting the two positioning pins 61a through the round holes 41b, and does not rotate integrally with the upper jig 60 according to the expansion and contraction of the thermal expansion of the upper jig 60. Moving.

図３に示すように、囲繞部材４１の外周部には、囲繞部材４１にて被覆される基板４の外周縁を固定するために下方に突出した少なくとも１対の爪４１ｃを有する。少なくとも１対の爪４１ｃは、基板４の外周縁の対向辺を引っ掛けて固定するように基板４の両側に１個ずつ設けられる。基板４は、小型であり熱膨張による伸縮が少ないため、リフロー時に少なくとも１対の爪４１ｃに固定された状態で熱膨張による割れの発生が抑制される。
囲繞部材４１とケース３との間の距離は、リフロー時に予想される上治具６０の伸びの距離以上に設定され、囲繞部材４１とケース３とが熱膨張時であっても接触しない。 As shown in FIG. 3, the outer peripheral portion of the surrounding member 41 has at least one pair of claws 41 c protruding downward in order to fix the outer peripheral edge of the substrate 4 covered with the surrounding member 41. At least one pair of claws 41 c is provided on each side of the substrate 4 so as to hook and fix the opposite sides of the outer peripheral edge of the substrate 4. Since the board | substrate 4 is small and there is little expansion-contraction by thermal expansion, generation | occurrence | production of the crack by thermal expansion is suppressed in the state fixed to at least 1 pair of nail | claw 41c at the time of reflow.
The distance between the surrounding member 41 and the case 3 is set to be equal to or longer than the extension distance of the upper jig 60 expected at the time of reflow, and the surrounding member 41 and the case 3 do not come into contact with each other even during thermal expansion.

錘治具５０は、はんだ材を介在させた状態で積層された配線部材６上に配置される。錘治具５０は、囲繞部材４１に囲繞される複数の錘部材５１を有する。   The weight jig 50 is disposed on the wiring member 6 stacked with a solder material interposed. The weight jig 50 has a plurality of weight members 51 surrounded by the surrounding member 41.

錘部材５１は、囲繞部材４１の縦孔部４１ａ内に配置される矩形柱状である。錘部材５１は、１個の半導体チップ５ごとに配置される。このため、錘部材５１は、例えば基板４上に３つの半導体チップ５が搭載される場合には、この３個の半導体チップ５上の配線部材６上にそれぞれ３個の錘部材５１が配置される。錘部材５１は、下部を囲繞部材４１の縦孔部４１ａ内に格納されることで、倒れ難くなる。
錘部材５１は、カバー５２を有する。カバー５２は、半導体チップ５表面の例えば信号パッド部などのはんだ付着禁止領域を被覆し、リフロー時のはんだ付着を防止する。 The weight member 51 has a rectangular columnar shape disposed in the vertical hole portion 41 a of the surrounding member 41. The weight member 51 is disposed for each semiconductor chip 5. Therefore, for example, when three semiconductor chips 5 are mounted on the substrate 4, the three weight members 51 are arranged on the wiring members 6 on the three semiconductor chips 5. The Since the weight member 51 is stored in the vertical hole portion 41a of the surrounding member 41 at the lower portion, it is difficult for the weight member 51 to fall down.
The weight member 51 has a cover 52. The cover 52 covers a solder adhesion prohibition region such as a signal pad portion on the surface of the semiconductor chip 5 to prevent solder adhesion during reflow.

錘部材５１としては、スライド式カバー錘部材５１ａおよびモノブロックカバー錘部材５１ｂの２種類が存在する。図３左側の錘部材５１がスライド式カバー錘部材５１ａであり、図３右側の錘部材５１がモノブロックカバー錘部材５１ｂである。   There are two types of weight members 51: a sliding cover weight member 51a and a monoblock cover weight member 51b. The weight member 51 on the left side of FIG. 3 is a sliding cover weight member 51a, and the weight member 51 on the right side of FIG. 3 is a monoblock cover weight member 51b.

スライド式カバー錘部材５１ａは、配線部材６に載置される直方体状の本体５３と、本体５３側方の半導体チップ５領域に設けられたスライド式カバー部５４と、を有する。スライド式カバー部５４は、本体５３の側面に突出した軸受５３ａを通してスライド自在な軸部５５と、軸部５５の下端部に設けられたカバー５２ａと、軸部５５の上端部に設けられた落下防止用のストッパ５６と、を有する。スライド式カバー部５４のカバー５２ａは、軸部５５を本体５３に対してスライドさせることで、本体５３の載置された配線部材６よりも下方の半導体チップ５表面のはんだ付着禁止領域に押し付けられる。   The sliding cover weight member 51 a includes a rectangular parallelepiped main body 53 placed on the wiring member 6, and a sliding cover portion 54 provided in the semiconductor chip 5 region on the side of the main body 53. The slide type cover part 54 includes a shaft part 55 slidable through a bearing 53 a protruding from the side surface of the main body 53, a cover 52 a provided at the lower end part of the shaft part 55, and a drop provided at the upper end part of the shaft part 55. And a stopper 56 for prevention. The cover 52a of the slide type cover portion 54 is pressed against the solder adhesion prohibition region on the surface of the semiconductor chip 5 below the wiring member 6 on which the main body 53 is placed by sliding the shaft portion 55 with respect to the main body 53. .

モノブロックカバー錘部材５１ｂは、直方体状であり、カバー５２ｂを本体５３と一体化して有する。カバー５２ｂは、配線部材６に載置された本体５３の側方から本体５３の下面が載置された配線部材６よりも下方の半導体チップ５表面に対面して下方に突出し、カバー５２ｂの突出面とはんだ付着禁止領域との間がリフロー時にはんだ飛沫を入り込ませない所定隙間に設定される。   The monoblock cover weight member 51 b has a rectangular parallelepiped shape, and has a cover 52 b integrated with the main body 53. The cover 52b protrudes downward from the side of the main body 53 placed on the wiring member 6 so as to face the surface of the semiconductor chip 5 below the wiring member 6 on which the lower surface of the main body 53 is placed. A predetermined gap is set between the surface and the solder adhesion prohibited area so that solder splash does not enter during reflow.

上治具６０は、下治具２０とともに半導体装置１を上下に挟み込む。上治具６０は、下治具２０と同一の線膨張率を有する材料で構成される。
上治具６０は、矯正部材３１の中央の矩形孔部３１ａに配置されるとともに囲繞部材４１を位置決めする位置決めピン６１ａを有する連携部材６１と、連携部材６１の中央の矩形孔部６１ｂに配置される遮熱部材６２と、を有する。 The upper jig 60 sandwiches the semiconductor device 1 with the lower jig 20 up and down. The upper jig 60 is made of a material having the same linear expansion coefficient as that of the lower jig 20.
The upper jig 60 is disposed in the rectangular hole 31a in the center of the correction member 31 and is disposed in the cooperation member 61 having a positioning pin 61a for positioning the surrounding member 41 and the rectangular hole 61b in the center of the cooperation member 61. And a heat shield member 62.

連携部材６１は、囲繞部材４１を位置決めする。
連携部材６１は、矯正部材３１の矩形孔部３１ａの形状を有し、矯正部材３１の矩形孔部３１ａの内壁下部において突出した段部３１ａ１に引っ掛けられ、矩形孔部３１ａを塞ぐ。連携部材６１は、各囲繞部材４１の２箇所の丸穴４１ｂそれぞれに挿通されるように位置決めピン６１ａを有する。位置決めピン６１ａは、丸棒状で先端を尖らせた尖頭型であり、位置決めピン６１ａ挿通時の先端のずれを円錐型の丸穴４１ｂの半径距離の範囲内において囲繞部材４１を丸穴４１ｂの中心に位置補正する。連携部材６１は、中央に矩形孔部６１ｂを有する。 The cooperation member 61 positions the surrounding member 41.
The cooperation member 61 has the shape of the rectangular hole portion 31a of the correction member 31, and is hooked by the step portion 31a1 protruding at the inner wall lower portion of the rectangular hole portion 31a of the correction member 31, thereby closing the rectangular hole portion 31a. The linking member 61 has positioning pins 61a so as to be inserted through the two round holes 41b of each surrounding member 41. The positioning pin 61a is a round bar shape with a pointed tip, and the displacement of the tip when the positioning pin 61a is inserted is within the range of the radial distance of the conical round hole 41b. Correct the position to the center. The cooperation member 61 has a rectangular hole 61b in the center.

遮熱部材６２は、半導体装置１の上面がリフロー炉内の上側ヒータから過熱されることを防止する。
遮熱部材６２は、連携部材６１の矩形孔部６１ｂの形状を有し、連携部材６１の矩形孔部６１ｂの内側面下部において突出した段部に引っ掛けられ、矩形孔部６１ｂを塞ぐ。 The heat shield member 62 prevents the upper surface of the semiconductor device 1 from being overheated by the upper heater in the reflow furnace.
The heat shield member 62 has the shape of the rectangular hole 61b of the linkage member 61, and is hooked on a stepped portion that protrudes at the lower part of the inner surface of the rectangular hole 61b of the linkage member 61, thereby closing the rectangular hole 61b.

次に、本実施形態に係る半導体装置１の製造方法におけるリフローの実施手順の詳細を説明する。
図４は、本実施形態に係る半導体装置１の製造方法におけるリフローの実施手順を示すフローチャートである。 Next, details of the reflow procedure in the method for manufacturing the semiconductor device 1 according to the present embodiment will be described.
FIG. 4 is a flowchart showing a reflow execution procedure in the method for manufacturing the semiconductor device 1 according to the present embodiment.

図４に示すように、ステップＳ１では、下治具２０であるベース部材２１を、載置台上に配置する。   As shown in FIG. 4, in step S1, the base member 21, which is the lower jig 20, is placed on the mounting table.

ステップＳ２では、ウォータジャケット２を、ベース部材２１上に配置する。ウォータジャケット２は、ベース部材２１上の第２固定ピン７２を、ウォータジャケット２の長手方向中央部かつ短手方向一端部側の１箇所の孔部２ｃに挿通されることで、ベース部材２１上に位置決めされる。   In step S <b> 2, the water jacket 2 is disposed on the base member 21. The water jacket 2 is inserted on the base member 21 by inserting the second fixing pin 72 on the base member 21 into the hole 2c at one central portion in the longitudinal direction of the water jacket 2 and one end in the short direction. Is positioned.

ステップＳ３では、ケース３を、ウォータジャケット２上に配置する。ケース３は、ウォータジャケット２に挿通されたベース部材２１上の第２固定ピン７２を、ケース３の外壁部３ａにおける長手方向中央部かつ短手方向一端部側の１箇所の孔部３ｃに挿通されることで、ベース部材２１上かつウォータジャケット２上に位置決めされる。   In step S <b> 3, the case 3 is placed on the water jacket 2. The case 3 inserts the second fixing pin 72 on the base member 21 inserted through the water jacket 2 into one hole 3c on the outer wall 3a of the case 3 in the longitudinal center and one end in the lateral direction. By doing so, it is positioned on the base member 21 and the water jacket 2.

ステップＳ４では、矯正部材３１を、ケース３内に後から配置される基板４、半導体チップ５および配線部材６の実装部品がこの順に積層されたウォータジャケット２の周囲を囲繞できるように配置する。この際、矯正部材３１の５本の細棒部３１ｄが配線部材６よりも上側の空間に配置される。矯正部材３１の配置後、矯正部材３１の４本の脚部３１ｃそれぞれを、ベース部材２１上の各クランプ２２によってクランプする。   In step S4, the correction member 31 is arranged so as to surround the periphery of the water jacket 2 in which mounting components of the substrate 4, the semiconductor chip 5 and the wiring member 6 to be arranged later in the case 3 are laminated in this order. At this time, the five thin rod portions 31 d of the correction member 31 are arranged in the space above the wiring member 6. After the correction member 31 is arranged, each of the four legs 31 c of the correction member 31 is clamped by each clamp 22 on the base member 21.

ステップＳ５では、第１はんだ材７を、ウォータジャケット２上に配置する。   In step S <b> 5, the first solder material 7 is disposed on the water jacket 2.

ステップＳ６では、第１はんだ材７を介して複数個の基板４を、ウォータジャケット２上であってケース３の仕切り部３ｂ間のそれぞれの空間に配置する。   In step S <b> 6, the plurality of substrates 4 are arranged on the water jacket 2 through the first solder material 7 in the spaces between the partition portions 3 b of the case 3.

ステップＳ７では、囲繞部材４１を、配線部材６および半導体チップ５が縦孔部４１ａ内に格納されるように基板４上を被覆し、囲繞部材４１の少なくとも１対の爪４１ｃを基板４の対向辺それぞれに引っ掛けて固定する。囲繞部材４１は、位置決めピン６１ａに挿通される丸穴４１ｂの移動によって位置補正されるため、基板４を移動させることなくラフに配置できる。囲繞部材４１とケース３との間の距離は、リフロー時に予想される矯正部材３１などの上治具６０の伸びの距離以上の間隙になる。   In step S7, the surrounding member 41 is covered on the substrate 4 so that the wiring member 6 and the semiconductor chip 5 are stored in the vertical hole portion 41a, and at least one pair of claws 41c of the surrounding member 41 is opposed to the substrate 4. Hang on each side and fix. Since the position of the surrounding member 41 is corrected by the movement of the round hole 41b inserted through the positioning pin 61a, the surrounding member 41 can be arranged roughly without moving the substrate 4. The distance between the surrounding member 41 and the case 3 is a gap equal to or longer than the extension distance of the upper jig 60 such as the correction member 31 expected at the time of reflow.

ステップＳ８は、第２はんだ材８を、複数個の基板４それぞれの上に配置する。   In step S <b> 8, the second solder material 8 is disposed on each of the plurality of substrates 4.

ステップＳ９では、第２はんだ材８を介して複数の半導体チップ５それぞれを、複数個の基板４それぞれの対応位置に配置する。   In step S <b> 9, each of the plurality of semiconductor chips 5 is disposed at a corresponding position of each of the plurality of substrates 4 via the second solder material 8.

ステップＳ１０では、第３はんだ材９を、複数の半導体チップ５それぞれの上に配置する。   In step S <b> 10, the third solder material 9 is disposed on each of the plurality of semiconductor chips 5.

ステップＳ１１では、第３はんだ材９を介して複数の配線部材６それぞれを、複数の半導体チップ５それぞれの上に配置する。   In step S <b> 11, each of the plurality of wiring members 6 is disposed on each of the plurality of semiconductor chips 5 via the third solder material 9.

ステップＳ１２では、錘部材５１を、囲繞部材４１の縦孔部４１ａ内かつ配線部材６上に配置する。   In step S <b> 12, the weight member 51 is disposed in the vertical hole portion 41 a of the surrounding member 41 and on the wiring member 6.

ステップＳ１３では、連携部材６１を、矯正部材３１の矩形孔部３１ａに配置する。連携部材６１が矯正部材３１の矩形孔部３１ａに配置されると、連携部材６１の複数本の位置決めピン６１ａが複数個の囲繞部材４１それぞれの２箇所の丸穴４１ｂに挿通される。このとき、囲繞部材４１は、丸穴４１ｂに挿通される位置決めピン６１ａによって丸穴４１ｂの半径距離の範囲内において丸穴４１ｂの中心に位置補正される。
続いて、上治具６０である遮熱部材６２を、連携部材６１の矩形孔部６１ｂに配置する。 In step S <b> 13, the cooperation member 61 is disposed in the rectangular hole 31 a of the correction member 31. When the cooperation member 61 is disposed in the rectangular hole 31 a of the correction member 31, the plurality of positioning pins 61 a of the cooperation member 61 are inserted into the two round holes 41 b of each of the plurality of surrounding members 41. At this time, the position of the surrounding member 41 is corrected to the center of the round hole 41b within the radius distance of the round hole 41b by the positioning pin 61a inserted through the round hole 41b.
Subsequently, the heat shield member 62 that is the upper jig 60 is disposed in the rectangular hole 61 b of the cooperation member 61.

ステップＳ１４では、製造治具１０に保持された半導体装置１を、リフロー炉内に投入し、上側および下側のヒータ８１，８２によって加熱しその後冷却することで、はんだ材７，８，９を溶融しその後固化する。これにより、ウォータジャケット２と基板４との間、基板４と半導体チップ５との間および半導体チップ５と配線部材６との間の３層のはんだ付けの接合工程を同時に行う。
ここで、上治具６０、ウォータジャケット２および下治具２０それぞれがヒータ８１，８２の加熱によって相違した熱膨張変化（伸縮）を行う。この場合、上治具６０および下治具２０が１箇所の第１固定ピン７１によって固定され、ウォータジャケット２および下治具２０が第１固定ピン７１近傍の１箇所の第２固定ピン７２によって固定されることで、上治具６０、ウォータジャケット２および下治具２０それぞれの熱膨張変化（伸縮）は許容される。ただし、上治具６０および下治具２０は、同一の線膨張率の材料によって構成されるため、熱膨張変化（伸縮）がほぼ等しくなる。矯正部材３１を介して位置決めピン６１ａによって位置決めされた囲繞部材４１は、上治具６０の熱膨張に応じて水平方向に回動せずに移動する。囲繞部材４１に固定された基板４は、半導体装置１のサイズに比して複数個に分割されて小型であり熱膨張変化が小さいため、少なくとも１対の爪４１ｃによる固定や下面全体のウォータジャケット２との間のはんだ接合を原因として割れが発生しない。
また、リフロー炉内では、半導体チップ５表面においてはんだ材７，８，９の溶融したはんだ飛沫が発生する。しかし、半導体チップ５表面のはんだ付着禁止領域は、スライド式カバー錘部材５１ａまたはモノブロックカバー錘部材５１ｂのカバー５２ａ，５２ｂによって被覆され、はんだ飛沫の付着を防止される。 In step S14, the semiconductor device 1 held by the manufacturing jig 10 is put into a reflow furnace, heated by the upper and lower heaters 81 and 82, and then cooled, whereby the solder materials 7, 8, and 9 are changed. Melt and then solidify. Thus, the three-layer soldering joining process between the water jacket 2 and the substrate 4, between the substrate 4 and the semiconductor chip 5, and between the semiconductor chip 5 and the wiring member 6 is simultaneously performed.
Here, the upper jig 60, the water jacket 2, and the lower jig 20 perform different thermal expansion changes (expansion and contraction) due to the heating of the heaters 81 and 82. In this case, the upper jig 60 and the lower jig 20 are fixed by one first fixing pin 71, and the water jacket 2 and the lower jig 20 are fixed by one second fixing pin 72 in the vicinity of the first fixing pin 71. By fixing, the thermal expansion change (extension / contraction) of each of the upper jig 60, the water jacket 2 and the lower jig 20 is allowed. However, since the upper jig 60 and the lower jig 20 are made of a material having the same linear expansion coefficient, the thermal expansion change (expansion / contraction) is substantially equal. The surrounding member 41 positioned by the positioning pin 61 a via the correction member 31 moves without rotating in the horizontal direction according to the thermal expansion of the upper jig 60. Since the substrate 4 fixed to the surrounding member 41 is divided into a plurality of pieces and is smaller than the size of the semiconductor device 1 and is small in thermal expansion change, it is fixed by at least one pair of claws 41c and the water jacket of the entire lower surface. No cracking occurs due to the solder joint between the two.
In the reflow furnace, molten solder droplets of the solder materials 7, 8, 9 are generated on the surface of the semiconductor chip 5. However, the solder adhesion prohibition region on the surface of the semiconductor chip 5 is covered with the covers 52a and 52b of the sliding cover weight member 51a or the monoblock cover weight member 51b, thereby preventing adhesion of solder splashes.

本実施形態に係る半導体装置１の製造方法によれば、以下の効果が奏される。
はんだ材７，８，９によってはんだ付けされる基板４、半導体チップ５および配線部材６が、上治具６０から延出された位置決めピン６１ａに挿通された囲繞部材４１に囲繞されて固定される。このため、基板４、半導体チップ５および配線部材６は、下治具２０やケース３などの他部材から離間させて固定できる。よって、リフロー工程（ステップＳ１４）にて基板４が配置されたウォータジャケット２と下治具２０やケース３などの他部材との熱膨張差あるいは基板４が配置されたウォータジャケット２と上治具６０との熱膨張差によってこれら部材間の伸縮が相違しても、囲繞部材４１に固定された基板４、半導体チップ５および配線部材６は、下治具２０やケース３などの他部材に干渉されず、水平方向の進退を自在とする。また、囲繞部材４１に固定された基板４、半導体チップ５および配線部材６が下治具２０やケース３などの他部材と当接せず影響を受けないため、当接時に拡大する応力に起因する半導体チップ５のはんだ付けの不具合は発生しない。したがって、リフロー工程（ステップＳ１４）にて部材間に相違する伸縮が生じても半導体装置１は良好にはんだ付けできる。 According to the manufacturing method of the semiconductor device 1 according to the present embodiment, the following effects are exhibited.
The substrate 4, the semiconductor chip 5, and the wiring member 6 to be soldered by the solder materials 7, 8, and 9 are surrounded and fixed by the surrounding member 41 inserted through the positioning pins 61 a extended from the upper jig 60. . For this reason, the substrate 4, the semiconductor chip 5, and the wiring member 6 can be fixed apart from other members such as the lower jig 20 and the case 3. Therefore, a difference in thermal expansion between the water jacket 2 on which the substrate 4 is disposed in the reflow process (step S14) and other members such as the lower jig 20 and the case 3, or the water jacket 2 and the upper jig on which the substrate 4 is disposed. Even if the expansion and contraction between these members differs due to the difference in thermal expansion from 60, the substrate 4, the semiconductor chip 5 and the wiring member 6 fixed to the surrounding member 41 interfere with other members such as the lower jig 20 and the case 3. It is not allowed to move forward and backward in the horizontal direction. Further, since the substrate 4, the semiconductor chip 5, and the wiring member 6 fixed to the surrounding member 41 do not contact and are not affected by other members such as the lower jig 20 and the case 3, the stress is increased due to contact. The trouble of soldering of the semiconductor chip 5 to be generated does not occur. Therefore, the semiconductor device 1 can be soldered satisfactorily even when different expansion and contraction occurs between the members in the reflow process (step S14).

なお、本発明は上記実施形態に限定されるものではなく、本発明の目的を達成できる範囲での変形、改良は本発明に含まれる。
１個の囲繞部材を位置決めする位置決めピンは、２本だけでなく、２本以上であってもよい。
はんだ材は、高温鉛フリーはんだなどを用いることができ、はんだの代わりにろう材やナノＡｇなどの金属粒子を含む接合材であってもよい。
爪は、基板の対向辺に長い領域の間設けられてもよく、２対以上であってもよく、または、少なくとも１対の爪が対応する対向辺とは別の対向辺にも対応して設けられてもよい。 It should be noted that the present invention is not limited to the above-described embodiment, and modifications and improvements within the scope that can achieve the object of the present invention are included in the present invention.
The number of positioning pins for positioning one surrounding member is not limited to two, and may be two or more.
The solder material may be a high-temperature lead-free solder or the like, and may be a bonding material including a brazing material or metal particles such as nano Ag instead of the solder.
The claws may be provided between long regions on the opposite sides of the substrate, may be two or more pairs, or correspond to opposite sides different from the opposite sides to which at least one pair of claws correspond. It may be provided.

１…半導体装置
４…基板
５…半導体チップ
６…配線部材
８…第２はんだ材
９…第３はんだ材
１０…製造治具
２０…下治具
３０…囲繞治具
５０…錘治具
６０…上治具
６１ａ…位置決めピン
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 4 ... Board | substrate 5 ... Semiconductor chip 6 ... Wiring member 8 ... 2nd solder material 9 ... 3rd solder material 10 ... Manufacturing jig 20 ... Lower jig 30 ... Surrounding jig 50 ... Weight jig 60 ... Top Jig 61a ... Positioning pin

Claims (2)

実装部品が搭載された状態の半導体装置にはんだリフローを実施する半導体装置の製造方法であって、
基板の周囲に囲繞治具を配置する工程と、
前記基板にはんだ材を介在させて半導体チップを配置する工程と、
前記半導体チップ上にはんだ材を介在させて配線部材を配置する工程と、
前記配線部材上に錘治具を配置する工程と、
前記半導体装置を上治具および下治具によって上下に挟み込み、前記上治具から延出された位置決めピンを前記囲繞治具に挿通することで、前記囲繞治具を位置決めする工程と、
前記囲繞治具が位置決めされた前記半導体装置をリフロー炉内にて加熱しその後に冷却することで、はんだ材を溶融後固化してはんだ付けするリフロー工程と、を含むことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device for performing solder reflow on a semiconductor device on which a mounting component is mounted,
Placing a go jig around the substrate;
Placing a semiconductor chip with a solder material interposed in the substrate;
Arranging a wiring member with a solder material interposed on the semiconductor chip;
Placing a weight jig on the wiring member;
A step of positioning the surrounding jig by sandwiching the semiconductor device up and down by an upper jig and a lower jig, and inserting a positioning pin extending from the upper jig into the surrounding jig;
A reflow process in which the semiconductor device on which the surrounding jig is positioned is heated in a reflow furnace and then cooled, so that the solder material is melted and then solidified and soldered. Manufacturing method. 実装部品が搭載された状態の半導体装置にはんだリフローを実施する半導体装置の製造治具であって、
前記実装部品が搭載される基板の周囲に配置される囲繞治具と、
はんだ材を介在させた状態で積層された前記実装部品上に配置される錘治具と、
前記半導体装置を上下に挟み込む上治具および下治具と、
前記上治具から延出され、前記囲繞治具に挿通されることで、前記囲繞治具を位置決めする位置決めピンと、を備え、
前記半導体装置とともにリフロー炉内に投入されることを特徴とする半導体装置の製造治具。
A semiconductor device manufacturing jig for performing solder reflow on a semiconductor device on which mounted components are mounted,
An surrounding jig disposed around a substrate on which the mounting component is mounted;
A weight jig disposed on the mounting component laminated with a solder material interposed therebetween;
An upper jig and a lower jig for sandwiching the semiconductor device vertically;
A positioning pin for positioning the surrounding jig by being extended from the upper jig and being inserted through the surrounding jig,
A semiconductor device manufacturing jig, which is put into a reflow furnace together with the semiconductor device.
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